Intel Patents

Intel Corporation designs and manufactures microprocessors and chipsets for computing and communications equipment manufacturers. Its products may be found in desktops, servers, tablets, smartphones and other devices.

Intel Patents by Type

  • Intel Patents Granted: Intel patents that have been granted by the United States Patent and Trademark Office (USPTO).
  • Intel Patent Applications: Intel patent applications that are pending before the United States Patent and Trademark Office (USPTO).
  • Publication number: 20170238241
    Abstract: Described herein are techniques related to reducing scanning in a cellular network. A mobile device reduces scanning of the cellular network when coverage holes are detected and/or predicted along a route traveled by or a place visited by the mobile device. A mobile device also reduces scanning of the cellular network when the mobile device is stationary. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope and meaning of the claims.
    Type: Application
    Filed: December 6, 2016
    Publication date: August 17, 2017
    Applicant: Intel Corporation
    Inventors: Jaroslaw J. Sydir, Anthony G. Lamarca
  • Publication number: 20170237956
    Abstract: An optical micro-projection system comprising the following components: at least one laser light source (200, 400, 402, 600); at least one movable mirror (102, 103, 203) for deviating light from said light source to allow generation of images on a projection surface (104, 301, 303, 306, 603); a self mixing module for measurement of the distance (604) between the projection source and a projection surface, said self mixing module comprising:—at least one photodiode (401, 601) for monitoring the light emission power of the laser light source;—an optical power variation counter for counting optical power variations (605); successive displacements of said mirror allowing the self mixing module providing successive projection distance measurements of a plurality of points of said projection surface. A projection method for optical micro-projection system and a distance measurement method are also provided.
    Type: Application
    Filed: June 20, 2016
    Publication date: August 17, 2017
    Applicant: INTEL CORPORATION
    Inventors: LUCIO KILCHER, FAOUZI KHECHANA
  • Publication number: 20170237154
    Abstract: Embodiments of wireless antenna array systems to achieve three-dimensional beam coverage are described herein. Other embodiments may be described and claimed.
    Type: Application
    Filed: February 20, 2017
    Publication date: August 17, 2017
    Applicant: Intel Corporation
    Inventors: Debabani Choudhury, Richard D. Roberts, Ulun Karacaoglu
  • Publication number: 20170237811
    Abstract: An apparatus for compute module management is described herein. The apparatus includes a host system and a logic solution. The host system includes a central processing unit and a plurality of sensors that collect system management data from multiple interfaces. The logic solution consolidates the system management data to a single format for a single interface and transmits the system management data to a central authority. The central authority includes system management firmware for managing each compute module using the consolidated system management data.
    Type: Application
    Filed: December 21, 2016
    Publication date: August 17, 2017
    Applicant: INTEL CORPORATION
    Inventors: CHRISTOPHER NEIL BRADLEY, TERRENCE TRAUSCH
  • Publication number: 20170237671
    Abstract: Method, apparatus, and systems for implementing Quality of Service (QoS) within high performance fabrics. A multi-level QoS scheme is implemented including virtual fabrics, Traffic Classes, Service Levels (SLs), Service Channels (SCs) and Virtual Lanes (VLs). SLs are implemented for Layer 4 (Transport Layer) end-to-end transfer of fabric packets, while SCs are used to differentiate fabric packets at the Link Layer. Fabric packets are divided into flits, with fabric packet data transmitted via fabric links as flits streams. Fabric switch input ports and device receive ports detect SC IDs for received fabric packets and implement SC-to-VL mappings to determine VL buffers to buffer fabric packet flits in. An SL may have multiple SCs, and SC-to-SC mapping may be implemented to change the SC for a fabric packet as it is forwarded through the fabric, while maintaining its SL. A Traffic Class may include multiple SLs, enabling request and response traffic for an application to employ separate SLs.
    Type: Application
    Filed: May 3, 2017
    Publication date: August 17, 2017
    Applicant: Intel Corporation
    Inventors: Todd Rimmer, Thomas D. Lovett, Albert Cheng
  • Publication number: 20170235228
    Abstract: Techniques related to multi-pass patterning lithography, device structures, and devices formed using such techniques are discussed. Such techniques include exposing a resist layer disposed over a grating pattern with non-reflecting radiation to generate an enhanced exposure portion within a trench of the grating pattern and developing the resist layer to form a pattern layer having a pattern structure within the trench of the grating pattern.
    Type: Application
    Filed: September 22, 2014
    Publication date: August 17, 2017
    Applicant: Intel Corporation
    Inventors: Manish CHANDHOK, Todd R. YOUNKIN, Sang H. LEE, Charles H. WALLACE
  • Publication number: 20170237659
    Abstract: Method, apparatus, and systems for reliably transferring Ethernet packet data over a link layer and facilitating fabric-to-Ethernet and Ethernet-to-fabric gateway operations at matching wire speed and packet data rate. Ethernet header and payload data is extracted from Ethernet frames received at the gateway and encapsulated in fabric packets to be forwarded to a fabric endpoint hosting an entity to which the Ethernet packet is addressed. The fabric packets are divided into flits, which are bundled in groups to form link packets that are transferred over the fabric at the Link layer using a reliable transmission scheme employing implicit ACKnowledgements. At the endpoint, the fabric packet is regenerated, and the Ethernet packet data is de-encapsulated. The Ethernet frames received from and transmitted to an Ethernet network are encoded using 64b/66b encoding, having an overhead-to-data bit ratio of 1:32.
    Type: Application
    Filed: December 31, 2016
    Publication date: August 17, 2017
    Applicant: Intel Corporation
    Inventors: Mark S Birrittella, Thomas D. Lovett, Todd M. Rimmer
  • Publication number: 20170235575
    Abstract: A method for supporting architecture speculation in an out of order processor is disclosed. The method comprises fetching two threads into the processor, wherein a first thread executes in a speculative state and a second thread executes in a non-speculative state. The method also comprises enabling a speculative scope for an execution of the first thread and a non-speculative scope for an execution of the second thread in an architecture of the processor, wherein the speculative scope and the non-speculative scope can both be fetched into the architecture and be present concurrently.
    Type: Application
    Filed: November 16, 2016
    Publication date: August 17, 2017
    Applicant: Intel Corporation
    Inventor: Mohammad Abdallah
  • Publication number: 20170236580
    Abstract: Nonvolatile memory (e.g. phase change memory) devices, systems, and methods of programming the nonvolatile memory including dual demarcation voltage sensing before writes.
    Type: Application
    Filed: February 17, 2016
    Publication date: August 17, 2017
    Applicant: Intel Corporation
    Inventors: Daniel Chu, Kiran Pangal, Mase Taub, Sandeep Guliani, Raymond Zeng
  • Publication number: 20170235338
    Abstract: An electronic device is described herein. The electronic device includes a portable housing for the electronic device. A zipper of the portable housing is to enable access to the electronic device. Additionally, the electronic device includes a flexible display integrated into the portable housing. The zipper may enable electromagnetic interference (EMI) shielding while enclosing the electronic device and associated components within the portable form factor. In embodiments, a flexible magnetic seal may be used to enclose the electronic device and associated components within the portable form factor.
    Type: Application
    Filed: September 26, 2014
    Publication date: August 17, 2017
    Applicant: INTEL CORPORATION
    Inventors: Hong W. Wong, Wah Yiu Kwong, Cheong W. Wong, Xiaoguo Liang, Christine Kim
  • Publication number: 20170235482
    Abstract: In various embodiments, the size, shape, and arrangement of keys on a virtual keyboard may be determined based on touchscreen contacts made by the user. Further, the actual contact patch made by the user may be analyzed to interpret which point of contact was intended, and other factors such as spelling and context may also be considered. These factors may be determined based on a calibration session and/or on continuing inputs during operation of the keyboard, and applied to future operational interpretations of the touchscreen contacts.
    Type: Application
    Filed: December 31, 2016
    Publication date: August 17, 2017
    Applicant: Intel Corporation
    Inventor: Bran Ferren
  • Publication number: 20170235701
    Abstract: Techniques for embedded high speed serial interface methods are described herein. The techniques include an apparatus for sideband signaling including a first serial sideband link module and a second serial sideband link module. The first serial sideband link module is to propagate packets from an upstream port to a downstream port via a first signaling lane, and the second serial sideband link module is to propagate packets from the downstream port to the upstream port via a second signaling lane.
    Type: Application
    Filed: December 24, 2014
    Publication date: August 17, 2017
    Applicant: INTEL CORPORATION
    Inventors: Akshay Pethe, Mahesh Wagh, David Harriman, Su Wei Lim, Debendra Das Sharma, Daniel Froelich, Venkatraman Iyer, James Jaussi, Zuoguo Wu
  • Publication number: 20170236099
    Abstract: In one aspect, the invention is a computer program product residing on a computer readable medium having a plurality of instructions stored thereon. The instructions when executed by the processor, cause that processor to schedule a network-based media event; and to invite an attendee to attend the network-based media event. Other aspects of the invention includes a process and a method.
    Type: Application
    Filed: May 4, 2017
    Publication date: August 17, 2017
    Applicant: INTEL CORPORATION
    Inventors: Peter Sirotka, Don Johnson, Sudheer Tumuluru
  • Publication number: 20170236654
    Abstract: Hybrid electrochemical capacitors, electronic devices using such capacitors, and associated methods are disclosed. In an example, a hybrid electrochemical capacitor can include a first electrode made from Mg, Na, Zn, Al, Sn, or Li, a second electrode made from a porous material such as porous carbon or passivated porous silicon, and an electrolyte. The hybrid electrochemical capacitors can have enhanced voltage and energy density compared to other electrochemical capacitors, and enhanced power density compared to batteries.
    Type: Application
    Filed: April 27, 2017
    Publication date: August 17, 2017
    Applicant: Intel Corporation
    Inventors: DONALD S. GARDNER, CHUNLEI WANG, YANG LIU, ZHAOHUI CHEN, CHARLES W. HOLZWARTH, BUM KI MOON
  • Publication number: 20170236246
    Abstract: A mechanism is described for facilitating parallel scheduling of multiple commands on computing devices. A method of embodiments, as described herein, includes detecting a command of a plurality of commands to be processed at a graphics processing unit (GPU), and acquiring one or more resources of a plurality of resources to process the command. The plurality of resources may include other resources being used to process other commands of the plurality of commands. The method may further include facilitating processing of the command using the one or more resources, wherein the command is processed in parallel with processing of the other commands using the other resources.
    Type: Application
    Filed: September 12, 2014
    Publication date: August 17, 2017
    Applicant: INTEL CORPORATION
    Inventor: MICHAL ANDRZEJ MROZEK
  • Publication number: 20170236247
    Abstract: A mechanism is described for facilitating ray compression for efficient graphics data processing at computing devices. A method of embodiments, as described herein, includes forwarding a set of rays to a ray compression unit hosted by a graphics processor at a computing device, and facilitating the ray compression unit to compress the set of rays, wherein the set of rays are compressed into a compressed representation.
    Type: Application
    Filed: February 17, 2016
    Publication date: August 17, 2017
    Applicant: INTEL CORPORATION
    Inventor: TOMAS G. AKENINE-MOLLER
  • Publication number: 20170236575
    Abstract: Embodiments are generally directed to memory refresh operation with page open. An embodiment of a memory device includes a memory array including a plurality of memory banks; and a control logic to provide control operations for the memory device including a page open refresh mode, wherein the control logic is to perform a refresh cycle in response to a refresh command with a memory page of the memory array open, the refresh operation including precharge of one or more memory banks of the plurality of memory banks, refresh of the one or more memory banks, and activation of the memory page.
    Type: Application
    Filed: May 3, 2017
    Publication date: August 17, 2017
    Applicant: Intel Corporation
    Inventors: Bruce QUERBACH, Kuljit BAINS, John HALBERT
  • Publication number: 20170236566
    Abstract: Memory devices, systems, and methods that maximize command and address (CA) signal group rate with minimized margin degradation across a channel and associated operating modes are disclosed and described. In one example, the operating mode can be 1 bit per 1.5 clock cycles.
    Type: Application
    Filed: February 17, 2016
    Publication date: August 17, 2017
    Applicant: Intel Corporation
    Inventors: Pooja Nukala, Christopher Mozak, Kristina D. Morgan, Rebecca Loop
  • Publication number: 20170236499
    Abstract: Techniques are disclosed for video playback decoding surface prediction. For instance, in some embodiments, video content may be parsed for information that can be used to predict what surfaces (e.g., computer graphics shapes to be rendered, as defined by vertices specifying the location and possibly other attributes of the shape) are most likely to be accessed, for example, by a display or a graphics processing unit (GPU) in the near future. In accordance with some embodiments, these surfaces may be pre-loaded, for example, into cache memory or other desired high-bandwidth memory in advance to minimize or otherwise reduce memory access latency. In some cases, these surfaces may be entered in a list that is kept updated with each new input frame, and the surfaces in that list may be kept inside the cache (or other high-bandwidth memory) for future display or GPU access.
    Type: Application
    Filed: September 24, 2015
    Publication date: August 17, 2017
    Applicant: INTEL CORPORATION
    Inventors: NING LUO, CHANGLIANG WANG, PENNE Y. LEE
  • Patent number: 9733363
    Abstract: Devices and methods are directed to estimating a position of the device/user using a delta range measurement (DRM) module to measure a range difference between first and second range values for first and second time instants based on, e.g., carrier phase measurements. The time period between the first and second time instants may be greater than a periodic interval at which a new phase value is sampled. This architecture of the DRM module provides extended delta ranges values which also overlap in time, enabling a combination of improved dilution of precision and keeping fast generation of delta range values suitable for use in continuous filtering. A filter, e.g., a Kalman filter, may be used compute current estimates of two positions, or a combination of a position and a position difference, of the device based at least on the range difference and a priori estimate(s) of the position(s) of the device.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: August 15, 2017
    Assignee: Intel IP Corporation
    Inventor: Tomer Dahan
  • Patent number: 9733282
    Abstract: Apparatuses and methods of current balancing, current sensing and phase balancing, offset cancellation, digital to analog current converter with monotonic output using binary coded input (without binary to thermometer decoder), compensator for a voltage regulator (VR), etc. are provided here. An apparatus is provided which comprises: a plurality of inductors coupled to a capacitor and a load; a plurality of bridges, each of which is coupled to a corresponding inductor from the plurality of inductors; and a plurality of current sensors, each of which is coupled to a bridge to sense current through a transistor of the bridge.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: Gerhard Schrom, J. Keith Hodgson, Alexander Lyakhov, Chiu Keung Tang, Narayanan Raghuraman, Narayanan Natarajan
  • Patent number: 9731369
    Abstract: A solder and methods of forming an electrical interconnection are shown. Examples of solders include gallium based solders. A solder including gallium is shown that includes particles of other solders mixed with a gallium based matrix. Methods of applying a solder are shown that include swiping a solder material over a surface that includes a resist pattern. Methods of applying a solder are also shown that include applying a solder that is immersed in an acid solution that provides a fluxing function to aid in solder adhesion.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: Ting Zhong, Rajashree Raji Baskaran, Aleksandar Aleks Aleksov
  • Patent number: 9734077
    Abstract: Method and apparatus for sending packets using optimized PIO write sequences without sfences. Sequences of Programmed Input/Output (PIO) write instructions to write packet data to a PIO send memory are received at a processor supporting out of order execution. The PIO write instructions are received in an original order and executed out of order, with each PIO write instruction writing a store unit of data to a store buffer or a store block of data to the store buffer. Logic is provided for the store buffer to detect when store blocks are filled, resulting in the data in those store blocks being drained via PCIe posted writes that are written to send blocks in the PIO send memory at addresses defined by the PIO write instructions. Logic is employed for detecting the fill size of packets and when a packet's send blocks have been filled, enabling the packet data to be eligible for egress.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: Mark Debbage, Yatin M. Mutha
  • Patent number: 9733909
    Abstract: A system for an agnostic runtime architecture. The system includes a system emulation/virtualization converter, an application code converter, and a converter wherein a system emulation/virtualization converter and an application code converter implement a system emulation process, and wherein the system converter implements a system and application conversion process for executing code from a guest image, wherein the system converter or the system emulator. The system further includes a reordering process through JIT (just in time) optimization that ensures loads do not dispatch ahead of other loads that are to the same address, wherein a load will check for a same address of subsequent loads from a same thread, and a thread checking process that enable other thread store checks against the entire load queue and a monitor extension.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: August 15, 2017
    Assignee: INTEL CORPORATION
    Inventor: Mohammad Abdallah
  • Patent number: 9733689
    Abstract: Methods and apparatuses relating to transactional power management are described. In one embodiment, a hardware apparatus includes a hardware processor having a core, a plurality of power domains to transition to one of a plurality of power states in response to a power management command for each power domain, and a power transaction unit to assign a first power management command as a first power transaction and a second power management command as a second power transaction for concurrent execution, perform a commit of the first power transaction and the second power transaction when there is no conflict between the first power transaction and the second power transaction, and perform an abort of the first power transaction and a commit of the second power transaction when there is a conflict between the first power transaction and the second power transaction.
    Type: Grant
    Filed: June 27, 2015
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Nivedha Krishnakumar, Youvedeep Singh, Suketu R. Partiwala
  • Patent number: 9733858
    Abstract: A processing system is provided that includes a memory for storing an input bit stream and a processing logic, operatively coupled to the memory, to generate a first score based on: a first set of matching data related to a match between a first bit subsequence and a candidate bit subsequence within the input bit stream, and a first distance of the candidate bit subsequence from the first set of matching data. A second score is generated based on a second set of matching data related to a match between a second bit subsequence and the candidate bit subsequence, and a second distance of the candidate bit subsequence from the second set of matching data. A code to replace the first or second bit subsequence in an output bit stream is identified. Selection of the one of the bit subsequences to replace is based on a comparison of the scores.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: James D. Guilford, Vinodh Gopal, Gilbert M. Wolrich, Daniel F. Cutter
  • Patent number: 9734054
    Abstract: Methods and apparatus related to efficient implementation of geometric series are discussed herein. For example, memory stores data corresponding to a geometric series. Logic, coupled to the memory, generates a channel address based at least in part on a summation of a tag address and one or more geometric series components of the geometric series. Other embodiments are also claimed.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventor: Massimo Sutera
  • Patent number: 9734069
    Abstract: Systems and methods for multicast tree-based data distribution in a distributed shared cache. An example processing system comprises: a plurality of processing cores, each processing core communicatively coupled to a cache; a tag directory associated with caches of the plurality of processing cores; a shared cache associated with the tag directory; a processing logic configured, responsive to receiving an invalidate request with respect to a certain cache entry, to: allocate, within the shared cache, a shared cache entry corresponding to the certain cache entry; transmit, to at least one of: a tag directory or a processing core that last accessed the certain entry, an update read request with respect to the certain cache entry; and responsive to receiving an update of the certain cache entry, broadcast the update to at least one of: one or more tag directories or one or more processing cores identified by a tag corresponding to the certain cache entry.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: Simon C. Steely, Jr., William C. Hasenplaugh, Samantika S. Sury
  • Patent number: 9734263
    Abstract: Described is a method and apparatus for efficient pre-silicon validation of an integrated circuit. The method comprises: analyzing an architectural verification environment associated with a hardware description language (HDL) architecture of an integrated circuit, recognizing method calls associated with the architectural verification environment, and generating a list of recognized method calls that is loaded for a debug program to debug the HDL architecture of the integrated circuit.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: Erez Kohavi, Evgeniy Ainbinder
  • Patent number: 9735348
    Abstract: An embodiment includes a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed layers; the tunnel barrier directly contacting a first side of the free layer; and an oxide layer directly contacting a second side of the free layer; wherein the tunnel barrier includes an oxide and has a first resistance-area (RA) product and the oxide layer has a second RA product that is lower than the first RA product. The MTJ may be included in a perpendicular spin torque transfer memory. The tunnel barrier and oxide layer form a memory having high stability with an RA product not substantively higher than a less table memory having a MTJ with only a single oxide layer. Other embodiments are described herein.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: Charles C. Kuo, Kaan Oguz, Brian S. Doyle, Elijah V. Karpov, Roksana Golizadeh Mojarad, David L. Kencke, Robert S. Chau
  • Patent number: 9734359
    Abstract: A system to provide an always-on embedded anti-theft protection for a platform is described. The system comprises in one embodiment, a storage including encryption to protect data, a risk behavior logic to detect a potential problem when the data is not encrypted, a core logic component to provide logic to analyze the potential problem and to trigger a security action logic to perform the security action, when the potential problem indicates a theft suspicion, and the security action logic, to cause the platform to attempt a transition to a reduced power state when triggered by the core logic component, the transition causing the data to be encrypted.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: August 15, 2017
    Assignee: INTEL CORPORATION
    Inventor: Michael Berger
  • Patent number: 9734531
    Abstract: A technique includes using a processor-based machine to determine a dynamic interaction characteristic of a group of users. The technique further includes, based at least in part on the determined dynamic interaction characteristic, determining a profile of the group for a recommendation engine.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: August 15, 2017
    Assignee: INTEL CORPORATION
    Inventors: Rita H. Wouhaybi, Audrey C. Younkin, William C. Deleeuw
  • Patent number: 9734597
    Abstract: A mechanism is described for facilitating interpolated minimum-maximum compression/decompression for efficient processing of graphics data at computing devices. A method of embodiments, as described herein, includes detecting a tile having pixels representing graphics contents capable of being processed by a graphics processor of a computing device; computing a minimum color value and a maximum color value of the tile. The method may further include splitting the tile into a plurality of interpolation tiles, where each interpolation tile includes a set of pixels of one or more colors. The method may further include computing a plurality of local minimum color values for the plurality of interpolation tiles, computing, based on the plurality of local minimum values, a plurality of residuals for the plurality of interpolation tiles to reduce spreads from the plurality of interpolation tiles, and compressing the reduced plurality of interpolation tiles based on the plurality of residuals.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: Tomas G. Akenine-Moller, Jon N. Hasselgren, Jim K. Nilsson
  • Patent number: 9734988
    Abstract: To form a complex and fine pattern by combining optical exposure technology and charged particle beam exposure technology, provided is an exposure apparatus that radiates a charged particle beam at a position corresponding to a line pattern on a sample, including a beam generating section that generates a plurality of the charged particle beams at different irradiation positions in a width direction of the line pattern; a scanning control section that performs scanning with the irradiation positions of the charged particle beams along a longitudinal direction of the line pattern; a selecting section that selects at least one charged particle beam to irradiate the sample from among the plurality of charged particle beams, at a designated irradiation position in the longitudinal direction of the line pattern; and an irradiation control section that controls the at least one selected charged particle beam to irradiate the sample.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: August 15, 2017
    Assignee: INTEL CORPORATION
    Inventors: Akio Yamada, Shinji Sugatani, Masaki Kurokawa, Masahiro Seyama
  • Patent number: 9735270
    Abstract: A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Robert S. Chau, Tahir Ghani, Kaizad R. Mistry
  • Patent number: 9734116
    Abstract: Techniques and mechanisms for configuring an integrated circuit (IC) chip to implement a protocol stack. In an embodiment, a transaction layer of the IC chip is operable to exchange with a link layer of the IC chip transaction layer packets (TLPs) having a format compatible with one defined in a Peripheral Component Interconnect Express™ (PCIe™) specification. Configuration circuitry of the IC chip provides for configuration of a first protocol stack including the transaction layer, circuitry of the link layer and a first physical layer of the IC chip. The configuration circuitry further provides for an alternative configuration of a second protocol stack including the transaction layer, circuitry of the link layer and a second physical layer of the IC chip. In another embodiment, the first protocol stack supports single-ended signaling to communicate TLP information, whereas the second protocol stack supports differential signaling to communicate TLP information.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: Bryan L. Spry, Marcus W. Song, Deepak M. Rangaraj, Avinash N. Ananthakrishnan, Robert J. Hayes, Aimee D. Wood, Adam E. Letendre, Brent R. Boswell
  • Patent number: 9735412
    Abstract: A battery cell includes a first current collector, a cathode in electrical contact with the first current collector, and a second current collector. The second current collector includes a metal foam having a porous structure, and an electrically insulating layer on outer surfaces of the porous structure facing the cathode. The electrically insulating layer isolates the outer surfaces facing the cathode from ions provided by the cathode. The electrically insulating layer is configured to allow an electrolyte to transport ions from the cathode to an inner portion of the porous structure of the metal foam. The battery cell may further include a separator to separate the cathode and the first current collector from the second current collector. When the battery cell is in at least a partially charged state, ions form an anode including a metal plating within the inner porous structure of the metal foam.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: August 15, 2017
    Assignee: INTEL CORPORATION
    Inventors: Naoki Matsumura, Andrew W. Keates
  • Patent number: 9735747
    Abstract: Techniques related to balancing audio for mobile devices are discussed. Such techniques may include detecting a speaker of the device is at least partially obstructed, determining an audio output from the device is impeded due to the speaker being at least partially obstructed, and increasing an output from the speaker and/or an alternative speaker based on the audio output from the device being impeded.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: Tomer Rider, Shahar Taite, Igor Ljubuncic, Raphael Sack
  • Patent number: 9735765
    Abstract: Embodiments include apparatuses, methods, and systems for jitter equalization and phase error detection. In embodiments, a communication circuit may include a data path to pass a data signal and a clock path to pass a clock signal. A jitter equalizer may be coupled with the data path and/or clock path to provide a programmable delay to the data signal and/or clock signal, respectively. The delay may be determined by a training process in which a supply voltage may be modulated by a modulation frequency. The delay may be dependent on a value of the supply voltage, such as a voltage level and/or jitter frequency component of the supply voltage. A phase error detector is also described that may be used with the communication circuit and/or other embodiments.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: Nicholas P. Cowley, Chi Man Kan, Ruchir Saraswat
  • Patent number: 9735812
    Abstract: A radio frequency (RF) transceiver system comprises an input port configured to receive an RF receive signal and a receiver (RX) digital signal processing (DSP) unit configured to process a digital IF signal based on the RF receive signal and generate a processed digital IF signal at an output port based thereon. Further, the RF transceiver system comprises a digital interface unit comprising a digital interface configured to convey the processed digital IF signal from the output port. In addition, the RF transceiver system comprises a quality estimation unit configured to estimate a quality indicator of the RF receive signal or a signal associated therewith, and dynamically adapt a digital transmission word length of the processed digital IF signal over the digital interface, based on the estimated quality indicator.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: August 15, 2017
    Assignee: Intel IP Corporation
    Inventor: Stefan Helmut Schmalzl
  • Patent number: 9735813
    Abstract: Described is an apparatus for boosting a transition edge of a signal, the apparatus comprises: a logic to provide input data having a Unit Interval (UI); a programmable delay unit to receive the input data and operable to delay the input data by a fraction of the UI to generate a delayed input data; and one or more drivers to drive the input data and the delayed input data to a node.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: Shenggao Li, Xiaoqing Wang
  • Patent number: 9735819
    Abstract: A radio receiver for multiple radio network operation includes an RF unit for generating a first down-converted signal from a radio signal received from a first radio network and a second down-converted signal from a radio signal received from a second radio network. Further, it includes a first receiver comprising a paging indicator channel demodulator for demodulating a paging indicator channel of the first radio network based on the first down-converted signal, and a second receiver including a pilot channel demodulator for demodulating a pilot channel of the second radio network based on the second down-converted signal.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: August 15, 2017
    Assignee: Intel Deutschland GmbH
    Inventors: Thorsten Clevorn, Herbert Dawid, Bertram Gunzelmann
  • Patent number: 9734880
    Abstract: Embodiments include apparatuses, systems, and methods including a memory apparatus including a plurality of bit cells, wherein each of the plurality of bit cells correspond to a respective weight value and include a switch device that has a magnetic tunnel junction (MTJ) or other suitable resistive memory element to produce stochastic switching. In embodiments, the switch device may produce a switching output according to a stochastic switching probability of the switch device. In embodiments, a bit line or a source line passes a current across the MTJ for a switching time associated with the stochastic switching probability to produce the switching output which enables a determination of whether the respective weight value is to be updated. Other embodiments may also be described and claimed.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: Charles Augustine, Somnath Paul, Sadique Ul Ameen Sheik, Muhammad M. Khellah
  • Patent number: 9733935
    Abstract: A method of processing an instruction is described that includes fetching and decoding the instruction. The instruction has separate destination address, first operand source address and second operand source address components. The first operand source address identifies a location of a first mask pattern in mask register space. The second operand source address identifies a location of a second mask pattern in the mask register space. The method further includes fetching the first mask pattern from the mask register space; fetching the second mask pattern from the mask register space; merging the first and second mask patterns into a merged mask pattern; and, storing the merged mask pattern at a storage location identified by the destination address.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: Jesus Corbal, Andrew T. Forsyth, Roger Espasa, Manel Fernandez, Thomas D. Fletcher
  • Patent number: 9733937
    Abstract: A method, apparatus, and system are provided for performing compare and exchange operations using a sleep-wakeup mechanism. According to one embodiment, an instruction at a processor is executed to help acquire a lock on behalf of the processor. If the lock is unavailable to be acquired by the processor, the instruction is put to sleep until an event has occurred.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: Bratin Saha, Matthew C. Merten, Per Hammarlund
  • Patent number: 9733939
    Abstract: A processor includes a processing unit including a storage module having stored thereon a physical reference list for storing identifications of physical registers that have been referenced by multiple logical registers, and a reclamation module for reclaiming physical registers to a free list based on a count of each of the physical registers on the physical reference list.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: Vijaykumar Balaram Kadgi, James D. Hadley, Avinash Sodani, Matthew C. Merten, Morris Marden, Joseph A. McMahon, Grace C. Lee, Laura A. Knauth, Robert S. Chappell, Fariborz Tabesh
  • Patent number: 9733942
    Abstract: A hardware based translation accelerator. The hardware includes a guest fetch logic component for accessing guest instructions; a guest fetch buffer coupled to the guest fetch logic component and a branch prediction component for assembling guest instructions into a guest instruction block; and conversion tables coupled to the guest fetch buffer for translating the guest instruction block into a corresponding native conversion block. The hardware further includes a native cache coupled to the conversion tables for storing the corresponding native conversion block, and a conversion look aside buffer coupled to the native cache for storing a mapping of the guest instruction block to corresponding native conversion block, wherein upon a subsequent request for a guest instruction, the conversion look aside buffer is indexed to determine whether a hit occurred, wherein the mapping indicates the guest instruction has a corresponding converted native instruction in the native cache.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: August 15, 2017
    Assignee: INTEL CORPORATION
    Inventor: Mohammad Abdallah
  • Patent number: 9733944
    Abstract: A method for outputting reliably predictable instruction sequences. The method includes tracking repetitive hits to determine a set of frequently hit instruction sequences for a microprocessor, and out of that set, identifying a branch instruction having a series of subsequent frequently executed branch instructions that form a reliably predictable instruction sequence. The reliably predictable instruction sequence is stored into a buffer. On a subsequent hit to the branch instruction, the reliably predictable instruction sequence is output from the buffer.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: August 15, 2017
    Assignee: INTEL CORPORATION
    Inventor: Mohammad Abdallah
  • Patent number: 9733956
    Abstract: Various techniques for adjusting settings based on sensor data are described herein. In one example, a method includes detecting sensor data from a sensor and ranking the sensor data based on predetermined zones. The method can also include identifying a dominant zone from the predetermined zones, and adjusting the setting based on the dominant zone.
    Type: Grant
    Filed: December 24, 2013
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: Prasanna Krishnaswamy, Gangatharan Jothiswaran, Arvind S
  • Patent number: 9733987
    Abstract: Examples may include techniques to coordinate the sharing of resources among virtual elements, including service chains, supported by a shared pool of configurable computing resources based on relative priority among the virtual element and service chains. Information including indications of the performance of the service chains and also the relative priority of the service chains may be received. The resource allocation of portions of the shared pool of configurable computing resources supporting the service chains can be adjusted based on the received performance and priority information.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: August 15, 2017
    Assignee: INTEL CORPORATION
    Inventors: Andrew J. Herdrich, Kapil Sood, Nrupal R. Jani, David J. Harriman, Mesut A. Ergin, Scott P. Dubal, Ravishankar Iyer