Intel Patents

Intel Corporation designs and manufactures microprocessors and chipsets for computing and communications equipment manufacturers. Its products may be found in desktops, servers, tablets, smartphones and other devices.

Intel Patents by Type

  • Intel Patents Granted: Intel patents that have been granted by the United States Patent and Trademark Office (USPTO).
  • Intel Patent Applications: Intel patent applications that are pending before the United States Patent and Trademark Office (USPTO).
  • Publication number: 20170176330
    Abstract: A gas detection device includes an enclosure having an interior chamber, an audio loudspeaker in acoustic communication with the interior chamber of the enclosure, and a gas sensor configured to detect a gas within the interior chamber of the enclosure. The device may include a ventilation port configured to permit two-way gaseous communication between the interior chamber and an atmosphere external to the enclosure, where the atmosphere comprises the gas. The audio loudspeaker is configured to generate a pressure within the interior chamber. The pressure causes a portion of the external atmosphere to be drawn into the interior chamber via the ventilation port. The gas sensor may include an emitter and a receiver. The gas detection device can be integrated into a mobile electronic device, such as a smartphone or tablet computer.
    Type: Application
    Filed: December 22, 2015
    Publication date: June 22, 2017
    Applicant: Intel Corporation
    Inventors: Saku Lahti, Mikko S. Komulainen, Tapio Liusvaara
  • Publication number: 20170181339
    Abstract: A method of assembly comprising providing an assembly probe, the assembly probe having an end coupling face; providing a droplet of fluid on the end coupling face of the assembly probe; coupling an electronic component to the end coupling face of the assembly probe with the fluid droplet, the electronic component having a peripheral dimension equal to or less than 2 mm in each of length, width and height; placing the electronic component on a substrate with the assembly probe; decoupling the electronic component from the end coupling face of the assembly probe; and assembling the electronic component to the substrate.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 22, 2017
    Applicant: Intel Corporation
    Inventors: Kyle Yazzie, Pramod Malatkar, Xiao Lu, Daniel Chavez-Clemente
  • Publication number: 20170181334
    Abstract: Disclosed are EMI shielded packages, electronic device packages, and related methods. EMI shielded packages are formed by applying an insulating material to a first side of a substrate strip, separating the substrate strip into segments, adhering the insulating material of the segments to a solid conductor, applying a conductive paste around lateral sides of the segments, curing the conductive paste, and cutting through the conductive paste and the solid conductor to form the EMI packages. An electronic device package includes a substrate including electronic circuitry, an EMI shield, and an insulating material insulating the substrate from the EMI shield. The EMI shield includes a solid conductor adhered to the insulating material, and a cured conductive paste at least partially surrounding a lateral edge of the substrate. The cured conductive paste electrically connects the solid conductor to a conductive terminal in a lateral side of the substrate.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 22, 2017
    Applicant: INTEL CORPORATION
    Inventor: Robert Sankman
  • Publication number: 20170181271
    Abstract: Disclosed herein are apparatus, systems, and methods for warpage mitigation in printed circuit board (PCB) assemblies. In some embodiments, a PCB assembly for warpage mitigation may include: a PCB; an interposer disposed on the PCB, wherein the interposer has a first face and an opposing second face, the first face is disposed between the second face and the PCB, conductive contacts are disposed at the second face, solder is disposed on the conductive contacts, the interposer includes a first heater trace proximate to the conductive contacts, and, when a first power is dissipated in the first heater trace, the first heater trace is to generate heat to cause the solder disposed on the conductive contacts to melt; wherein the PCB includes a second heater trace.
    Type: Application
    Filed: December 21, 2015
    Publication date: June 22, 2017
    Applicant: Intel Corporation
    Inventors: Rashelle Yee, Russell S. Aoki, Shelby Ferguson, Michael Hui, Jonathon Robert Carstens, Joseph J. Jasniewski, Kevin J. Ceurter
  • Publication number: 20170176260
    Abstract: Disclosed herein are integrated circuit (IC) packages with temperature sensor traces, and related systems, devices, and methods. In some embodiments, an IC package may include a package substrate and an IC die disposed on the package substrate, wherein the package substrate includes a temperature sensor trace, and an electrical resistance of the temperature sensor trace is representative of an equivalent temperature of the temperature sensor trace.
    Type: Application
    Filed: December 21, 2015
    Publication date: June 22, 2017
    Applicant: INTEL CORPORATION
    Inventors: Shelby Ferguson, Rashelle Yee, Russell S. Aoki, Michael Hui, Jonathon Robert Carstens, Joseph J. Jasniewski
  • Publication number: 20170176538
    Abstract: Systems and methods are disclosed for estimating a full-charge battery cell capacity without a coulomb counting device. First and second measured voltages of the battery cell are measured during a charging or discharging period. The first and second measured voltages of the battery cell are converted to percentages of remaining battery life. The amount of charge delivered to the battery cell and/or delivered from the battery cell during charging/discharging is calculated. The change in the percentage of remaining battery life is compared to the amount of charge delivered to the battery cell and/or delivered from the battery cell to calculate various battery cell evaluation calculations, including a full-charge battery cell capacity.
    Type: Application
    Filed: December 21, 2015
    Publication date: June 22, 2017
    Applicant: INTEL CORPORATION
    Inventors: Naoki Matsumura, Andrew W. Keates
  • Publication number: 20170176198
    Abstract: A plurality of vehicles may each include one or more biometric sensors capable of measuring at least one physiological factor and/or at least one psychological factor logically associated with at least one occupant of each vehicle. Each of the plurality of vehicles may also include at least one vehicular sensor to measure at least one vehicular factor and/or at least one ambient environmental sensor to measure at least one ambient environmental factor. A route guidance state machine receives the data indicative of the at least one physiological factor, at least one psychological factor, at least one vehicular factor, and/or at least one ambient environmental factor and determines a route for a first vehicle that minimizes the likelihood of contact with others in the plurality of vehicles exhibiting one or more unsafe actions.
    Type: Application
    Filed: December 22, 2015
    Publication date: June 22, 2017
    Applicant: Intel Corporation
    Inventors: IGOR A. TATOURIAN, RITA A. WOUHAYBI, ANSUYA NEGI
  • Publication number: 20170176202
    Abstract: Systems and methods for directing foot traffic are disclosed. Crowd data is gathered from one or more crowd data sources to monitor crowd densities of a geographic area. Locations are received for pedestrian client devices within the geographic area. Augmented reality commands are determined and supplied to the pedestrian client devices to direct movement of users, generally away from more dense zones and toward less dense zones within the geographic area. The augmented reality commands may direct haptic augmented reality output by a pedestrian client device and/or an accessory associated therewith.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 22, 2017
    Applicant: INTEL CORPORATION
    Inventors: Glen J. Anderson, Yosi Govezensky, Eli Turiel, Tamara Gaidar
  • Publication number: 20170176495
    Abstract: Coated probe tips are described for plunger pins of an integrated circuit package tests system. One example has a plunger having a tip to contact a solder ball of an integrated circuit package, a sleeve to hold the plunger and allow the plunger to move toward and away from the package, the sleeve being held in a socket, a spring within the sleeve to drive the plunger toward the package, and a coating over the tip, the coating being harder than a solder ball.
    Type: Application
    Filed: December 21, 2015
    Publication date: June 22, 2017
    Applicant: INTEL CORPORATION
    Inventors: Wen Yin, Anna M. Prakash, Teag R. Haughan, Dingying David Xu, Joaquin Aguilar-Santillan
  • Publication number: 20170176516
    Abstract: A thermal heat for integrated circuit die processing is described that includes a thermal barrier. In one example, the thermal head has a ceramic heater configured to carry an integrated circuit die, a metal base, and a thermal barrier between the heater and the base.
    Type: Application
    Filed: December 21, 2015
    Publication date: June 22, 2017
    Applicant: INTEL CORPORATION
    Inventors: Mohit Mamodia, Kyle Yazzie, Dingying David Xu, Kuang Liu, Paul J. Diglio, Pramod Malatkar
  • Publication number: 20170177369
    Abstract: Methods and apparatus relating to non-contiguous multiple register access for microprocessor data exchange instructions are described. In an embodiment, a plurality of registers store data. A processor exchanges the stored data between the one or more of the plurality of registers and a logic component in response to a single instruction. The plurality of registers are non-contiguous. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 21, 2015
    Publication date: June 22, 2017
    Applicant: Intel Corporation
    Inventors: Peng Guo, Wei-Yu Chen, Guei-Yuan Lueh, Subramaniam Maiyuran
  • Publication number: 20170177057
    Abstract: Examples include techniques to power down output power rails for a storage device. In some examples, energy discharged from output capacitors for output power rails and energy discharged from input capacitors may be used to facilitate power down of power rails for the storage device.
    Type: Application
    Filed: December 21, 2015
    Publication date: June 22, 2017
    Applicant: Intel Corporation
    Inventors: ANDREW MORNING-SMITH, KAI-UWE SCHMIDT, ADRIAN MOCANU, MIKE M. NGO
  • Publication number: 20170177068
    Abstract: A power delivery system of a computing system can switch the computing platform from a set of main rails to a standby rail in a low-power state. For example, using a power optimizer framework, a platform controller hardware (PCH) and/or platform management controller (PCU) can transition an idle computing system to a low-power state using a standby rail with the main rails off. The PCU can instruct a processor in a C10 state to switch from main power rails to a standby rail. Once confirmed that the processor is in the C10 state, the PCU can turn off a processor voltage regulator and assert a platform sleep signal. After confirming the platform has entered the sleep state in which the platform has moved to the standby rails, the PCH or PCU can request a power supply to turn off the main rails but leave the standby rail active.
    Type: Application
    Filed: December 17, 2015
    Publication date: June 22, 2017
    Applicant: INTEL CORPORATION
    Inventors: Barnes Cooper, Vidoot Ponnala Rathnakar
  • Publication number: 20170177069
    Abstract: Disclosed are electrical systems and electronic devices. An electrical system includes an electronic device. The electronic device is configured to receive external power from an external power source, the external power sufficient to support normal mode operation of the electronic device. The electronic device includes control circuitry programmed to operate in the normal mode while receiving external power, and transition to one of a low power mode and a pre-shutdown mode responsive to sensor inputs. An electronic device includes an internal power source configured to provide internal power sufficient to support low power requirements of the electronic device operating in a low power mode, but not sufficient to support normal power requirements of a normal mode. The electronic device includes control circuitry programmed to transition from the low power mode to a hibernate mode while powered by only the internal power source.
    Type: Application
    Filed: December 21, 2015
    Publication date: June 22, 2017
    Applicant: INTEL CORPORATION
    Inventors: Sachin Bedare, Ayeshwarya Mahajan
  • Publication number: 20170177087
    Abstract: Hand skeletons are compared to a hand image and selected. The hand skeletons are used for hand and gesture recognition with a computing interface. In one example, the method includes projecting points of a generated hand skeleton onto a received hand image, classifying the skeleton points as inside or outside the hand image, quantifying the comparison to generate a comparison quantity using a comparison function distance measurement, the comparison function distance measurement comprising an outside skeleton distance that includes a sum of distances from each outside skeleton point to a nearest inside skeleton point, applying the comparison function quantity to select the generated hand skeleton as a best match, and applying the selected hand skeleton to generate a command to a computer system command interface.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 22, 2017
    Applicant: INTEL CORPORATION
    Inventors: ALON LERNER, ITAMAR GLAZER, SHAHAR FLEISHMAN
  • Publication number: 20170177089
    Abstract: A wearable sensor system is disclosed that provides a measurable magnetic field that changes horizontally within the range of motion of human limbs. The wearable sensor system includes a magnetic sensing device, and one or more magnet devices that provide the measurable magnetic field with a strength exceeding the Earth's magnetic field. To this end, the magnetic sensing system provides a “personal” magnetic field about a user, with that magnetic field traveling with the user and overpowering adjacent interfering fields. The wearable sensor system may include a sensor arrangement that measures a strength of the personal magnetic field and field direction to perform horizontal localization, and may send a representation of a same to a remote computing device to cause an action to occur. Some such actions include output of pre-recorded or synthesized musical notes, for example.
    Type: Application
    Filed: December 21, 2015
    Publication date: June 22, 2017
    Applicant: Intel Corporation
    Inventors: SWARNENDU KAR, JEREMY PARRA, SAURIN SHAH, BRIAN K. VOGEL
  • Publication number: 20170181263
    Abstract: The present disclosure provides systems and methods for a package securing system including a top plate, an alignment frame, a gasket, and a back plate. The top plate comprises a thermal conductive member to transfer heat from a central processing unit (CPU) and secure the CPU to a ball grid array (BGA) socket and a printed circuit board (PCB). The alignment frame is configured to align a connection between the BGA socket and the PCB. The gasket is to seal the CPU, the BGA socket, and the alignment frame between the PCB and the top plate. The back plate is configured to couple with the top plate through the PCB.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 22, 2017
    Applicant: INTEL CORPORATION
    Inventors: Emad Al-Momani, Srikanth Mothukuri
  • Publication number: 20170177216
    Abstract: Methods and apparatus related to enabling individual NVMe (Non-Volatile Memory express) IO (Input Output or I/O) queues on differing network addresses of an NVMe controller are described. In one embodiment, a plurality of backend controller logic is coupled to a plurality of non-volatile memory devices. One or more virtual controller target logic (coupled to the plurality of backend controller logic) transmit data from a first portion of a plurality of IO queues to a first backend controller logic of the plurality of the backend controller logic. The one or more virtual controller target logic transmit data from a second portion of the plurality of IO queues to a second backend controller logic of the plurality of backend controller logic. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 21, 2015
    Publication date: June 22, 2017
    Applicant: Intel Corporation
    Inventors: James P. Freyensee, Phil C. Cayton, Dave B. Minturn, Jay E. Sternberg
  • Publication number: 20170177259
    Abstract: Examples are given for techniques to use open bit line information for a memory system. In some examples, open information indicating locations of open bit lines for physical memory addresses of one or more memory devices may be used to successfully decoded ECC encoded data stored to the one or more memory devices. The open information, in some instances, is stored with the ECC encoded data and is available for use to enable a successful correction of errors in the ECC encoded data following a read request that causes the ECC encoded data to be read from the physical memory addresses.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 22, 2017
    Applicant: Intel Corporation
    Inventor: RAVI H. MOTWANI
  • Publication number: 20170177362
    Abstract: A processor includes a decode unit to decode an adjoining data element pairwise swap instruction. The instruction is to indicate a source packed data that is to include pairs of adjoining data elements, and is to indicate a destination storage location. An execution unit is coupled with the packed data registers and the decode unit. The execution unit, in response to the instruction, is to store a result packed data in the destination storage location, the result packed data to include pairs of adjoining data elements. Each pair of adjoining data elements of the result packed data is to correspond to a different pair of adjoining data elements of the source packed data. The adjoining data elements in each pair of the result packed data to have been swapped in position relative to the adjoining data elements in each corresponding pair of the source packed data.
    Type: Application
    Filed: December 22, 2015
    Publication date: June 22, 2017
    Applicant: INTEL CORPORATION
    Inventor: Ashish Jha
  • Publication number: 20170177365
    Abstract: A processor of an aspect includes a decode unit to decode a transaction end plus commit to persistence instruction. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to atomically ensure that all prior store to memory operations made to a persistent memory, which are to have been accepted to memory when performance of the instruction begins, but which are not necessarily to have been stored in the persistent memory when the performance of the instruction begins, are to be stored in the persistent memory before the instruction becomes globally visible. The execution unit, in response to the instruction, is also to atomically end a transactional memory transaction before the instruction becomes globally visible.
    Type: Application
    Filed: December 22, 2015
    Publication date: June 22, 2017
    Applicant: Intel Corporation
    Inventors: Kshitij A. Doshi, Christopher J. Hughes
  • Publication number: 20170177026
    Abstract: Particular embodiments described herein provide for an device that includes a first body coupled to a first housing, a second body coupled to a second housing, a hinge rod, and a spring clip on an outside diameter of the hinge rod, where the spring clip is configured to increase the torque of the hinge.
    Type: Application
    Filed: December 22, 2015
    Publication date: June 22, 2017
    Applicant: Intel Corporation
    Inventor: David A. Rittenhouse
  • Publication number: 20170177505
    Abstract: Examples include techniques for compressing counter values included in cryptographic metadata. In some examples, a cache line to fill a cache included in on-die processor memory may be received. The cache arranged to store cryptographic metadata. The cache line includes a counter value generated by a counter. The counter value to serve as version information for a memory encryption scheme to write a data cache line to a memory location of an off-die memory. In some examples, the counter value is compressed based on whether the counter value includes a pattern that matches a given pattern and is then stored to the cache. In some examples, a compression aware and last recently used (LRU) scheme is used to determine whether to evict cryptographic metadata from the cache.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 22, 2017
    Applicant: Intel Corporation
    Inventors: ABHISHEK BASAK, SIDDHARTHA CHHABRA, JUNGJU OH, DAVID M. DURHAM
  • Publication number: 20170177407
    Abstract: Work can be migrated between processor cores. For example, a thread causing a heavy load on a first core can be detected. A power control unit can determine to migrate the thread from the first less-efficient core to the second more-efficient core. The power control unit can request that the first core and the second core transition to a low-power state (e.g., a sleep state, a C6 power state, etc.). The first core can transfer its software context to a first core software context storage, halt and quiesce. The second core can halt and quiesce. The software context from the first core software context storage can be transferred to a second core software context storage of the second core. A processing core identifier of the first core can be assigned to the second core. The power control unit can then request the second core to transition to an active state (such as a C0 state).
    Type: Application
    Filed: December 17, 2015
    Publication date: June 22, 2017
    Applicant: INTEL CORPORATION
    Inventors: Guy Therien, Guy Sotomayor, Arijit Biswas, Michael D. Powell, Eric J. Dehaemer
  • Publication number: 20170177627
    Abstract: In an example, there is disclosed a computing apparatus, including one or more logic elements, including at least one hardware logic element, comprising a classification engine to: receive a clean multi-labeled dataset comprising a plurality of document each assigned to one or more of a plurality of categories; receive an unclean multi-labeled dataset; and produce a recategorized and cleansed dataset from the unclean multi-labeled dataset, comprising predicting a number of labels {circumflex over (l)} for a document j, and comparing {circumflex over (l)} to an existing number of labels l. There is also disclosed a method of providing a classification engine.
    Type: Application
    Filed: December 22, 2015
    Publication date: June 22, 2017
    Applicant: Intel IP Corporation
    Inventors: Nidhi Singh, Craig Philip Olinsky, Thamizhannal Paramasivam
  • Publication number: 20170177833
    Abstract: A mechanism is described for facilitating smart placement of devices for implicit triggering of feedbacks relating to users' physical activities according to one embodiment. A method of embodiments, as described herein, includes detecting scanning, in real-time, of a body of a user during one or more physical activities being by the user, where scanning is performed by one or more sensors placed in one or more items located within proximity of the user. The method may further include receiving data from the one or more sensors, where the data includes biometric data relating to the user. The method may further include forming a feedback based on processing of the biometric data, and communicating, in real-time, the feedback using an object or one or more feedback devices.
    Type: Application
    Filed: December 22, 2015
    Publication date: June 22, 2017
    Applicant: INTEL CORPORATION
    Inventors: ERIC LEWALLEN, MANAN GOEL, SAURIN SHAH, BRIAN W. BRAMLETT
  • Publication number: 20170177539
    Abstract: An apparatus is provided that includes a processor, a memory controller coupled to the processor to provide access to a system memory, and an interface controller to communicate with an endpoint device. The interface controller is coupled to the processor and configured to access a register of the endpoint device, the register to be mapped into a memory space of the system, the register to store a service latency tolerance value of the endpoint device. The endpoint device has a service latency tolerance value for a first state and a service latency tolerance value for a second state. The service latency tolerance value for the first state is greater than the service latency tolerance value for the second state.
    Type: Application
    Filed: March 8, 2017
    Publication date: June 22, 2017
    Applicant: Intel Corporation
    Inventors: Jaya L. Jeyaseelan, Jim Walsh, Robert E. Gough, Barnes Cooper, Neil W. Songer
  • Publication number: 20170178004
    Abstract: One embodiment provides an apparatus. The apparatus includes a wearable device. The wearable device includes a knowledge base, a user interface and automatic response logic. The knowledge base includes at least one data structure. Each data structure includes a plurality of ranked possible user responses. The automatic response logic is to select one data structure of the at least one data structure in response to a received communication. The selecting is based, at least in part, on an event type and based, at least in part, on a contact identifier. The communication is received from a communication partner device via a companion device. The automatic response logic is further to provide at least one ranked possible user response from the selected data structure to a user via the user interface.
    Type: Application
    Filed: December 21, 2015
    Publication date: June 22, 2017
    Applicant: Intel Corporation
    Inventors: Sunil TIPTUR NATARAJ, Fai YEUNG
  • Publication number: 20170177739
    Abstract: Techniques for prediction using multimap is described herein. The method for multimap prediction can include generating a user profile graph in the memory device based on user action input received at an input device. The method for multimap prediction can also include matching a user profile graph stored in the memory device to a subgraph of a multimap graph, both comprising nodes and edges, wherein each node indicates at least one of an activity input and a keyword. The method can include providing access to a multimap prediction in the memory device based on the user action input and the subgraph of the multimap graph.
    Type: Application
    Filed: December 22, 2015
    Publication date: June 22, 2017
    Applicant: Intel Corporation
    Inventors: Kalpana A. Algotar, Addicam V. Sanjay
  • Publication number: 20170178294
    Abstract: A mechanism is described for facilitating code filters for coded light depth acquisition in depth images at computing devices according to one embodiment. A method of embodiments, as described herein, includes detecting a code image of an object comprising pixels of code values and pixels of metadata values including confidence and code transition locations, and computing a vertical filter to be applied to the code image to smooth out the code transitions along vertical directions. The method further include computing a horizontal filter to be applied to the code image to smooth out the code transitions along horizontal directions, and computing a consistency filter to be applied to the code image to increase an accuracy of the code values and mark inconsistent pixels as invalid.
    Type: Application
    Filed: December 22, 2015
    Publication date: June 22, 2017
    Applicant: INTEL CORPORATION
    Inventors: Vitaly Surazhsky, Michael Bronstein, Alex Bronstein, Ron Kimmel, Erez Sperling, Aviad Zabatani, Ohad Manashe, David H. Silver
  • Publication number: 20170177873
    Abstract: Disclosed herein are embodiments related to security in cloudlet environments. In some embodiments, for example, a computing device (e.g., a cloudlet) may include: a trusted execution environment; a Basic Input/Output System (BIOS) to request a Key Encryption Key (KEK) from the trusted execution environment; and a Self-Encrypting Storage (SES) associated with the KEK; wherein the trusted execution environment is to verify the BIOS and provide the KEK to the BIOS subsequent to verification of the BIOS, and the BIOS is to provide the KEK to the SES to unlock the SES for access by the trusted execution environment.
    Type: Application
    Filed: March 4, 2016
    Publication date: June 22, 2017
    Applicant: Intel Corporation
    Inventors: Yeluri Raghuram, Susanne M. Balle, Nigel Thomas Cook, Kapil Sood
  • Publication number: 20170178117
    Abstract: A mechanism is described for facilitating smart geo-fencing-based payment transactions according to one embodiment. A method of embodiments, as described herein, includes detecting, by one or more capturing/sensing components of a data processing device, a first computing device within proximity of a geo-fenced location. The method further include receiving detection information relating to the detection of the first computing device, authenticating at least one of the first computing device and the geo-fenced location, and interfacing the first computing device with a second computing device. The method may further include facilitating a payment transaction, where the payment transaction includes payment of a monetary amount from the second computing device to the first computing device, and executing the payment transaction.
    Type: Application
    Filed: December 22, 2015
    Publication date: June 22, 2017
    Applicant: INTEL CORPORATION
    Inventors: ANNE P. MCCLARD, AAREN B. ESPLIN, WENDY MARCH
  • Publication number: 20170178350
    Abstract: A method for anisotropic filtering is provided herein. The method includes computing an anisotropic filter with a major-axis and a minor-axis for a pixel to be displayed on screen-space, wherein the anisotropic filter is to be applied to corresponding MIPs on a texture map. The method includes varying the length of the major-axis of the anisotropic filter based on the angle of the major-axis of anisotropy with respect to the screen space. The method includes determining a number of texels from the texture map that are to be sampled in the anisotropic filter based on the length of the modified major-axis. The method includes determining the color of the pixel based on the texels sampled in the anisotropic filter.
    Type: Application
    Filed: March 9, 2017
    Publication date: June 22, 2017
    Applicant: INTEL CORPORATION
    Inventors: Prosun Chatterjee, Larry Seiler, Steven Spangler
  • Publication number: 20170178362
    Abstract: A mechanism is described for facilitating interpolated minimum-maximum compression/decompression for efficient processing of graphics data at computing devices. A method of embodiments, as described herein, includes detecting a tile having pixels representing graphics contents capable of being processed by a graphics processor of a computing device; computing a minimum color value and a maximum color value of the tile. The method may further include splitting the tile into a plurality of interpolation tiles, where each interpolation tile includes a set of pixels of one or more colors. The method may further include computing a plurality of local minimum color values for the plurality of interpolation tiles, computing, based on the plurality of local minimum values, a plurality of residuals for the plurality of interpolation tiles to reduce spreads from the plurality of interpolation tiles, and compressing the reduced plurality of interpolation tiles based on the plurality of residuals.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 22, 2017
    Applicant: INTEL CORPORATION
    Inventors: TOMAS G. AKENINE-MOLLER, JON N. HASSELGREN, JIM K. NILSSON
  • Publication number: 20170178380
    Abstract: A method is described to facilitate real-time visualization. The method includes receiving sensory data from one or more wearable devices, determining a real-time body position of a use based on the sensory data, generating an image of the user based on the real-time body position and displaying the image of the user at an optical head-mounted display computing device.
    Type: Application
    Filed: December 21, 2015
    Publication date: June 22, 2017
    Applicant: Intel Corporation
    Inventors: Emily N. Ivers, Kahyun Kim, Paul F. Sorenson, Brian R. Fairbanks, Ronald T. Azuma, Jeremy Miossec-Backer
  • Publication number: 20170178387
    Abstract: Embodiments provide for a graphics processing apparatus including a graphics processing unit having bounding volume logic to operate on a compressed bounding volume hierarchy, wherein each bounding volume node stores a parent bounding volume and multiple child bounding volumes that are encoded relative to the parent bounding volume.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 22, 2017
    Applicant: INTEL CORPORATION
    Inventors: Sven Woop, Carsten Benthin, Rasmus Barringer, Tomas G. Akenine-Moller
  • Publication number: 20170178276
    Abstract: A mechanism is described for facilitating efficient clustering and compression of graphics data at computing devices. A method of embodiments, as described herein, includes detecting a tile having pixels representing graphics contents capable of being processed by a graphics processor of a computing device. The method may further include splitting the tile into a plurality of clusters, where each cluster includes a set of pixels of one or more colors. The method may further include determining a center color for each cluster of the plurality of colors, where determining further includes deciding whether the center color is classified as acceptable for compression. The method may further include compressing contents of one or more of clusters if one or more center colors of the one or more clusters are classified as acceptable.
    Type: Application
    Filed: December 22, 2015
    Publication date: June 22, 2017
    Applicant: INTEL CORPORATION
    Inventors: TOMAS G. AKENINE-MOLLER, JIM K. NILSSON
  • Publication number: 20170178011
    Abstract: One embodiment provides an apparatus. The apparatus includes a companion device. The companion device includes pattern recognition logic to construct a reference graph model based, at least in part, on a plurality of events captured from at least one of the companion device and a wearable device. The reference graph model includes at least one path, each path including one trigger node, at least one event node and a respective edge incident to each event node, a first edge coupling the trigger node and a first event node, a weight associated with each edge corresponding to a likelihood that a second event will follow a first event within a minimum trigger time interval.
    Type: Application
    Filed: December 21, 2015
    Publication date: June 22, 2017
    Applicant: Intel Corporation
    Inventors: FAI YEUNG, FU ZHOU
  • Publication number: 20170178305
    Abstract: A mechanism is described for facilitating three-dimensional (3D) depth imaging systems, and morphological and geometric filters for edge enhancement in depth images at computing devices according to one embodiment. A method of embodiments, as described herein, includes detecting an input digital image of an object, the digital image comprising data pixels contaminated by noise and confidence values corresponding to the data pixels, and computing a morphological filter by matching the confidence pixels in the input digital image with a set of matching templates, and using a set of masking templates to determine the data pixels and confidence pixels in the filtered image. The method further include computing an edge filter by performing computation of distances between the data pixels along a plurality of directions to determine an edge direction, and determining the data pixels and and the confidence pixels in a filtered image based on the edge direction.
    Type: Application
    Filed: December 22, 2015
    Publication date: June 22, 2017
    Applicant: INTEL CORPORATION
    Inventors: DAVID H. SILVER, MICHAEL BRONSTEIN, ALEX BRONSTEIN, RON KIMMEL, EREZ SPERLING, VITALY SURAZHSKY, AVIAD ZABATANI, OHAD MANASHE
  • Publication number: 20170178994
    Abstract: Disclosed herein are integrated circuit (IC) package support structures, and related systems, devices, and methods. In some embodiments, an IC package support structure may include a first heater trace, and a second heater trace, wherein the second heater trace is not conductively coupled to the first heater trace in the IC package support structure.
    Type: Application
    Filed: December 21, 2015
    Publication date: June 22, 2017
    Applicant: Intel Corporation
    Inventors: Michael Hui, Rashelle Yee, Jonathan Thibado, Daniel P. Carter, Shelby Ferguson, Anthony P. Valpiani, Russell S. Aoki, Jonathon Robert Carstens, Joseph J. Jasniewski, Harvey R. Kofstad, Michael Brazel, Tracy Clack, Viktor Vogman, Penny Woodcock, Kevin J. Ceurter, Hongfei Yan
  • Publication number: 20170178597
    Abstract: Embodiments provide for a graphics processing apparatus comprising a graphics processing unit including bounding volume logic to encode a first bounding volume and a second bounding volume for a bounding volume hierarchy, wherein the first bounding volume is to be encoded at a higher numerical precision relative to the second bounding volume and the first bounding volume encloses the second bounding volume.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 22, 2017
    Applicant: INTEL CORPORATION
    Inventor: Jon N. Hasselgren
  • Publication number: 20170179466
    Abstract: A system and method for an energy storage device, such as a battery, having an electrode tab, an electrode, and a laser weld coupling the electrode tab to the electrode. The electronic storage device or battery may be installed in an electronic device. Fabrication of the energy storage device may involve placing an electrode tab adjacent a surface of a thin layer of the electrode, and laser welding the electrode tab to the thin layer.
    Type: Application
    Filed: December 17, 2015
    Publication date: June 22, 2017
    Applicant: INTEL CORPORATION
    Inventor: Prabhat Tiwari
  • Publication number: 20170179043
    Abstract: Creating surface variations on a stiffener in a stack reduces inter-stiffener sticking and stiffener stack tilt in pick and place media. The surface variations provide one or more airgaps that reduce inter-stiffener surface contact, provide space for contaminants and/or provide an averaged surface height due to surface roughness.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 22, 2017
    Applicant: INTEL CORPORATION
    Inventors: Mingjie Xu, Suzana Prstic, Kedar Dhane
  • Publication number: 20170181205
    Abstract: A broadcast system and method for a direct connection network or personalized network, including a presenter computing device configured for a wireless direct connection with multiple receiving computing devices and to broadcast content via the wireless direct connection to the multiple receiving devices. The multiple receiving computing devices are configured for the wireless direct connection with the presenter computing device and to receive via the wireless direct connection the content broadcast by the presenter computing device. A server computing device is configured to authenticate the multiple receiving devices.
    Type: Application
    Filed: December 21, 2015
    Publication date: June 22, 2017
    Applicant: Intel Corporation
    Inventors: Ravindra Hegde, Singaravelan Nallasellan, Dharmendra Muthuswamy
  • Publication number: 20170179731
    Abstract: An apparatus is described herein. The apparatus includes a power transmit unit coil and an active shielding coil. The power transmit unit coil includes a set of main windings, positioned at a first location on a structure, to carry a first current in a first direction, wherein the first current is to cause an electromagnetic field to emanate from the power transmit unit coil. The active shielding coil is positioned at a second location on the structure and is to carry a second current in a direction substantially opposite the first direction wherein the second current is to cause a reduction of the size of the electromagnetic field.
    Type: Application
    Filed: December 22, 2015
    Publication date: June 22, 2017
    Applicant: Intel Corporation
    Inventors: Suraj Sindia, Songnan Yang, Zhen Yao, Robert F. Kwasnick
  • Publication number: 20170179733
    Abstract: A system for increasing the life of a battery cell by limiting the charging of the battery to less than full charge in response to a predicted electricity draw of a connected device being less than the full capacity of the battery before a predicted recharge will occur. The current draw of the connected device may be affected by the amount of time before a next recharge and environmental factors. The system may further comprise one or more sensors to gather data pertaining to environmental conditions that may be used in the calculation of a charge termination value. The charge termination value is an amount of charge to power the device for a duration of time at least until a predicted recharge begins.
    Type: Application
    Filed: December 21, 2015
    Publication date: June 22, 2017
    Applicant: INTEL CORPORATION
    Inventors: Naoki Matsumura, Andrew W. Keates, Krishnan Ravichandran
  • Publication number: 20170179660
    Abstract: A method of receiving a plug at a receptacle is disclosed. The method may include receiving a plug at a receptacle, the receptacle including contacts disposed with a rotational symmetry about a center point of the receptacle. The method may also include determining, via detection circuitry, any orientation of the plug inserted into the receptacle. The method may also include changing, via selection control circuitry, a connection path coupled to the contacts based on the orientation of the plug.
    Type: Application
    Filed: March 2, 2017
    Publication date: June 22, 2017
    Applicant: INTEL CORPORATION
    Inventors: Bradley Saunders, Robert Dunstan
  • Publication number: 20170179622
    Abstract: An electronic device connection system includes a first electrical device and a second electrical device. The first electrical device includes a plurality of electrical connectors disposed in, on, or about at least a portion of an exterior surface of the first electrical device. The second electrical device includes a plurality of electrical contacts disposed in, on, or about at least a portion of an exterior surface of the second electrical device. A mechanical compressor exerts a force on at least one of the first electrical device or the second electrical device such that the electrical connections on the first electrical device physically and conductively couple to the electrical contacts on the second electrical device. The device casing may function as the mechanical compressor. The electrical connectors and/or electrical contacts may include injection molded connectors that include a conductive material dispersed in a thermoplastic matrix.
    Type: Application
    Filed: December 22, 2015
    Publication date: June 22, 2017
    Applicant: Intel Corporation
    Inventors: SRIKANT NEKKANTY, DONALD T. TRAN, GREGORIO R. MURTAGIAN
  • Publication number: 20170179645
    Abstract: In one example an electronic device comprises at least one electronic component, a chassis comprising a first section, a connector to connect the first section of the chassis to a second section, the connector comprising a housing defining a first shaft, a retention structure disposed in the shaft, and a plurality of electrical contacts positioned within a corresponding plurality of channels in the retention structure. Other examples may be described.
    Type: Application
    Filed: December 21, 2015
    Publication date: June 22, 2017
    Applicant: Intel Corporation
    Inventors: Gavin Sung, Jeff Ku, Lance Lin, Tim Liu, Jason Y. Jiang
  • Publication number: 20170180220
    Abstract: Examples include techniques to generate workload performance fingerprints for cloud infrastructure elements. In some examples, performance metrics are obtained from resource elements or nodes included in an identified sub-graph that represents at least a portion of configurable computing resources of a cloud infrastructure. For these examples, averages for the performance metrics are determined and then stored at a top-level context information node for the identified sub-graph to represent a workload performance fingerprint for the identified sub-graph.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 22, 2017
    Applicant: Intel Corporation
    Inventors: ALEXANDER LECKEY, THIJS METSCH, JOSEPH BUTLER, MICHAEL J. MCGRATH, VICTOR BAYON-MOLINO