Intel Patents

Intel Corporation designs and manufactures microprocessors and chipsets for computing and communications equipment manufacturers. Its products may be found in desktops, servers, tablets, smartphones and other devices.

Intel Patents by Type

  • Intel Patents Granted: Intel patents that have been granted by the United States Patent and Trademark Office (USPTO).
  • Intel Patent Applications: Intel patent applications that are pending before the United States Patent and Trademark Office (USPTO).
  • Publication number: 20170141842
    Abstract: Logic may enable reverse direction communication with improved power efficiency. Logic may transmit a packet to a Responder during a transmission opportunity with an indication of a reverse direction grant. Logic may receive a response to the packet indicative of a lack of data packets to transmit by the Responder. Logic may enter a defer transmission mode in which transmissions are deferred during the transmission opportunity for greater than a point coordination function interframe space (PIFS) within the transmission opportunity. Logic may grant data transmission rights of the transmission opportunity during the defer transmission mode to the Responder. Logic may grant a contention-based data transmission rights of the transmission opportunity during the defer transmission mode. Logic may grant data transmission rights of the transmission opportunity during the defer transmission mode to the Granter.
    Type: Application
    Filed: March 29, 2014
    Publication date: May 18, 2017
    Applicant: INTEL IP CORPORATION
    Inventors: Solomon B. Trainin, Gadi Shor
  • Publication number: 20170142089
    Abstract: Technologies are provided in embodiments to manage an authentication confirmation score. Embodiments are configured to identify, in absolute session time, a beginning time and an ending time of an interval of an active user session on a client. Embodiments are also configured to determine a first value representing a first subset of a set of prior user sessions, where the prior user sessions of the first subset were active for at least as long as the beginning time. Embodiments can also determine a second value representing a second subset of the set of prior user sessions, where the prior user sessions of the second subset were active for at least as long as the ending time. Embodiments also determine, based on the first and second values, a decay rate for the authentication confidence score of the active user session. In some embodiments, the set is based on context attributes.
    Type: Application
    Filed: January 30, 2017
    Publication date: May 18, 2017
    Applicant: Intel Corporation
    Inventors: Micah Sheller, Conor Cahill, Jason Martin, Brandon Baker
  • Publication number: 20170141617
    Abstract: A non-contact power transmission apparatus accurately determines the kind of object that is placed on the charging deck of the non-contact power transmission apparatus, and, only when a non-contact power receiving apparatus is placed on the power transmission apparatus, allows power transmission and data communication to take place, thereby accurately determining the state of the receiver side and efficiently controlling the transmission of power. In the power transmission apparatus, the power supplied to the non-contact power receiving apparatus is measured, and the output power of the wireless power signal output from two different cores is controlled, thereby allowing the charging operation to be stably conducted even if the non-contact power receiving apparatus is moved anywhere on the power transmission apparatus.
    Type: Application
    Filed: November 22, 2016
    Publication date: May 18, 2017
    Applicant: INTEL CORPORATION
    Inventors: Chun-Kil JUNG, Yoon-Sang KUK
  • Publication number: 20170139537
    Abstract: Particular embodiments described herein provide for a system, an apparatus, and a method for determining a number of users and their respective positions relative to a device. One example embodiment includes acquiring touch point data from a hand of a user, clustering the touch point data, and determining a respective position of the user by mapping the clustered touch point data to a pre-defined hand pattern. The touch point data can include a plurality of touch points and a distance between each touch point is used to cluster the touch point data. In one example, the touch point data may be acquired using a touch sensor and the touch sensor can be a touch display.
    Type: Application
    Filed: May 13, 2015
    Publication date: May 18, 2017
    Applicant: Intel Corporation
    Inventors: Raghvendra Maloo, Gokul V. Subramaniam
  • Publication number: 20170139318
    Abstract: Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may be arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern.
    Type: Application
    Filed: January 30, 2017
    Publication date: May 18, 2017
    Applicant: INTEL CORPORATION
    Inventors: CHARLES H. WALLACE, HOSSAM M. ABDALLAH, ELLIOT N. TAN, SWAMINATHAN SIVAKUMAR, OLEG GOLONZKA, ROBERT M. BIGWOOD
  • Publication number: 20170139439
    Abstract: Particular embodiments described herein provide for an electronic device, such as a notebook computer or laptop, that includes a circuit board coupled to a plurality of electronic components (which includes any type of components, elements, circuitry, etc.). The electronic device may also include a base portion and a lid portion coupled to the base portion at a hinge configured such that the base portion and the lid portion can rotate between an open configuration of the electronic device and a closed configuration of the electronic device. The lid portion can include at least one segment that is to raise at least a portion of the base portion in response to a rotation toward the open configuration (e.g., opening the lid portion to access a touchpad or a keyboard of the electronic device, or to see a display of the electronic device).
    Type: Application
    Filed: December 12, 2016
    Publication date: May 18, 2017
    Applicant: Intel Corporation
    Inventors: James M. Okuley, Kimi Jensen
  • Publication number: 20170139448
    Abstract: Embodiments of an apparatus, system and method are described for a mobile computing device. A mobile computing device may comprise, for example, an enclosure arranged to support a display and one or more processor circuits, the enclosure having an enlarged portion at one side of the enclosure arranged to allow a user to clutch the enclosure with one hand at the one side, the enlarged portion having a thickness that is larger than a thickness of another portion of the enclosure, and the enlarged portion defining a cavity arranged to support one or more energy storage modules. Other embodiments are described and claimed.
    Type: Application
    Filed: January 30, 2017
    Publication date: May 18, 2017
    Applicant: Intel Corporation
    Inventors: Sameer Sharma, Gadi Amit, Yoshikazu Hoshino, Chadwick Harber, Daniel Clifton, Kenneth Jasinski
  • Publication number: 20170142131
    Abstract: Various embodiments are directed enabling anti-malware software to co-exist with protective features of an operating system. An apparatus may include a processor component including an IDT register storing an indication of size of an IDT; a monitoring component to retrieve the indication and compare the indication to a size of a guard IDT in response to modification of the IDT register to determine whether the guard routine is to inspect the IDT and a set of ISRs; and a cache component to overwrite the IDT and set of ISRs with a cached IDT and cached set of ISRs, respectively, based on the determination and prior to the inspection to prevent the guard routine from detecting a modification by an anti-malware routine, the cached IDT and cached set of ISRs generated from the IDT and set of ISRs, respectively, prior to the modification. Other embodiments are described and claimed.
    Type: Application
    Filed: September 19, 2016
    Publication date: May 18, 2017
    Applicant: Intel Corporation
    Inventors: Ramesh Thomas, Manohar R. Castelino, Kuo-Lang Tseng
  • Publication number: 20170140078
    Abstract: Various embodiments are generally directed to techniques for employing a hybrid of sequential and parallel processing to perform random sample and consensus (RANSAC). A device to perform RANSAC includes a derivation component to derive a first set of proposed models in parallel from a first set of minimal sample sets of a data set; and a comparison component to recalculate a required quantity of proposed models to derive an accurate model if a proposed model of the first set of proposed models better fits the data set than any proposed model derived prior to derivation of the first set of proposed models, and to determine whether to derive a second set of proposed models following derivation of the first set of proposed models based on a comparison of the required quantity to a quantity of previously derived proposed models that includes the first set. Other embodiments are described and claimed.
    Type: Application
    Filed: March 27, 2014
    Publication date: May 18, 2017
    Applicant: INTEL CORPORATION
    Inventors: Liu Yang, Qiang Li, Bin Wang, Xianchao Xu, Bing Niu
  • Publication number: 20170140221
    Abstract: A dual function camera is described for infrared and visible light imaging using electrically controlled filters. An example has an image sensor to image visible and infrared light, a lens system to image a scene onto the image sensor, and an electrically activated filter that selectively prevents visible light from the scene from impinging on the image sensor while capturing an infrared image.
    Type: Application
    Filed: November 13, 2015
    Publication date: May 18, 2017
    Applicant: INTEL CORPORATION
    Inventors: MIKKO OLLILA, ENDRE VEKA
  • Publication number: 20170141039
    Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ILD disposed on a top surface of a metal gate disposed on the substrate.
    Type: Application
    Filed: January 30, 2017
    Publication date: May 18, 2017
    Applicant: INTEL CORPORATION
    Inventors: BERNHARD SELL, OLEG GOLONZKA
  • Publication number: 20170139714
    Abstract: A unified architecture for dynamic generation, execution, synchronization and parallelization of complex instruction formats includes a virtual register file, register cache and register file hierarchy. A self-generating and synchronizing dynamic and static threading architecture provides efficient context switching.
    Type: Application
    Filed: November 21, 2016
    Publication date: May 18, 2017
    Applicant: Intel Corporation
    Inventor: Mohammad A. Abdallah
  • Publication number: 20170140570
    Abstract: A mechanism is described for facilitating efficient centralized rendering of viewpoint-agnostic graphics workloads at computing devices. A method of embodiments, as described herein, includes detecting, at a computing device, a viewpoint-agnostic workload relating to a graphics scene to be delivered at one or more computing devices; processing one or more viewpoint-agnostic rendering tasks relating to the viewpoint-agnostic workload to obtain a set of viewpoint-agnostic processing data, wherein the viewpoint-agnostic workload is common to the scene and independent of one or more specific viewpoints of the scene corresponding to the one or more computing devices; and distributing the set of viewpoint-agnostic processing data to the one or more computing devices.
    Type: Application
    Filed: November 13, 2015
    Publication date: May 18, 2017
    Applicant: INTEL CORPORATION
    Inventors: ADAM Z. LEIBEL, DANIEL H. WALSH, ROBERT B. TAYLOR
  • Publication number: 20170140809
    Abstract: Methods and apparatus related to multiple rank high bandwidth memory are described. In one embodiment, a semiconductor package includes a high bandwidth memory with multiple ranks. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: November 14, 2016
    Publication date: May 18, 2017
    Applicant: Intel Corporation
    Inventors: Christopher P. Mozak, Randy B. Osborne, Michael Gutzmann, James A. McCall
  • Publication number: 20170140791
    Abstract: Image stitching is described for multiple camera video by placing seams for objects in the scene. An object of interest is identified within an overlap between two images each from a different adjacent camera of a multiple camera system. An identified object of interest is placed within an identified one of the two images. A seam is placed between the two images so that the object of interest is within the identified image and not within the other of the two images. The two images are joined at the placed seam and the two joined images are rendered as a single image joined at the placed seam.
    Type: Application
    Filed: November 12, 2015
    Publication date: May 18, 2017
    Applicant: INTEL CORPORATION
    Inventors: Barnan Das, STANLEY BARAN, RICHMOND HICKS, SEAN PYO, KANGHEE LEE
  • Publication number: 20170141021
    Abstract: Incorporating at least one magnetic alignment structure on a microelectronic device and incorporating at least one alignment coil within a microelectronic substrate, wherein the alignment coil may be powered to form a magnetic field to attract the magnetic alignment structure, thereby aligning the microelectronic device to the microelectronic substrate. After alignment, the microelectronic device may be electrically attached to the substrate. Embodiments may include additionally incorporating an alignment detection coil within the microelectronic substrate, wherein the alignment detection coil may be powered to form a magnetic field to detect variations in the magnetic field generated by the alignment coil in order verify the alignment of the microelectronic device to the microelectronic substrate.
    Type: Application
    Filed: November 14, 2015
    Publication date: May 18, 2017
    Applicant: Intel Corporation
    Inventors: Ankur Agrawal, Srinivas Moola, Sujit Sharan, Vijay Govindarajan
  • Publication number: 20170141008
    Abstract: Embodiments of heat spreaders with integrated preforms, and related devices and methods, are disclosed herein. In some embodiments, a heat spreader may include: a frame formed of a metal material, wherein the metal material is a zinc alloy or an aluminum alloy; a preform secured in the frame, wherein the preform has a thermal conductivity higher than a thermal conductivity of the metal material; and a recess having at least one sidewall formed by the frame. The metal material may have an equiaxed grain structure. In some embodiments, the equiaxed grain structure may be formed by squeeze-casting or rheocasting the metal material.
    Type: Application
    Filed: November 16, 2015
    Publication date: May 18, 2017
    Applicant: Intel Corporation
    Inventors: Aravindha R. Antoniswamy, Thomas J. Fitzgerald
  • Publication number: 20170140572
    Abstract: A mechanism is described for facilitating efficient processing of graphics commands at computing devices. A method of embodiments, as described herein, includes detecting a current object representing a bundled state of graphics commands in a command list to be processed at a graphics processor of a computing device, and evaluating the current object to determine a previous object bound to a first set of the graphics commands, where the first set of the graphics commands is associated with a first command state corresponding to the previous object. The method may further include copying a second set of the graphics commands to a command buffer associated with the command list, where the second set of the graphics commands represents a remainder of the graphics commands in the command list upon excluding the first set of the graphics commands. The method may further include facilitating the graphics processor to execute the second set of the graphics commands from the command buffer.
    Type: Application
    Filed: November 13, 2015
    Publication date: May 18, 2017
    Applicant: INTEL CORPORATION
    Inventors: MICHAEL APODACA, SIDDHARTH Y. DHARMADHIKARI
  • Patent number: 9652018
    Abstract: Methods and apparatus relating to multi-level CPU (Central Processing Unit) high current protection are described. In one embodiment, different workloads may be assigned different license types and/or weights based on micro-architectural events (such as uop (micro-operation) types and sizes) and/or data types. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventors: Efraim Rotem, Nir Rosenzweig, Doron Rajwan, Alon Naveh, Eliezer Weissmann
  • Patent number: 9652170
    Abstract: A memory device responding to device commands for operational controls. An embodiment of memory device includes one or more memory elements, a system element including a memory controller, and a physical interface including command input pins to receive commands for the memory device. The commands include commands for operational controls for the memory device, including one or both of a first command for a reset control to reset the memory device and a second command for a clock enable (CKE) control to halt internal clock distribution for the memory device.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventor: Pete Vogt
  • Patent number: 9650794
    Abstract: Some demonstrative embodiments include devices, systems of steering data radio bearer traffic to a wireless local area network link. For example, a User Equipment (UE) may include a Wireless Local Area Network (WLAN) transceiver; a cellular transceiver to communicate traffic of a plurality of Data Radio Bearers (DRBs) via a cellular link between the UE and an evolved Node B (eNB); and a controller to establish at least one Point-to-Point (P2P) link with the eNB via a WLAN link between the UE and a WLAN Access Point (AP), and to steer traffic of one or more of the DRBs from the cellular link to the P2P link.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: May 16, 2017
    Assignee: INTEL IP CORPORATION
    Inventors: Alexandre S. Stojanovski, Alexander Sirotkin, Pingping Zong
  • Patent number: 9652033
    Abstract: A system and method of securing data displayed to two or more individuals on two or more displays, wherein the two or more displays include a first display and a second display. One or more fixations of a first individual on the first display are determined. One or more fixations of a second individual on the second display are determined. A first frame buffer is associated with the first display. A second frame buffer is associated with the second display. Segments of the content in the first and second frame buffers are displayed while other segments are obfuscated.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventors: Ned M. Smith, Vincent Weafer, Alan Krassowski, Carl Woodward
  • Patent number: 9651997
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed An example apparatus to update a spatially adjustable display disclosed herein includes a display size monitor to acquire an indication of a size of the spatially adjustable display, a service image comparator to compare the indication of the size to a size model, and a source image adjuster to invoke visual configuration adjustments to an output image of the spatially adjustable display based on parameters identified in the size model.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventor: David W. Browning
  • Patent number: 9651961
    Abstract: Methods and systems to regulate a voltage with multiple selectable voltage regulator (VR) modes, using multiple corresponding circuits and/or a configurable circuit. The circuit may be configurable for one or more of a power-gate VR mode, a switched-capacitor VR (SCVR) mode, and a linear mode, such as a low drop-out (LDO) VR mode. A feedback controller, such as a proportional-integral-derivative (PID) controller, may configure and/or control a multi-mode VR for a selected VR mode. The feedback controller may select a VR mode based on a reference voltage and voltage ranges associated with the VR modes. The circuit may be configurable as banks of VRs, and the controller may be implemented to transition between VR modes by switching sub-banks between modes until the transition is complete.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventors: Ramnarayanan Muthukaruppan, Pradyumna Agashe, Uday Bhaskar Kadali, Jnaneshwar Madugonda
  • Patent number: 9651775
    Abstract: A MEMS micro-mirror device comprising, a MEMS micro-mirror, a support structure and, a first and second torsional arm which each connect the MEMS micro-mirror to the support structure, wherein the first and second torsional arms are arranged to define a first oscillation axis about which the MEMS micro-mirror can oscillate; a single actuation coil for oscillating the MEMS micro mirror about the first oscillation axis, at least a portion of the single actuation coil being arranged to cooperate with the MEMS micro mirror; a magnet which is arranged such that a magnetic field generated by the magnet submerges at least the portion of the single actuation coil which cooperates with the MEMS micro mirror; wherein the single actuation coil is configured to extend along the first and second torsional arms.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: May 16, 2017
    Assignee: INTEL CORPORATION
    Inventors: Julien Gamet, Faouzi Khechana
  • Patent number: 9651610
    Abstract: Visible laser probing is described. In one example a probe device has a laser configured to provide a laser beam at a visible wavelength, an objective lens positioned in front of the laser to focus the laser beam on an active region of an integrated circuit through a back side of an integrated circuit die, and a detector positioned to receive a reflected laser beam reflected from the active region through a back side of the die, through the objective lens. The detector is configured to detect an amplitude modulation of the reflected laser beam wherein the amplitude modulation is attributable to the electric field at the active region.
    Type: Grant
    Filed: June 29, 2013
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventors: Travis M. Eiles, Rajiv Giridharagopal, David Shykind
  • Patent number: 9651395
    Abstract: Navigation systems and associated methods for providing navigation services are provided. Information associated with a desired route for a vehicle, such as a route between a current location and a desired destination, may be determined. Additionally, contextual information associated with the vehicle may be identified. Based upon the desired route and the contextual information, a direction may be generated for presentation to one or more users, and the generated direction may be output for presentation.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventor: Barbara Rosario
  • Patent number: 9651672
    Abstract: A method and system for time synchronization in a mobile device are disclosed. The method includes negotiating a synchronization schedule. The synchronization schedule defines a plurality of synchronization times for receiving synchronization messages. The method further includes transitioning the mobile device from a first state to a second state to receive a synchronization message. The mobile device uses less power in the first state than the second state and the mobile device cannot receive the synchronization message when in the first state. The method further includes synchronizing a clock component in response to receiving the synchronization message.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: May 16, 2017
    Assignee: INTEL CORPORATION
    Inventors: Yaron Alpert, Haim Rochberger
  • Patent number: 9651978
    Abstract: Described are apparatuses and methods for power management. The apparatus may include a power gate including a plurality of current sources. The power gate may be coupled to a load. The apparatus may further include a voltage control circuit, coupled to the power gate, to determine and select one or more current sources of the plurality of current sources to supply to the load. The apparatus may further include a current control circuit, coupled to the voltage control circuit, to control individual current sources of the one or more current sources to output a constant current. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventors: Rupak Ghayal, Pradipta Patra, Ramnarayanan Muthukaruppan, Raghu Nandan Chepuri
  • Patent number: 9652418
    Abstract: Pipelining is included inside a register file memory. A register file memory device includes a static bitcell, and pipelined combinational logic. The combinational logic pipeline couples the I/O (input/output) node to the static bitcell. The pipeline includes multiple stages, where each stage includes a static logic element and a register element, where the operation of each stage transfers data through to a subsequent stage. The number of stages can be different for a read than a write. The multiple stages perform the operations to execute the read or write request.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventors: Shahid Ali, Shivraj Dharne
  • Patent number: 9653040
    Abstract: A semiconductor chip is described. The semiconductor chip includes a display controller having a driver. The display controller is configurable to select a first, a second, a third and a fourth different display interface. The driver is designed to drive respective signals for each of the first, second, third and fourth interfaces through a single output.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventors: Aruna Kumar, Prakash K. Radhakrishnan, Pravas Pradhan, Sunil Kumar C R, Vikas J
  • Patent number: 9652747
    Abstract: An embodiment allows for context based alerts/alarms. For example, an embodiment may automatically determine that a user is in a meeting with another person based on a meeting entry in the user's calendar. In such a situation the embodiment may divert an incoming phone call, which would ordinarily result in a ring tone, to go directly to voice mail based on the calendar entry. In an embodiment the alert may be delayed until the meeting concludes. Unlike conventional systems, various embodiments do not require a user to change notification rules, manually flip a hardware switch, or create a “Do Not Disturb” setting that allows just a single “silent” time during the day. An embodiment allows data in a calendar to automatically drive the behavior of how a notification panel operates. Other embodiments are described herein.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventor: Ashok Raj
  • Patent number: 9652774
    Abstract: Embodiments of techniques for distributing and rendering media content are provided. In response to a request for a first media file, a combined media file is generated having first and second segments that together include data from the first media file and from a second media file. The combined media file is then provided to a player module operable to render only data from the first media file during a first operating mode, and operable to render data from both the first and second media files during a second operating mode. For example, the first media file may be a music file, and the second media file an advertisement. A consumer may play the music portion without special software or a license, but the advertisement will be rendered as well. Alternatively, the consumer may purchase a license and use special playback software to render the music without the advertisement.
    Type: Grant
    Filed: August 9, 2010
    Date of Patent: May 16, 2017
    Assignee: INTEL CORPORATION
    Inventors: Adam Bruce Cappio, Jeffey Ayars
  • Patent number: 9652849
    Abstract: Stereo image reconstruction techniques are described. An image from a root viewpoint is translated to an image from another viewpoint. Homography fitting is used to translate the image between viewpoints. Inverse compositional image alignment is used to determine a homography matrix and determine a pixel in the translated image.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventors: Jianguo Li, Ying Zheng, Qiang Li, Yurong Chen
  • Patent number: 9653070
    Abstract: A disclosed speech processor includes a front end to receive a speech input and generate a feature vector indicative of a portion of the speech input and a Gaussian mixture (GMM) circuit to receive the feature vector, model any one of a plurality of GMM speech recognition algorithms, and generate a GMM score for the feature vector based on the GMM speech recognition algorithm modeled. In at least one embodiment, the GMM circuit includes a common compute block to generate feature a vector sum indicative of a weighted sum of differences squares between the feature vector and a mixture component of the GMM speech recognition algorithm. In at least one embodiment, the GMM speech recognition algorithm being modeled includes a plurality of Gaussian mixture components and the common compute block is operable to generate feature vector scores corresponding to each of the plurality of mixture components.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventors: Jenny Chang, Michael E. Deisher, Ravishankar Iyer
  • Patent number: 9653144
    Abstract: Methods, systems, and apparatuses relating to package on package memory refresh and self-refresh rate management are described. In one embodiment, an apparatus includes a processor die, a dynamic memory die mounted to and overlapping the processor die, a first thermal sensor of the processor die disposed adjacent to a first hot spot from a first type of workload and a second thermal sensor of the processor die disposed adjacent to a second hot spot from a second type of workload, and a hardware control circuit of the processor die to cause a refresh of a capacitor of the dynamic memory die when either of an output of the first thermal sensor exceeds a first threshold value and an output of the second thermal sensor exceeds a second threshold value.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventors: Xiuting C. Man, Stanley S. Kulick
  • Patent number: 9652237
    Abstract: A processor includes a logic for stateless capture of data linear addresses (DLA) during precise event based sampling (PEBS) for an out-of-order execution engine. The engine may include a PEBS unit with logic to increment a counter each time an instance of a designated micro-op is retired a reorder buffer, capture output DLA referenced by an instance of the micro-op that executes after the counter overflows, set a captured bit associated with a reorder buffer identifier for the instance of the micro-op, and store a PEBS record in a debug storage when the instance of the micro-op is retired from the reorder buffer. The designated micro-op references a DLA of a memory accessible to the processor.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventors: Roger Gramunt, Ramon Matas, Benjamin C. Chaffin, Neal S. Moyer, Rammohan Padmanabhan, Alexey P. Suprun, Matthew G. Smith
  • Patent number: 9653548
    Abstract: Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Marko Radosavljevic, Ravi Pillarisetty, Benjamin Chu-Kung, Niloy Mukherjee
  • Patent number: 9653559
    Abstract: A die includes a semiconductive prominence and a surface-doped structure on the prominence. The surface-doped structure makes contact with contact metallization. The prominence may be a source- or drain contact for a transistor. Processes of making the surface-doped structure include wet-vapor- and implantation techniques, and include annealing techniques to drive in the surface doping to only near-surface depths in the semiconductive prominence.
    Type: Grant
    Filed: December 27, 2011
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventors: Niloy Mukherjee, Gilbert Dewey, Marko Radosavljevic, Niti Goel, Sanaz Kabehie, Matthew V. Metz, Robert S. Chau
  • Patent number: 9653324
    Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a die having a first side and a second side disposed opposite to the first side. The IC package may further include an encapsulation material encapsulating at least a portion of the die and having a first surface that is adjacent to the first side of the die and a second surface disposed opposite to the first surface. In embodiments, the second surface may be shaped such that one or more cross-section areas of the IC package are thinner than one or more other cross-section areas of the IC package. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: May 16, 2017
    Assignee: INTEL IP CORPORATION
    Inventors: Sven Albers, Sonja Koller, Thorsten Meyer, Georg Seidemann, Christian Geissler, Andreas Wolter
  • Patent number: 9653411
    Abstract: An electronic package that includes a substrate; an electronic component mounted to a surface of the substrate; and a porous coating that includes grains of metal powder formed onto the electronic component by melting the metal powder onto the electronic component. An electronic package that includes a substrate; an electronic component mounted to a surface of the substrate; and a porous coating that includes grains of metal powder formed onto the substrate by melting the metal powder onto the substrate. An electronic package that includes a substrate; an electronic component mounted to a surface of the substrate; an initial mold covering the electronic component; and a porous coating that includes grains of metal powder formed onto the initial mold by melting the metal powder onto the initial mold.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventors: Donglai David Lu, Zhaozhi George Li, Matthew T. Magnavita, Amram Eitan, Peng Chen
  • Patent number: 9652236
    Abstract: A processor includes a logic to execute a first instruction and a second instruction. The first instruction is ordered before the second instruction. Each instruction references a respective logical register assigned to a respective physical register. The processor also includes logic to reassign a physical register of the second instruction to another logical register before retirement of the first instruction.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventors: Srikanth T. Srinivasan, Mark J. Dechene, Yury N. Ilin, Justin M. Deinlein, Christine E. Wang, Matthew C. Merten
  • Patent number: 9652609
    Abstract: The entry/exit architecture may be a critical component of a protection framework using a secure enclaves-like trust framework for coprocessors. The entry/exit architecture describes steps that may be used to switch securely into a trusted execution environment (entry architecture) and out of the trusted execution environment (exit architecture), at the same time preventing any secure information from leaking to an untrusted environment.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventors: Xiaozhu Kang, Alpa T. Narendra Trivedi, Siddhartha Chhabra, Prashant Dewan, Uday R. Savagaonkar, David M. Durham
  • Patent number: 9652259
    Abstract: The setting in a configuration register is controlled based on a value stored in a management register and/or based on generation of a reset signal during a debugging operation or detection of a malfunction or power state transition in an electronic system. The management register may allocate a single bit to each configuration register, and the setting to be loaded into the configuration register is to be controlled based on the value of the bit. Additionally, or alternatively, the setting in the configuration register may be controlled when the reset signal assumes a value indicating that a default setting is to be stored.
    Type: Grant
    Filed: October 1, 2011
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventors: Blaise Fanning, Anil K. Sabbavarapu
  • Patent number: 9652268
    Abstract: A processor includes support for executing binary-translated code including code modifications. The processor includes a processor core that includes a cache to store translation indicators from a physical map, each translation indicator to indicate whether a corresponding memory location includes translated code to be protected. The processor core also includes logic to execute a translated instruction. The translated instruction is translated from an instruction stored in a memory location. The processor core further includes logic to set a translation indicator in the cache corresponding to the memory location to indicate that it includes translated code to be protected. The processor core also includes logic to request senior store buffer drains of other processor cores of the processor based upon the execution of the translated instruction.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventors: John H. Kelm, David P. Keppel, David N. Mackintosh
  • Patent number: 9652270
    Abstract: Embodiments of apparatus and methods for virtualized computing are described. In embodiments, an apparatus may include one of more processor cores and a cache coupled to the one or more processor cores. The apparatus may further include a hypervisor operated by the one or more processor cores to manage operation of virtual machines on the apparatus, including selecting a part of the cache to store selected data or code of the hypervisor or one of the virtual machines, and locking the part of the cache to prevent the selected data or code from being evicted from the cache. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventors: Alexander Komarov, Anton Langebner
  • Patent number: 9652297
    Abstract: Various embodiments are generally directed to techniques for assigning portions of a task among individual cores of one or more processor components of each processing device of a distributed processing system. An apparatus to assign processor component cores to perform task portions includes a processor component; an interface to couple the processor component to a network to receive data that indicates available cores of base and subsystem processor components of processing devices of a distributed processing system, the subsystem processor components made accessible on the network through the base processor components; and a core selection component for execution by the processor component to select cores from among the available cores to execute instances of task portion routines of a task based on a selected balance point between compute time and power consumption needed to execute the instances of the task portion routines. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: May 16, 2017
    Assignee: INTEL CORPORATION
    Inventors: Liang You, Nan Qiao, Jun Jin
  • Patent number: 9652300
    Abstract: Systems and methods for the processing of EU threads (also known as warps) in a thread group. The status of each EU thread in the group may be monitored, to determine if it is executing or if it is halted and waiting at a synchronization barrier. If certain threshold conditions are met, the waiting EU threads may be preempted to allow execution of threads from another thread group. The threshold conditions may include a minimum number of EUs in use, a minimum number of EU threads in the first thread group that are waiting at the synchronization barrier and/or a maximum number of EU threads that are still executing, and a minimum wait time for one or more of the EU threads waiting at the barrier.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventor: Marek Targowski
  • Patent number: 9652321
    Abstract: Apparatus, systems, and methods for Recovery algorithm in memory are described. In one embodiment, a controller comprises logic to receive a read request from a host device to read a line of data to the memory device, wherein the data is spread across a plurality (N) of dies and comprises an error correction code (ECC) spread across the plurality (N) of dies, retrieve the line of data from the memory device, perform an error correction code (ECC) check on the line of data retrieved from the memory device, and invoke a recovery algorithm in response to an error in the ECC check on the line of data retrieved from the memory device. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventors: Ravi H. Motwani, Kiran Pangal
  • Patent number: 9652351
    Abstract: The present techniques include detecting a charger and remote host for a Type-C connector. An apparatus, system, and method are described herein. The apparatus comprises a USB Type-C port and a USB receiver detector. A charger and a remote host are differentiated based on the USB receiver detector.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventors: Amit Kumar Srivastava, Karthi R. Vadivelu