Abstract: An improved system of numerical description "in-the-large" of a program logic is used for global analysis of long-lived programs needed for perfective maintenance, including program enhancing and program reusing. Documentation "in-the-large" comprises linear program circuits, each circuit consisting of at least three non-routine logical parts consecutively following each other. A program circuit is individually numbered and its data-processing task is semantically described, creating a linear data flow (LDF). Documentation "in-the-large" is developed from the immediate environment of each logical part, this environment being represented by a numerical description of all links of this part with neighboring logical parts.

Abstract: A memory controller in which a number of local memories are primarily dedicated to the shared use of a number of local processors of a data processing system to increase the efficiency of use of both the processors and memories. A controller is associated with each local memory to control connection of any one of the local processors to its associated local memory. A local processor can also be connected via a controller and an adapter circuit connected to the controller to a system bus to obtain access to circuits connected thereto. In addition, a system processor connected to the system bus may also be connected to any particular one of the local memories via its associated controller and adapter connected thereto to load data or programs into the local memory for use by the local processors, and to read out the results of previous processing done by the local processors.

Abstract: A microprocessor is configured as two virtual processors having separate program counters, a common memory and a common execution unit. The processors are configured in a two stage pipeline arrangement and the instructions are interleaved so that as one processor fetches instructions the other executes. One processor runs a fixed length loop of single instructions to provide service of input/output pins at regular and frequent times to afford high resolution. The other processor runs multiple instruction routines. The instructions of either processor can modify the instructions of the other and determine whether a given instruction should be executed. The microprocesor is used as a coprocessor to relieve a main microprocessor of the burdens of managing I/O pins and of running some complex algorithms.

Abstract: A computer system which uses a main processor with main memory, and operates under a specialized software operating system, provides for checking the integrity of its compiler by use of software routines which permit an authorized user or an authorized program to authorize a file as a compiler and additionally will operate to identify any ordinary user and ordinary programs so as to prevent such ordinary user or ordinary program from authorizing a code file as a compiler.

Abstract: A node for obtaining access to a bus. In this arbitration method, the node receives a conditional grant. The node determines whether access to the bus will actually transfer to it. The node contains distributed logic that examines an extend bus cycle signal to determine whether it can become a transmitter to transfer messages on the bus. When the node becomes a transmitter, it generates an extend bus cycle signal to maintain access to the bus when executing a multi-cycle transfer, even though other nodes, perhaps with higher priorites, require access to the bus.

Abstract: An advance polling bus arbiter includes a priority selector for selecting during a polling cycle a highest priority source system unit which is seeking access to a system bus. Bus grant logic sends the highest priority source system a bus grant signal which indicates that the selected system unit can make a transfer during the next cycle. An advance link logic unit compares a target bus address received from the selected system unit to a local bus address and simultaneously signals an intersystem bus link of an impending intersystem transfer while the source system unit is receiving its bus grant signal.

Abstract: A printer controlled by a CPU in which a ROM having stored therein a control program executed by the CPU in replaceable. The ROM has stored therein identifying codes for identifying the control program stored in the ROM, and initializing data. A nonvolatile memory capable of being read out and written and having contents retained even if a power switch is turned off is provided with memory areas which can store respectively the identifying codes and the initializing data stored in the ROM in an identical array fashion. Each time the power switch is turned on, the identifying codes stored in the ROM are compared with identifying codes stored in the nonvolatile memory. If the identifying codes in the ROM and the identifying codes in the nonvolatile memory are inconsistent with each other, the identifying codes and the initializing data stored in the ROM are transferred and written respectively to the memory areas of the nonvolatile memory.

Abstract: A hard-wired circuit for sorting data including an input for receiving a new multibit word of a series of multibit words to be sorted, a plurality of comparators and respective storage devices, each comparator being connected to receive a sorted multibit word stored in its associated storage device and the new multibit word from the input and to compare the multibit words simultaneously with comparisons of other comparators and to provide a comparison output, and a controller responsive to the comparison outputs to store the new multibit word at a storage device such that it is in proper position with respect to sorted multibit words stored in other storage devices.

Abstract: A pattern generator and controller arrangement operates for controlling the component parts of an MRI system. The arrangement comprises a plurality of channels including a main control channel and output channels. The arrangement receives instructions from the system CPU which then leaves the control and outputting to the arrangement, thereby avoiding the necessity of a large expensive CPU to operate the system with versatility and speed.

Abstract: A memory accessible by more than one external processor has a data capacity exceeding the addressing capacity of the processors and is capable of modifying the addressing data of the processors.

Abstract: A memory system includes a plurality of memory modules, wherein the selection of one among the memory modules is performed in preselection as to the memory activation for a memory access operation on the basis of the previously performed selection of the same module for a preceding memory access operation and wherein, in case the performed preselection is not the appropriate one, the appropriate selection is first performed and then the memory access operation is "retried".

Abstract: A sorting technique which relies on the operating system collating weights of characters to the extent that a collating weight difference exists in any of the pairs of corresponding characters of two different strings of characters being compared. While this comparision is being made, the first tie of collating weights for a pair of nonidentical corresponding characters triggers a comparison of the ASCII code values of the two corresponding characters which tied. Assuming that such a tie has occurred, and if, after reaching the end of this process no differences in the collating weights of corresponding characters are found, then if one string has a corresponding character with a lower ASCII value, that string is considered to precede the other string in the alphabetic sequence.

Abstract: An improved method for access to data from a remote computer and an improved method for accessing remote heterogeneous data bases. The method includes a personal computer having an application program for processing data by keyboard input that operates on a local applications data base having files with a first file structure. A remote host computer accesses data in remote files having a second file structure. A preselected keystroke of the first computer modifies the data accession program of the remote computer to reformat retrieved data in the format of the personal computer applications program before transmission back to the personal computer, so that the personal computer resident portions of the program require no information as to where the requested data is located or what the host computer file structure is.

Abstract: A for controlling a includes circuit a register for holding the repetition number of a program operation to be repeated, a counter receiving the content of the register and adapted to decrement in response with each execution of the program operation to be repeated, a memory for storing a sequence of instructions, and a controller for receiving an instruction read from the memory modification in a normal condition and to convert the received instruction into a no-operation instruction when the content of the counter becomes a predetermined content.

Abstract: A system for coordinating the measurement activity of a plurality of emulators and their associated internal analyzers uses a bus with three signal lines. A READY signal is set false by any emulator that initiates a break (a transition from running user code to running a monitor). The READY signal is set false by the breaking emulator at the very beginning of its break, without waiting for the resumption of the monitor program. The false ready signal is detected immediately by the other emulators, which then break in sympathy. The READY signal is further used to restart all emulators in unsion. The emulator that initiated the break remains running its monitor, while the others start their monitors, determine that they did not cause the break, and then in anticipation of a restart, essentially suspend their monitors and prepare to start running user code. As each emulator becomes ready it releases the READY signal. As the last emulator becomes ready, it too releases READY, which then goes true.

Abstract: Apparatus and method for concurrent dispatch of instruction words which selectively comprise instruction components which are separately and substantially simultaneously received by distinct floating point and integer functional units. The instruction words are powers of 2 in length, (measured in terms of the smallest machine addressable unit) typically a 4 byte longword and an 8 byte quadword aligned to the natural boundaries also corresponding to powers of 2. To provide maximum operating efficiency, each functional (or processing) unit executes a component of an instruction word during an execution cycle. The type and length of the instruction word are indicated by one of the bit fields of the instruction word, which permits the apparatus to properly detect, store and transfer the instruction word to the appropriate functional unit.

Abstract: Modularly Structured Digital Communications System having Operations-Oriented Communication Means. The operations-oriented communication means are distributed in three structure levels such that operating technology apparatus program modules that are associated with types of terminal equipment are provided in a line technology task structure for generating logical operating technology status messages or for setting data for operating technology terminal equipment. A coordination program module for controlling the operations-oriented information and data flow is provided in a coordination task structure and at least one application program module for sequencing application-oriented functions is provided in an application task structure.

Abstract: A document data processing is disclosed including: a device for entering original data; an editing device for editing the original data into edited data; and a device for displaying a document corresponding to the edited data.

Abstract: A data flow type information processor includes a program storing portion, a data pair producing portion and a processing portion. In the data flow type information processor in executing a data flow program having a loop structure, a function for synchronizing with all of loop variables, that is, function for assuring that the value of all of the loop variables are determined in a loop execution stage to be considered, is applied to a group of instruction information for determining a loop termination.

Abstract: This invention measures the degree of clustering of an index for a relational data base table, estimates the number of physical page accesses required to access the table using a partial index scan using the index, and selects the index providing the fastest access path to the table. The degree of clustering is measured as follows:DC=Number of clustered rows (NCR)/Total rows (NR)A multiplier greater than 1 can be applied to the degree of clustering to reflect the benefit of having consecutively accessed rows on adjacent or nearby data pages.The degree of clustering so calculated is used to estimate the number of random and sequential page accesses required for a partial index scan. These numbers of accesses are then multiplied by the unit time required for each, and added to the total CPU processing time required to arrive at the estimated total time for the scan.