Patents Examined by Eugene R. LaRoche
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Patent number: 5402380Abstract: An object of the present invention is to provide a semiconductor device that permits easy and efficient testing. A nonvolatile semiconductor memory including word lines WLi and bit lines BLi, a memory cell matrix 17 including nonvolatile memory cells Cij, a sense amplifier 15, a write/erase timing circuit 9 for performing timing control necessary for write and erase operations, and a status register 2 for storing the operating state of the memory at the completion of the operation of the circuit 9, wherein there are provided, outside the address of the memory cell matrix 17, two kinds of dummy cells, D1, D2, D3, . . . , whose values are fixed to different values that induce different outputs from the sense amplifier 15. A pass condition or a fail condition is generated by accessing the dummy cells.Type: GrantFiled: February 7, 1994Date of Patent: March 28, 1995Assignee: Fujitsu LimitedInventors: Sinsuke Kumakura, Hirokazu Yamazaki, Hisayoshi Watanabe, Yasushi Kasa
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Patent number: 5402386Abstract: A row select circuit for semiconductor memories is disclosed. The row select circuit includes a decoder portion and a driver portion. The decoder potion of the row select circuit includes a plurality of decoder circuits, each servicing a multiplicity of rows. Two levels of decoding are used to select a row. First, one of the plurality of decoder circuits is selected. Second, a predecoder is provided for simultaneously selecting one of the multiplicity of rows serviced by the selected decoder circuit. A single current source is used to service the multiplicity of rows associated with a particular decoder. The driver portion of the circuit includes a driver circuit for each row. Each driver includes an inverter stage, a driver stage, a clamp and a voltage reference circuit. For a selected row, the driver circuit provides ultra-fast access time. For the deselected rows, the driver circuit consumes minimal power.Type: GrantFiled: July 15, 1993Date of Patent: March 28, 1995Assignee: Sun Microsystems, Inc.Inventors: Lee S. Tavrow, Mark R. Santoro, Gary W. Bewick
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Patent number: 5402373Abstract: A NAND cell type EEPROM has bit lines, each of which is associated with a NAND cell unit including a series array of four memory cell transistors. Each transistor is a MOSFET with a control gate and a floating gate for data storage. The memory cell transistors are connected at their control gates to word lines, respectively. One end of the NAND cell unit is connected through a first select transistor to a corresponding bit line; the other end thereof is connected via a second select transistor to a source voltage. The memory cell transistors and the select transistors are arranged in a well region formed in a substrate. In an erase mode, the bit line voltage, the substrate voltage and the well voltage are held at a high voltage, whereas the word lines are at zero volts. The gate potential of the select transistors is held at the high voltage, whereby the internal electric field of these select transistors is weakened to improve the dielectric breakdown characteristic thereof.Type: GrantFiled: February 24, 1994Date of Patent: March 28, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Seiichi Aritome, Riichiro Shirota, Ryouhei Kirisawa, Yoshihisa Iwata, Masaki Momodomi
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Patent number: 5402390Abstract: Switching circuits controlled by a fuse that can be blown after testing the DRAM part select the timing signals coupled from a binary counter to internal signal generator circuits. The internal Circuits control self refresh in this embodiment. The decision to leave the fuse intact or blow the fuse rests on the test results obtained from each part and can vary depending upon maturity of the manufacturing process, the pause test results obtained and whether a low power part is desired. The fuse is affected after fabrication of the chip and at the same time as other fuses used for redundancy. This provides another degree of freedom in the manufacture of integrated circuits.Type: GrantFiled: October 4, 1993Date of Patent: March 28, 1995Assignee: Texas Instruments Inc.Inventors: Duc Ho, Duy-Loan T. Le, Kenneth A. Poteet, Scott E. Smith
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Patent number: 5402379Abstract: A method and apparatus for an improved precharge device for an internal bus of an integrated circuit. Multiple precharge devices connect to signal lines throughout an internal bus. The multiple precharge devices are distributed along the internal as opposed to a single precharge device at one end utilized prior thereto. The present invention reduces the time necessary to precharge signal lines due to the decreased effective RC time delay affecting each precharge device.Type: GrantFiled: August 31, 1993Date of Patent: March 28, 1995Assignee: SGS-Thomson Microelectronics, Inc.Inventor: David C. McClure
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Patent number: 5402377Abstract: A semiconductor memory device has a primary memory cell array, a primary decoder having a first circuit producing an intermediate signal from an address signal and a second circuit producing a first cell selection signal from the intermediate signal for selectively driving a word line and a bit line, an auxiliary memory cell array having a plurality of memory cells, each being used for a defective memory cell found in the primary memory cell array, an auxiliary decoder connected to the primary decoder to receive the intermediate signal, a non-volatile memory for storing first information indicating that the primary memory cell array contains a defective memory cell from which a cell defect signal is produced and for storing second information indicating an address of the defective memory cell from which a defective cell address signal is produced, and a control circuit responsive to the cell defect signal and the defective cell address signal for producing a first control signal to be supplied to the second cType: GrantFiled: May 17, 1994Date of Patent: March 28, 1995Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Kenichi Ohhata, Hiroaki Nambu, Kazuo Kanetani, Youji Idei, Takeshi Kusunoki, Toru Masuda
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Patent number: 5400279Abstract: An electrically erasable programmable read-only memory has an array of programmable memory cells connected to parallel bit lines on a semiconductive substrate. The memory cells include NAND cell blocks each of which has a first selection transistor coupled to a corresponding bit line, a second selection transistor coupled to the ground potential, and a series array of memory cell transistors each having a floating gate and a control gate. Word lines are respectively connected to the control gates of the memory cell transistors. In a data read mode, a selection transistor of a certain NAND cell block including a selected memory cell transistor is rendered conductive to connect this cell block to a bit line associated therewith.Type: GrantFiled: May 26, 1993Date of Patent: March 21, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Masaki Momodomi, Yasuo Itoh, Yoshihisa Iwata, Fujio Masuoka, Masahiko Chiba
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Patent number: 5400284Abstract: A precharge transistor precharges a bus. A discharge transistor discharges the bus. A push-pull driver is connected to the bus, and consists of a p-channel MOS transistor and an n-channel MOS transistor. The push-pull driver sets the potential of the bus to "H" level or "L" level. A detection circuit detects which one of the discharge transistor and the push-pull driver is being driven. When the push-pull drive is being driven, a control circuit renders the precharge transistor inoperative.Type: GrantFiled: December 22, 1993Date of Patent: March 21, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Shingo Hanatani, Kazumasa Ando
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Patent number: 5400282Abstract: A semiconductor memory device having a normal mode of reading and writing data from and to a selected memory cell of a memory cell array. The semiconductor memory device is characterized by control means for switching the normal operation mode to a test mode in response to a test mode signal applied to a certain input terminal, selecting all desired memory cells of the memory cell array at a time, and allowing data applied to a data input terminal to be written to all the selected and desired memory cells at one time.Type: GrantFiled: July 17, 1992Date of Patent: March 21, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Youichi Suzuki, Makoto Segawa, Toshiaki Ohno, Sumako Shiraishi
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Patent number: 5400314Abstract: An optical pickup for use in various optical recording/reproducing apparatus includes a general-purpose lamp producing a wide range of light wavelengths, a converging device for converging the light of the lamp, and a pinhole and color filter for enhancing the temporal/spatial coherence of the light. The lamp radiates light containing the intensity of a laser and spectral distribution characteristic of a laser.Type: GrantFiled: November 29, 1993Date of Patent: March 21, 1995Assignee: Samsung Electronics Co., Ltd.Inventor: Chul-woo Lee
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Patent number: 5400295Abstract: In a semiconductor integrated circuit device having a data latch function, one of two inverters constituting a data latch circuit is formed of a PMOS transistor and an NMOS transistor, with the source terminal of the NMOS transistor being connected to a terminal for applying a reset signal. The reset signal is applied to an inverter through the NMOS transistor, and the inverter inverts the reset signal and resets the data latch circuit. Since one inverter of the data latch circuit is formed of the PMOS transistor and the NMOS transistor, the setting/resetting function of the semiconductor integrated circuit device can readily be implemented.Type: GrantFiled: November 13, 1992Date of Patent: March 21, 1995Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tetsuya Matsumura, Satoshi Kumaki, Shinichi Nakagawa
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Patent number: 5400274Abstract: A synchronous memory (50) having a looped global data line (80) reduces a difference between minimum and maximum propagation delays between different locations in a memory array (51) during a read cycle of the memory (50). The looped global data line (80) has a first portion (80') and a second portion (80"). The first portion (80') extends along an edge of the memory array (51) in a direction substantially parallel to a direction of the word lines of the array (51). Sense amplifiers (73-78) are coupled to the first portion (80') of the looped global data line (80). At one end of the array (51), the second portion (80") of the looped global data line extends back in an opposite direction to the first portion (80') and is coupled to output data circuits (84). Reducing the difference in propagation delays improves noise margins and allows increased operating speed.Type: GrantFiled: May 2, 1994Date of Patent: March 21, 1995Assignee: Motorola Inc.Inventors: Kenneth W. Jones, Lawrence F. Childs
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Patent number: 5400292Abstract: A dynamic type semiconductor memory device includes a plurality of data input/output nodes, a plurality of /CAS buffers for generating column address strobe signals corresponding to each of said input/output nodes, and an input node carrying out only data input. A switching signal generation circuit generates first and second switching signals indicating data input/output control modes. Memory cells corresponding in number to the data input/output nodes are selected simultaneously from a memory cell array. In operation of control mode A, data input/output is effected using an input node and one data input/ouput node. In the case of control mode B, data writing/reading is effected via a plurality of data input/output nodes according to one column address strobe signal. In the case of control mode C, data input/output is carried out individually for each input/output node according to a plurality of column address strobe signals. Modes A, B and C can be realized in one DRAM.Type: GrantFiled: November 22, 1993Date of Patent: March 21, 1995Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takahiko Fukiage, Yoshinori Inoue
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Patent number: 5400277Abstract: A resistor is connected to the source/drain of a transistor and used as a load element of a memory cell. A trench is formed which extends from a top of the wafer through an isolation region of the wafer to a silicon base of the wafer. The silicon base of the wafer is located below the isolation region of the wafer. A resistive layer of material is formed in the trench. The resistive layer extends from the top of the wafer through the isolation region of the wafer and is electrically connected to the silicon base of the wafer. The resistor is connected to other circuitry on the wafer, for example, by implanting into the wafer atoms of a first conductivity type into a region immediately adjacent to the resistive layer of material in the trench. In the preferred embodiment, the resistive layer of material is deposited polysilicon.Type: GrantFiled: October 29, 1993Date of Patent: March 21, 1995Assignee: VLSI Technology, Inc.Inventor: Edward D. Nowak
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Patent number: 5400319Abstract: A machine-readable serial number is formed on a CD-ROM by using a laser to selectively remove a reflective layer from the CD-ROM. Removal of the reflective layer creates defects in addressable information storage locations on the CD-ROM. The serial number is read by detecting the defects. The serial number is used in a software distribution system in which many different software programs are distributed on a single CD-ROM and an access code based on the desired software program and the serial number of a particular CD-ROM is used to "unlock" the desired program on the particular CD-ROM.Type: GrantFiled: October 6, 1993Date of Patent: March 21, 1995Assignee: Digital Audio Disc CorporationInventors: Barry A. Fite, Michael L. Mitchell, Russ A. Kunz, Clifford R. Brannon
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Patent number: 5398207Abstract: A MOS dynamic random access memory device has a memory cell array section formed on a semiconductor substrate, including memory cells each having a data storage capacitor and a transfer-gate transistor. Parallel bit lines are associated with the memory cell array section. Parallel word lines extend transverse to the bit lines, including a word line connected to the transfer-gate transistor. A booster circuit is arranged to provide a potentially raised voltage which is higher than a power supply voltage. A sense amplifier circuit is connected with a corresponding bit line pair of the word lines. A word-line driver circuit has an input connected to the booster circuit and an output connected to the word line. A bit-line restoring circuit is connected to the sense amplifier circuit.Type: GrantFiled: May 28, 1993Date of Patent: March 14, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Kenji Tsuchida, Takashi Ohsawa
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Patent number: 5398204Abstract: It is an object of the invention to provide a nonvolatile semiconductor system, particularly a flash (entire array erasure) type EEPROM, of which reading operation can be prevented from failing even if any one memory transistor is overerased. When the data reading operation is carried out for a memory transistor 1, an N-channel transistor 6 is turned off, and P-channel transistors 7 and 8 are also turned off, since a word line WL2 is at GND level. Even if a memory transistor 3 is overerased, for example, a drain current can be prevented from flowing from a bit line BL1 to a source power, which also prevents wrong reading operation. Even if any one memory transistor is overerased and not selected, a wrong reading operation can be prevented since no electric current flows from the bit line. Thus, any means for preventing the overerasing, such as verifying operation means or the like, is not required.Type: GrantFiled: November 8, 1993Date of Patent: March 14, 1995Assignee: Seiko Epson CorporationInventor: Akira Maruyama
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Patent number: 5398205Abstract: A semiconductor memory device including a plurality of memory cells of one-transistor and one-capacitor type is disclosed.Type: GrantFiled: May 9, 1994Date of Patent: March 14, 1995Assignee: NEC CorporationInventor: Shinsuke Yamaguchi
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Patent number: 5398212Abstract: A semiconductor memory device according to the present invention includes: a memory cell array including (2.sup.n +m) memory cells, wherein n and m are integers satisfying the relationship 2.sup.n <2.sup.n +m<2.sup.n+1 ; an address decoder for receiving an address signal of (n+l) bits and for specifying one of the (2.sup.Type: GrantFiled: March 30, 1994Date of Patent: March 14, 1995Assignee: Sharp Kabushiki KaishaInventors: Koji Imura, Mikiro Okada, Yukimine Shimada
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Patent number: 5398203Abstract: A non-volatile memory device is described. The memory device includes a memory array and current regulating circuitry coupled to the memory array. The memory array includes a first memory cell coupled to a first bit line and a second memory cell coupled to a second bit line such that the first memory cell receives a first current during programming of the first memory cell and the second memory cell receives a second current during programming of the second memory cell. The current regulating circuitry regulates the first and second currents during programming of the first and second memory cells such that when the first cell is being programmed and the second cell is not being programmed, the circuitry limits the first current flowing through the first bit line for programming the first memory cell to be substantially equivalent to the first current if the first and second memory cells are being programmed substantially at the same time.Type: GrantFiled: September 1, 1993Date of Patent: March 14, 1995Assignee: Cypress Semiconductor CorporationInventor: Bruce Prickett, Jr.