Patents Examined by Eugene R. LaRoche
  • Patent number: 5398135
    Abstract: A zoom lens is constructed by two lens groups in which a first lens group having a positive focal length is arranged on an object side and a second lens group having a negative focal length is arranged on an image side. A zooming operation is performed by changing a distance between the first and second lens groups. The first lens group has first to fourth lenses sequentially arranged from the object side toward the image side. The first lens is constructed by a positive meniscus lens having a convex face directed onto the object side. The second lens is constructed by a biconcave lens. The third lens is constructed by a positive lens. The fourth lens is constructed by a biconvex lens. The second lens group has fifth to seventh lenses sequentially arranged from the object side toward the image side. The fifth lens is constructed by a positive meniscus lens having a convex face directed onto the image side.
    Type: Grant
    Filed: March 4, 1993
    Date of Patent: March 14, 1995
    Assignee: Ricoh Company, Ltd.
    Inventor: Kazuyasu Ohashi
  • Patent number: 5396467
    Abstract: A two-phase sense amplifier includes a data sensing circuitry including a presetting current detecting circuit for allowing the sense amplifier to be in a presetting phase when an X-decoder decodes an address of a selected word line of a selected memory cell and a Y-decoder decodes an address of a selected bit line of the selected memory cell and then for setting a voltage level of the selected bit line to be around a switching point and an evaluating current detecting circuit for allowing the sense amplifier to be in an evaluating phase after the voltage level of the selected bit line is around the switching point in order to sense a current in the selected cell for converting the current into a voltage output, a dummy cell circuitry electrically connected to the data sensing circuitry for providing a reference voltage to the data sensing circuitry, and a differential amplifier electrically connected to the data sensing circuitry and the dummy cell circuitry for accepting and comparing the voltage output and
    Type: Grant
    Filed: March 30, 1994
    Date of Patent: March 7, 1995
    Assignee: United Microelectronics Corp.
    Inventors: Ding-Jen Liu, Jyh-Jen Cho
  • Patent number: 5396463
    Abstract: A data output circuit of a semiconductor memory circuit with pull-up and pull-down transistors for outputting data through complementary switching operation, comprising a pre-charge means for pre-charging a pair of data signals read from a memory cell having a given voltage level in a first operational mode, a switching means for connecting the output signal of the pre-charge means amplified to the gates of the pull-up and pull-down transistors, and an enable circuit for connecting the output signal of the switching means to the gates of the pull-up and pull-down transistors in a second operational mode. The switching means is a level change circuit to control the pull-up and pull-down transistors, which are data output drivers, by employing a constant voltage source to provide a voltage rise Vpp increased over the source voltage level Vcc of an integrated circuit before enabling the integrated circuit.
    Type: Grant
    Filed: November 9, 1992
    Date of Patent: March 7, 1995
    Inventors: Young-Rae Kim, Yun-Sang Lee
  • Patent number: 5396449
    Abstract: A content addressable memory in accordance with the present invention includes a number of bistable memory cells having as inputs thereto first and second bit lines and an address line, and a COMPARE circuit connected to each of the memory cells so as to provide the COMPARE function without loading the first and second bit lines and including means for inhibiting current flow when a miscompare occurs.
    Type: Grant
    Filed: December 21, 1993
    Date of Patent: March 7, 1995
    Assignee: International Business Machines Corporation
    Inventors: Francois I. Atallah, Stacy J. Garvin, David W. Nuechterlein
  • Patent number: 5396458
    Abstract: In a semiconductor memory device, when positive high voltages are respectively applied to a control gate(20) and a drain region(14) and a source region(13) is grounded, hot electrons are produced in the boundary between the drain region(14) and a channel region. The hot electrons are injected into a floating gate(18) through a tunnel oxide film(17). Consequently, information is written. At the time of reading out information, the drain region(14) is grounded, a positive read voltage is applied to the source region(13), and a predetermined sense voltage is applied to the control gate(20). At this time, the area between the source and the drain is kept in a non-conduction state if electrons are stored in the floating gate(18), while conduction occurs between the source and the drain if no electrons are stored therein. Since no hot electrons are produced in the boundary between the drain region(14) and the channel region at the time of reading, it is possible to effectively prevent so-called soft writing.
    Type: Grant
    Filed: October 20, 1992
    Date of Patent: March 7, 1995
    Assignee: Rohm Co., Ltd.
    Inventor: Noriyuki Shimoji
  • Patent number: 5396448
    Abstract: The associative memory capable of improving the efficiency in replacing an entry and testability of compare operation. The associative memory includes a Content Addressable Memory (CAM) cell array for executing a compare operation; a Random Access Memory (RAM) cell array for operating responsive to a result of the CAM cell array; and a HIT entry number detection circuit for receiving a result of the compare operation in the CAM cell array and outputting a HIT entry number.
    Type: Grant
    Filed: April 23, 1992
    Date of Patent: March 7, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshinari Takayanagi, Masanori Uchida
  • Patent number: 5396471
    Abstract: A data protection circuit includes an address detection circuit latch circuit and replacing circuit. The address detection circuit,detects that an address signal for designating an address of a semiconductor memory has designated a specified address. The latch circuit latches a detection output of the address detection circuit. The replacing circuit replaces at least one bit of the address signal by readout data of the semiconductor memory in response to a latch output of the latch circuit.
    Type: Grant
    Filed: March 23, 1994
    Date of Patent: March 7, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroo Kitsu
  • Patent number: 5396462
    Abstract: Diodes are connected between a clamp control line and respective one of data lines. A voltage of the clamp control line in a read operation is set to a value higher, by a forward voltage of the diodes or less, than a lower value among the voltages of the data line to which a selected digit line is connected. The voltages of the data lines to which only non-selected digit lines are connected are clamped to a predetermined value.
    Type: Grant
    Filed: August 5, 1993
    Date of Patent: March 7, 1995
    Assignee: NEC Corporation
    Inventor: Tomoyuki Kaneko
  • Patent number: 5396455
    Abstract: A non-volatile random access memory is described incorporating a plurality of memory cells, each memory cell having a Hall effect device including amorphous magnetic material and a switch for directing current through the flail effect device. An array of memory cells are interconnected by word lines, current lines, and bit lines. The invention overcomes the problem of a rugged non-volatile random access memory with long term reliability.
    Type: Grant
    Filed: April 30, 1993
    Date of Patent: March 7, 1995
    Assignee: International Business Machines Corporation
    Inventors: Michael J. Brady, Richard J. Gambino, Lia Krusin-Elbaum, Ralph R. Ruf
  • Patent number: 5396468
    Abstract: Various optimizing techniques are used for erasing semiconductor electrically erasable programmable read only memories (EEPROM). An erase algorithm accomplishes erasing of a group of memory cells by application of incremental erase pulses. Techniques include a 2-phase verification process interleaving between pulse applications; special handling of a sample of cells within each erasable unit group; defects handling; and adaptive initial erasing voltages. A streamlined write operation on a flash sector of the EEPROM is implemented by employing the optimized erase in an efficient manner. The write operation includes an initial quick erase of the sector followed by programming of data and verification. Only on those infrequent occasions when a failure occurs as manifested during program verification that the optimized erase will need be evoked.
    Type: Grant
    Filed: November 8, 1993
    Date of Patent: March 7, 1995
    Assignee: SunDisk Corporation
    Inventors: Eliyahou Harari, Daniel C. Guterman, Sanjay Mehrotra, Stephen J. Gross, John S. Mangan
  • Patent number: 5396452
    Abstract: A dynamic random access memory. The memory includes a write transistor N3 and a read transistor N2. In a preferred embodiment the write transistor has a threshold level higher than the read transistor. A sense amplifier senses and amplifies a difference in voltage between a bit line and a sense node that is developed when the read transistor permits or does not permit current to flow between ground an a bit line. Associated semiconductor device structures and fabrication techniques are also disclosed.
    Type: Grant
    Filed: July 2, 1993
    Date of Patent: March 7, 1995
    Inventor: Sven E. Wahlstrom
  • Patent number: 5396454
    Abstract: A memory cell includes gated diodes as load elements. For example, the memory cell includes a word line, a bit line, an inverted bit line, a ground line, a power line, a first transistor, a second transistor, a third transistor, a fourth transistor, a first gated diode and a second gated diode. The first transistor has a first end connected to the inverted bit line, a second end, and a gate connected to the word line. The second transistor has a first end, a second end connected to the bit line, and a gate connected to the word line. The third transistor has a first end connected to the second end of the first transistor, a second end connected to the ground line, and a gate connected to the first end of the second transistor. The fourth transistor has a first end connected to the first end of the second transistor, a second end connected to the ground line, and a gate connected to the second end of the first transistor.
    Type: Grant
    Filed: September 24, 1993
    Date of Patent: March 7, 1995
    Assignee: VLSI Technology, Inc.
    Inventor: Edward D. Nowak
  • Patent number: 5396465
    Abstract: A semiconductor memory device has adjacent memory arrays and isolation transistors disposed between a common bit sense amplifier and the memory arrays. An isolation control circuit according the present invention generates the power supply voltage Vcc (not the boost voltage Vpp) during the burn-in mode of operation, so that the gate oxide layer of the isolation transistors is prevented from being destroyed or deteriorated.
    Type: Grant
    Filed: November 24, 1993
    Date of Patent: March 7, 1995
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Cheol Oh, Yong-Sik Seok
  • Patent number: 5396469
    Abstract: An SRAM comprising a plurality of SRAM storage cells connected in a plurality of rows and columns. Each storage cell has four terminals. Two terminals provide power for the storage cell, and two terminals are data terminals used in reading and writing the storage cell. The data terminals are connected to first and second bit lines in the storage cell's column via coupling transistors that are controlled by word lines associated with the various rows, there being two such bit lines associated with each column. The memory includes a power system that maintains a first potential difference between the power terminals of a storage cell when the storage cell is being read and a second potential difference between the power terminals when the storage cell is being written. The absolute value of the second potential difference is less than the absolute value of the first potential difference. This arrangement reduces the swing in potential on the bit lines needed to write a storage cell.
    Type: Grant
    Filed: March 31, 1994
    Date of Patent: March 7, 1995
    Assignee: Hewlett-Packard Company
    Inventor: Natsuki Kushiyama
  • Patent number: 5396466
    Abstract: A method of testing bit lines of a memory unit includes the steps of alternately writing a set of first binary values and a set of inverted first binary values to blocks having even block values and to blocks having odd block values for all storage elements within each of a plurality of blocks of the memory unit; setting the memory unit to a stressed condition; alternately reading pieces of binary data from first-row storage elements of the blocks having even block values and from final-row storage elements of the blocks having odd block values by repeatedly inverting a row value of a memory address and incrementing a block value of the memory address for each block; setting the memory unit to a normal condition; and repeating the first setting step, the alternate reading step, and the second setting step for all the columns of the plurality of the blocks.
    Type: Grant
    Filed: March 17, 1994
    Date of Patent: March 7, 1995
    Assignee: Fujitsu Limited
    Inventors: Rikizo Nakano, Noriyuki Matsui
  • Patent number: 5396480
    Abstract: A laser beam is radiated on a recording medium such as a phase transition type optical disk to change optical characteristics depending on a change in arrangement of atoms in a recording layer of the recording medium so as to repetitively record/erase information represented by the lengths of optical marks, the recording power of the laser beam radiated to record the information in the recording medium is changed stepwise in two or more power levels sequentially higher than an erasure power level of a laser beam radiated to erase the information recorded in the recording medium.
    Type: Grant
    Filed: November 24, 1993
    Date of Patent: March 7, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoki Morishita, Naomasa Nakamura, Katsumi Suzuki, Tadashi Kobayashi
  • Patent number: 5394355
    Abstract: A read only memory includes a memory cell provided at an intersection between a word line and a bit line, and a plurality of reference potential transmission lines each receiving a reference potential determined in accordance with an externally applied potential designating signal. The memory cell includes a transistor element having a gate coupled to a word line, a drain coupled to a bit line and a source which is coupled to one of the reference potential transmission lines or is held in an open state. Stored data in the memory cell is changed by switching the potentials of the reference potential transmission lines. This enables storing of different data bits in one memory cell.
    Type: Grant
    Filed: August 20, 1993
    Date of Patent: February 28, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shinichi Uramoto, Tetsuya Matsumura, Masahiko Yoshimoto, Kazuya Ishihara, Hiroshi Segawa
  • Patent number: 5394375
    Abstract: A row decoder for a semiconductor memory device is disclosed which includes a plurality of decoding circuits each driving a corresponding one of word lines in response to first and second control signals associated therewith. Each of the decoding circuits includes a first node supplied with the first control signal, a second node supplied with the second control signal, a first transistor connected between the first node and the corresponding word line and turned ON when the second control signal takes an active level, and a second transistor connected between the corresponding word line and a reference potential terminal and turned ON when the second control signal takes an inactive level.
    Type: Grant
    Filed: April 8, 1993
    Date of Patent: February 28, 1995
    Assignee: NEC Corporation
    Inventor: Shinichi Iwashita
  • Patent number: 5394363
    Abstract: A pulse write driver circuit comprising a first NAND gate for inputting a write enable signal and a data input transfer negative signal, a second NAND gate for inputting the write enable signal and a data input transfer positive signal, an odd number of first inverters for sequentially inverting an output signal from the first NAND gate, a first NOR gate for inputting the output signal from the first NAND gate and an output signal from the first inverters, an odd number of second inverters for sequentially inverting an output signal from the second NAND gate, a second NOR gate for inputting the output signal from the second NAND gate and an output signal from the second inverters, an odd number of third inverters for sequentially inverting the write enable signal, a third NOR gate for inputting the write enable signal and an output signal from the third inverters, a fourth NOR gate for inputting output signals from the first to third NOR gates, and a fourth inverter for inverting an output signal from the fou
    Type: Grant
    Filed: December 29, 1993
    Date of Patent: February 28, 1995
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Gwang M. Han
  • Patent number: 5394361
    Abstract: Maximum operating speed is achieved in an array of memory cells by performing both read and write operations within a single memory cycle. As outgoing data are read from the memory cells, incoming data are stored immediately in those cells. Reduced power consumption is achieved in such memories by preventing the occurrance of a write operation if the value of a bit to be written to a memory cell is the same as the value of the bit currently stored in that memory cell. More particularly, the result of a read operation on a particular memory cell is compared with the data value to be written to that cell to determine whether a subsequent write operation is required. If the value in the cell equals the value to be written, the write operation is not performed.
    Type: Grant
    Filed: October 22, 1992
    Date of Patent: February 28, 1995
    Assignee: AT&T Corp.
    Inventor: Alexander G. Dickinson