Patents Examined by Phillip Vales
  • Patent number: 5623505
    Abstract: An information data detecting apparatus for use in a recording medium playing apparatus detects the presence/absence of information data under software control using an error correction code. The information data detecting apparatus acquires a read signal representing the contents of a specified sector, extracts digital data from the read signal, performs an error-correcting operation on the extracted digital data and produces an error-correctable indicating flag when error correction is possible. When detecting the presence of the error-correctable indicating flag, the information data detecting apparatus produces a written-state signal indicating that the specified sector is used.
    Type: Grant
    Filed: November 8, 1994
    Date of Patent: April 22, 1997
    Assignee: Pioneer Electronic Corporation
    Inventors: Kyota Funamoto, Takashi Morimae, Ken Masui
  • Patent number: 5404495
    Abstract: A microcomputer having an error correction function includes a summing function for calculating a total-sum of data associated with a block of stored data, a total-sum changing function for calculating a new total sum of data associated with the block of stored data when new data is stored in the block of stored data, the new total sum of data being based on an equation S.sub.new =S.sub.old +X.sub.new -X.sub.old, where, X.sub.new denotes new data replacing old data X.sub.old, and S.sub.
    Type: Grant
    Filed: November 7, 1991
    Date of Patent: April 4, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Hiroshi Yoneda
  • Patent number: 5390323
    Abstract: The invention provides a method and apparatus for logging all references to microstore addresses irrespective of the number of times that a same address is referenced and irrespective of the order in which addresses are referenced. It provides a log indicating simply whether each address of the microstore has or has not been referenced within a prescribed time period. There is no limit placed on the duration of the prescribed time period and thus logging can cover long-term events such as, the full execution of a single macro-instruction, the full execution of an assembly level routine or the execution of all micro-instructions resident in the microstore as they are subjected to all possible input parameters. A practical tool for global visualization of computer operations is therefore provided.
    Type: Grant
    Filed: August 5, 1991
    Date of Patent: February 14, 1995
    Assignee: Amdahl Corporation
    Inventors: Linda Newell, Matt Noel
  • Patent number: 5333139
    Abstract: A method in which the boundary-scan circuitry of a boundary-scan chain is placed in a first condition in which each bit of a series of bits will traverse a path through an equipment identification register if one exists or will require one clock to traverse each device in the boundary-scan chain in which no complete identification register exists. A first recognizable series of bits is sent through the chain and the beginning of the series of bits is detected at the output of the chain while a count is kept at the output to determine the number of individual boundary-scan circuits in the chain. The count is incremented by one for each identification register traversed or for each circuit which has no such complete register.
    Type: Grant
    Filed: December 30, 1992
    Date of Patent: July 26, 1994
    Assignee: Intel Corporation
    Inventor: Jay J. Sturges
  • Patent number: 5319626
    Abstract: A method for rewriting four defect management areas on an optical disk according to an ECMA standard is performed by means of deleting an old data which has been recorded on the respective defect management areas and then sequentially writing down a new data on respective defect management areas.
    Type: Grant
    Filed: August 26, 1991
    Date of Patent: June 7, 1994
    Assignees: Mitsubishi Electric Corporation, Teac Corporation
    Inventors: Minoru Ozaki, Kyosuke Yoshimoto, Hiroyuki Onda, Koji Yamana, Takuya Nagata, Hidehiko Murata, Yutaka Kobayashi
  • Patent number: 5313464
    Abstract: A symbol interleaving method for organizing data in a semiconductor memory such that fault tolerance of the memory is optimized when used in conjunction with a Reed-Solomon burst error correcting code. The Reed-Solomon symbols are aligned with respect to the bus bits of the memory such that the impact of a bus bit failure that affects all memory devices in the memory using the bus is constrained within the correction capability of the ECC. The symbols also are distributed among the memory devices in order to maximize fault tolerance. Up to two memory devices in the preferred embodiment may fail without exceeding the correction capability of the code.
    Type: Grant
    Filed: May 5, 1992
    Date of Patent: May 17, 1994
    Assignee: Digital Equipment Corporation
    Inventor: Francis H. Reiff
  • Patent number: 5299208
    Abstract: Decoding power is enhanced by (1) flagging only those codewords where the ECC capability has been exceeded; (2) permitting codewords to be of any byte length (n) and codeword depth (.lambda.) subject only to the requirement that n and .lambda. be relatively prime; and (3) interleaving encoded bytes of successive codewords diagonally in a single continuous sequence to form an array with a toroidal topology so that all burst errors will be continuous from codeword to codeword, irrespective of where they occur in the array. These attributes assure that there will never be a problem with burst errors affecting.ltoreq..lambda. rows because there is no "last row" and "first row".
    Type: Grant
    Filed: November 14, 1991
    Date of Patent: March 29, 1994
    Assignee: International Business Machines Corporation
    Inventors: Miguel M. Blaum, Henricus C. Van Tilborg