Abstract: A solid state drive includes DRAM logical flash and flash memory, in which system processor reads and writes only to the DRAM logical flash which minimizes writes to the flash memory. A method for operation of a solid state flash device includes writing, by a CPU, to a solid state drive by sending commands and data to DRAM logical flash using flash commands and formatting.

Abstract: A solid state drive (SSD) includes dynamic random access memory (DRAM), flash memory, and a solid state drive (SSD) controller. The solid state drive (SSD) also includes a peripheral component interconnect express (PCIe) bus to connect the SSD to a computing device such that a central processing unit (CPU) of the computing device exclusively reads data from, and writes data to, the DRAM. The SSD controller writes data to the flash memory from the DRAM independently of received commands from the computing device.

Abstract: A solid state drive (SSD) includes dynamic random access memory (DRAM), flash memory, and a solid state drive (SSD) controller. The solid state drive (SSD) also includes a peripheral component interconnect express (PCIe) bus to connect the SSD to a computing device such that a central processing unit (CPU) of the computing device exclusively reads data from, and writes data to, the DRAM. The SSD controller writes data to the flash memory from the DRAM independently of received commands from the computing device.

Abstract: A solid state drive includes DRAM logical flash and flash memory, in which system processor reads and writes only to the DRAM logical flash which minimizes writes to the flash memory. A method for operation of a solid state flash device includes writing, by a CPU, to a solid state drive by sending commands and data to DRAM logical flash using flash commands and formatting.

Abstract: A solid state drive includes DRAM logical flash and flash memory, in which system processor reads and writes only to the DRAM logical flash which minimizes writes to the flash memory. A method for operation of a solid state flash device includes writing, by a CPU, to a solid state drive by sending commands and data to DRAM logical flash using flash commands and formatting.

Abstract: A solid state drive (SSD) includes dynamic random access memory (DRAM), flash memory, and a solid state drive (SSD) controller. The solid state drive (SSD) also includes a peripheral component interconnect express (PCIe) bus to connect the SSD to a computing device such that a central processing unit (CPU) of the computing device exclusively reads data from, and writes data to, the DRAM. The SSD controller writes data to the flash memory from the DRAM independently of received commands from the computing device.

Abstract: A high speed USB memory controller includes a microprocessor, flash memory, memory buffers directly accessible to the microprocessor and flash memory, and a USB interface for writing data directly into the memory buffers. This allows devices with multiple flash die to operate at full bus speed.

Abstract: A solid state drive includes DRAM logical flash and flash memory, in which system processor reads and writes only to the DRAM logical flash which minimizes writes to the flash memory. A method for operation of a solid state flash device includes writing, by a CPU, to a solid state drive by sending commands and data to DRAM logical flash using flash commands and formatting.

Abstract: A solid state drive includes DRAM logical flash and flash memory, in which system processor reads and writes only to the DRAM logical flash which minimizes writes to the flash memory. A method for operation of a solid state flash device includes writing, by a CPU, to a solid state drive by sending commands and data to DRAM logical flash using flash commands and formatting.

Abstract: A high speed USB memory controller includes a microprocessor, flash memory, memory buffers directly accessible to the microprocessor and flash memory, and a USB interface for writing data directly into the memory buffers. This allows devices with multiple flash die to operate at full bus speed.

Abstract: A high speed USB memory controller includes a microprocessor, flash memory, memory buffers directly accessible to the microprocessor and flash memory, and a USB interface for writing data directly into the memory buffers. This allows devices with multiple flash die to operate at full bus speed.

Abstract: A high speed USB memory controller includes a microprocessor, flash memory, memory buffers directly accessible to the microprocessor and flash memory, and a USB interface for writing data directly into the memory buffers. This allows devices with multiple flash die to operate at full bus speed.

Abstract: A solid state drive includes DRAM logical flash and flash memory, in which system processor reads and writes only to the DRAM logical flash which minimizes writes to the flash memory. A method for operation of a solid state flash device includes writing, by a CPU, to a solid state drive by sending commands and data to DRAM logical flash using flash commands and formatting.

Abstract: A page-based failure management system for flash memory includes at least one flash memory device which includes at least one page and at least one operable page. The system also includes an indication of operability of the at least one page in the at least one flash device.

Abstract: A page-based failure management system for flash memory includes at least one flash memory device which includes at least one page and at least one operable page. The system also includes an indication of operability of the at least one page in the at least one flash device.

Abstract: An improved method for fabricating Chip-on-Board memory modules using partially-defective memory chips or a combination of partially-defective and flawless memory parts, comprises mounting unpackaged (or a combination of packaged and unpackaged) memory parts to a printed circuit board using one or more selectively settable materials, testing and patching the memory parts, and providing a protective cover after a suitable combination of memory parts and patches produces a fully-functional memory module. Also, a new set of printed circuit boards designed to allow fabrication of memory modules using single-bit patching, any-bit patching, and DDR technology with unpackaged memory parts. In a preferred embodiment, the method and printed circuit boards mentioned above are combined to produce a number of low-cost memory modules using modern, available partially-defective and flawless memory parts.

Abstract: A method and apparatus for building a memory module using improved patching schemes comprises, mounting multiple primary and secondary memory parts on a multi-layer circuit board, positioning I/O bit line patching networks adjacent to the primary and secondary memory parts, matching read/write control signals for primary and secondary memory parts which share I/O bit line patching networks, testing primary and secondary memory parts to identify non-operable I/O lines, and patching any non-operable I/O line of a primary memory part by replacing it with a fully operable I/O line of its associated backup memory part. The method and apparatus include multi-layer circuit boards which utilize 2-to-1, 4-to-1, and 8-to-1 patching configurations.

Abstract: A method and apparatus for implementing a selectively operable clock booster for DDR memory and other logic modules, which utilize partially-defective memory parts or a combination of partially-defective and flawless memory parts. The method and apparatus include an improved clocking method and system, which enables the use of partially-defective memory parts without distorting the clock signal. In one embodiment, a Phase-Locked Loop circuit and a clock patching network are used to significantly reduce clock distortion on a memory module.

Abstract: Methods and devices for using less-than-perfect memory chips and packages in the manufacture of memory modules. In the preferred method the failed I/O lines in primary memory packages are disconnected and replaced by selected I/O lines from flawless or partially defective backup parts all mounted on the same module. The various processes comprise sorting of partially defective parts according to the results of wafer or packages test, judicious distribution of backup parts on a PC board module and routing of their I/O lines, optimized patching techniques and multi-level tests and repatching routines. The methods and processes are equally applicable to Chip On Board assemblies as well as package assemblies.