Abstract: A method, an apparatus, and a computer program product in a data processing system are presented for using hardware assistance for gathering performance information that significantly reduces the overhead in gathering such information. Performance indicators are associated with instructions or memory locations, and processing of the performance indicators enables counting of events associated with execution of those instructions or events associated with accesses to those memory locations. The performance information that has been dynamically gathered from the assisting hardware is available to the software application during runtime in order to autonomically affect the behavior of the software application, particularly to enhance its performance. For example, the counted events may be used to autonomically collecting statistical information about the ability of a software application to successfully acquire a semaphore.

Abstract: A method, apparatus and computer instructions for hardware assist for autonomically patching code. The present invention provides hardware microcode to a new type of metadata to selectively identify instructions to be patched for specific performance optimization functions. The present invention also provides a new flag in the machine status register (MSR) to enable or disable a performance monitoring application or process to perform code-patching functions. If the code patching function is enabled, the application or process may patch code at run time by associating the metadata with the selected instructions. The metadata includes pointers pointing to the patch code block code. The program code may be patched autonomically without modifying original code.

Abstract: A method and apparatus in a data processing system for measuring events associated with the execution of instructions are provided. Instructions are received at a processor in the data processing system. If a selected indicator is associated with the instruction, counting of each event associated with the execution of the instruction is enabled. In some embodiments, the performance indicators, counters, thresholds, and other performance monitoring structures may be stored in a page table that is used to translate virtual addresses into physical storage addresses. A standard page table is augmented with additional fields for storing the performance monitoring structures. These structures may be set by the performance monitoring application and may be queried and modified as events occur that require access to physical storage.

Abstract: A method, apparatus, and computer instructions in a data processing system for processing instructions. Instructions are received at a processor in the data processing system. If a selected indicator is associated with the instruction, counting of each event associated with the execution of the instruction is enabled.

Abstract: A method, apparatus, and computer instructions in a data processing system for processing instructions are provided. Instructions are received at a processor in the data processing system. If a selected indicator is associated with the instruction, counting of each event associated with the execution of the instruction is enabled. Functionality may be provided in the performance monitoring application for initiating the measurement of secondary metrics with regard to identified instructions, data addresses, ranges of identified instructions, or ranges of identified data addresses, based on counter values for primary metrics. Thus, for example, when a primary metric counter, or a combination of primary metric counters, meets or exceeds a predetermined threshold value, an interrupt may be generated. In response to receiving the interrupt, counters associated with the measuring of secondary metrics of a range of instructions/data addresses may be initiated.

Abstract: A method, apparatus, and computer instructions in a data processing system for processing instructions. Instructions are received at a processor in the data processing system. If a selected indicator is associated with the instruction, counting of each event associated with the execution of the instruction is enabled.

Abstract: A method, apparatus, and computer instructions in a data processing system for processing instructions and monitoring accesses to memory location ranges. An instruction for execution is identified. A determination is made as to whether the instruction is within a contiguous range of instructions. Execution information relating to the instruction is identified if the instruction is within the contiguous range of instructions. With memory location accesses, an access to a memory location is identified. A determination of whether the memory location is within a contiguous range of memory locations is made. Access information is identified if the memory location is within the contiguous range of memory locations.

Abstract: A method, apparatus, and computer instructions for autonomically counting selected branch instructions executed in a processor to improve branch predictions. Counters are provided to count branch instructions that are executed in a processor to collect branch statistics. A set of branch statistics fields is allocated to associate with a branch instruction. When a program is executed, the stored statistics allows the program to look at the branch statistics in the counter to perform branch prediction. Hence, a user may use branch statistics values from the hardware counter to perform analysis on application code.

Abstract: A method, apparatus, and computer instructions for local program reorganization using branch count per instruction hardware. In a preferred embodiment, a hardware counter is used in the present invention to count the number of times a branch is taken when branch instructions are executed. Branch count statistics generated from the hardware counters are available to a program in order to analyze whether code reorganization is necessary. If reorganization is necessary, the program autonomically reorganizes instructions locally at run time to allow more instructions to be executed prior to taking a branch, so that the number of branches taken is minimized without modifying underlying program code.

Abstract: A method, apparatus, and computer instructions for processing instructions. Responsive to receiving an instruction for execution in an instruction cache in a processor in the data processing system, a determination is made as to whether an indicator is associated with the instruction and whether the instruction is of a certain type within a range of instructions. An interrupt is generated if the indicator is associated with the instruction and the instruction is of the certain type within the range of instructions.

Abstract: A method, an apparatus, and a computer program product in a data processing system are presented for using hardware assistance for gathering performance information that significantly reduces the overhead in gathering such information. Performance indicators are associated with instructions or memory locations, and processing of the performance indicators enables counting of events associated with execution of those instructions or events associated with accesses to those memory locations. The performance information that has been dynamically gathered from the assisting hardware is available to the software application during runtime in order to autonomically affect the behavior of the software application, particularly to enhance its performance. For example, the counted events may be used to autonomically improve the performance of the execution of an application by relocating code segments and data areas.

Abstract: A method, apparatus, and computer instructions for providing pre and post handlers to log trace records before entering or after exiting the interrupt handler. A trace record includes a ‘from’ address where the interrupt occurs or where the branch instruction is executed or a ‘to’ address for the branch to case and counts of selected performance monitoring events. A timestamp may be associated with each event. In one embodiment, the pre and post handler is used with trap on branch to log trace records prior to and immediate after taking a branch. In another embodiment, a pre handler is enabled to log trace records that occur prior to executing interrupt service routines. A post handler is enabled to log trace records that occur after the interrupt service routines is executed and prior to returning to normal execution. Resulting low-level performance trace data may be collected by the user at a later time for more structured performance analysis.

Abstract: A method, apparatus, and computer instructions in a data processing system for processing instructions are provided. Instructions are received at a processor in the system. If a selected indicator is associated with the instruction, counting of each event associated with the execution of the instruction is enabled. The performance indicators and counter values may be used as a mechanism for identifying cache hits and cache misses. Performance counters are incremented each time the instructions of routines of interest are executed and each time the instructions must be reloaded into the cache. From the values of these counters the cache hit-miss ratio may be determined. When the cache hit-miss ratio becomes less than a predetermined threshold, i.e. a greater number of cache misses than cache hits, the present invention may determine that a problem condition has occurred and initiate “chase tail” operations for avoiding overwriting of entries in the cache.

Abstract: A method, apparatus, and computer instructions in a data processing system for processing instructions are provided. Instructions are received at a processor in the data processing system. If a selected indicator is associated with the instruction, counting of each event associated with the execution of the instruction is enabled. In some embodiments, when it is determined that a cache line is being falsely shared using the performance indicators and counters, an interrupt may be generated and sent to a performance monitoring application. An interrupt handler of the performance monitoring application will recognize this interrupt as indicating false sharing of a cache line. Rather than reloading the cache line in a normal fashion, the data or instructions being accessed may be written to a separate area of cache or memory area dedicated to false cache line sharing data. The code may then be modified by inserting a pointer to this new area of cache or memory.

Abstract: A method, apparatus, and computer instructions in a data processing system for processing instructions are provided. Instructions are received at a processor in the data processing system. If a selected indicator is associated with the instruction, counting of each event associated with the execution of the instruction is enabled. In some embodiments, the performance indicators may be utilized to obtain information regarding the nature of the cache hits and reloads of cache lines within the instruction or data cache. These embodiments may be used to determine whether processors of a multiprocessor system, such as a symmetric multiprocessor (SMP) system, are truly sharing a cache line or if there is false sharing of a cache line. This determination may then be used as a means for determining how to better store the instructions/data of the cache line to prevent false sharing of the cache line.

Abstract: A method, apparatus, and computer instructions for counting interrupts by type. An interrupt count is incremented when a particular type of interrupt occurs. The count may be stored in the IDT or an interrupt count table outside the IDT. The interrupt unit increments the count each time a particular type of interrupt occurs. In the event of a potential count overflow, the mechanism of the present invention provides logic necessary to notify software in order to handle the overflow.

Abstract: An apparatus and method for cataloging symbolic data for use in performance analysis of computer programs is provided. The apparatus and method stores symbolic data for loaded modules during or shortly after a performance trace and utilizes the stored symbolic data when performing a performance analysis at a later time. A merged symbol file is generated for a computer program, or application, under trace. The merged symbol file contains information useful in performing symbolic resolution of address information in trace files for each instance of a module. During post processing of the trace information generated by a performance trace of a computer program, symbolic information stored in the merged symbol file is compared to the trace information stored in the trace file. The correct symbolic information in the merged symbol file for loaded modules is identified based a number of validating criteria.

Abstract: An apparatus and method for cataloging symbolic data for use in performance analysis of computer programs is provided. The apparatus and method stores symbolic data for loaded modules during or shortly after a performance trace and utilizes the stored symbolic data when performing a performance analysis at a later time. A merged symbol file is generated for a computer program, or application, under trace. The merged symbol file contains information useful in performing symbolic resolution of address information in trace files for each instance of a module. During post processing of the trace information generated by a performance trace of a computer program, symbolic information stored in the merged symbol file is compared to the trace information stored in the trace file. The correct symbolic information in the merged symbol file for loaded modules is identified based a number of validating criteria.

Abstract: An apparatus and method for cataloging symbolic data for use in performance analysis of computer programs is provided. The apparatus and method stores symbolic data for loaded modules during or shortly after a performance trace and utilizes the stored symbolic data when performing a performance analysis at a later time. A merged symbol file is generated for a computer program, or application, under trace. The merged symbol file contains information useful in performing symbolic resolution of address information in trace files for each instance of a module. During post processing of the trace information generated by a performance trace of a computer program, symbolic information stored in the merged symbol file is compared to the trace information stored in the trace file. The correct symbolic information in the merged symbol file for loaded modules is identified based a number of validating criteria.

Abstract: An apparatus and method for cataloging symbolic data for use in performance analysis of computer programs is provided. The apparatus and method stores symbolic data for loaded modules during or shortly after a performance trace and utilizes the stored symbolic data when performing a performance analysis at a later time. A merged symbol file is generated for a computer program, or application, under trace. The merged symbol file contains information useful in performing symbolic resolution of address information in trace files for each instance of a module. During post processing of the trace information generated by a performance trace of a computer program, symbolic information stored in the merged symbol file is compared to the trace information stored in the trace file. The correct symbolic information in the merged symbol file for loaded modules is identified based on a number of validating criteria.