Abstract: A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data.

Abstract: The present invention provides for a method of and apparatus for compressing and uncompressing image data. According to one embodiment of the present invention, the method of compressing a color cell comprises the steps of: defining at least four luminance levels of the color cell; generating a bitmask for the color cell, the bitmask having a plurality of entries each corresponding to a respective one of the pixels, each of the entries for storing data identifying one of the luminance levels associated with a corresponding one of the pixels; calculating a first average color of pixels associated with a first one of the luminance levels; calculating a second average color of pixels associated with a second one of the luminance levels; and storing the bitmask in association with the first average color and the second average color.

Abstract: A scaleable network based computer system having a distributed texture memory architecture. A network residing within the computer system is used to transmit packets between a host processor and a number of subsystems. Three basic types of subsystems are coupled to the network: a geometry subsystem is used to process primitives; a rasterization subsystem is used to render pixels; and a display subsystem is used to drive a computer monitor. Any number and combination of these three types of subsystems can be coupled to one or more network chips to implement a wide variety of configurations. One or more memory chips can be coupled to any of the rasterization subsystems. These memory chips are used to store texture data. A rasterization subsystem can access texture data from its associated memory chips or can request texture data residing within any of the other memory chips.

Abstract: A cache memory for high latency and out-of-order return of texture data. The present invention includes a texture cache memory that prefetches texture data before it is needed. Further, the texture cache memory counts the number of times a cache line is requested and a number of times the cache line is read, and determines whether the cache line is free by keeping track of the different between the two numbers. The texture cache memory of the present invention is capable of working efficiently in computer systems where there is a long latency from the time the texture data is requested and the time the texture data is available for use. In addition, the present invention is capable of handling texture data which enters into the texture cache memory in a different order from which it was requested. The present invention significantly improves performance of the texture data retrieval subsystem within network based or memory hierarchy based computer systems.