Patents by Inventor Kevin W. Glass

Kevin W. Glass has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7233776
    Abstract: According to one embodiment a microelectromechanical (MEMS) switch is disclosed. The MEMS switch includes a pulse generator to provide a low voltage source, a transformer coupled to the pulse generator to boost a voltage received from the pulse generator and a switch component coupled to the pulse generator. The switch component includes an actuation capacitor to store charge associated with the voltage received from the transformer.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: June 19, 2007
    Assignee: Intel Corporation
    Inventors: Kevin W. Glass, Bart R. McDaniel
  • Patent number: 7132894
    Abstract: In one embodiment, the present invention includes a differential traveling wave amplifier having a lumped differential preamplifier stage and a distributed differential amplifier stage coupled by a differential end termination interface. In certain embodiments, the distributed differential amplifier stage may include transverse electromagnetic transmission lines coupled between its input and output.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: November 7, 2006
    Assignee: Intel Corporation
    Inventors: Eric S. Shapiro, Jose Robins, Kevin W. Glass, Kursad Kiziloglu
  • Patent number: 7091788
    Abstract: An amplifier includes a Darlington transistor pair and a biasing network to increase bias currents in an input transistor.
    Type: Grant
    Filed: December 3, 2003
    Date of Patent: August 15, 2006
    Assignee: Intel Corporation
    Inventors: Kevin W. Glass, Malcolm H. Smith
  • Patent number: 7088174
    Abstract: A method and apparatus to provide slice adjustment and offset cancellation in a high frequency limiting amplifier is described.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: August 8, 2006
    Assignee: Intel Corporation
    Inventor: Kevin W. Glass
  • Patent number: 7064585
    Abstract: In one embodiment, the present invention includes an apparatus having a threshold detector with a current comparator to determine if an input signal exceeds a threshold. The input signal may be obtained from a received optical signal and may be compared to a reference signal obtained from a hierarchical Schmitt trigger, in certain embodiments.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: June 20, 2006
    Assignee: Intel Corporation
    Inventor: Kevin W. Glass
  • Patent number: 6822491
    Abstract: A frequency prescaler includes an asynchronous counter having a least significant stage clocked by an input signal, and a first true single phase clock flip-flop having an input stage with an embedded logic gate to decode a state of the asynchronous counter, configured to modify a modulus of the asynchronous counter.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: November 23, 2004
    Assignee: Intel Corporation
    Inventor: Kevin W. Glass
  • Patent number: 6121913
    Abstract: A method and apparatus for performing analog to digital conversion. A voltage to current converter converts an analog input voltage to an input current. A current reference generates a reference current. A plurality of scaling elements scaled the reference current to yield a plurality of scaled reference currents each corresponding to some voltage level within the dynamic range of the input voltage. The input current is compared to each of the scaled reference currents in a plurality of current comparators to generate a thermometer code from which a digital representation of the analog input voltage is derived.
    Type: Grant
    Filed: March 4, 1999
    Date of Patent: September 19, 2000
    Assignee: Intel Corporation
    Inventors: Kevin W. Glass, Waleed Khalil, Bart R. McDaniel
  • Patent number: 6037890
    Abstract: A method and apparatus for performing analog to digital conversion. A voltage to current converter converts an analog input voltage to an input current. A current reference generates a reference current. A plurality of scaling elements scaled the reference current to yield a plurality of scaled reference currents each corresponding to some voltage level within the dynamic range of the input voltage. The input current is compared to each of the scaled reference currents in a plurality of current comparators to generate a thermometer code from which a digital representation of the analog input voltage is derived.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: March 14, 2000
    Assignee: Intel Corporation
    Inventors: Kevin W. Glass, Waleed Khalil, Bart R. McDaniel
  • Patent number: 6008673
    Abstract: A current regenerative comparator. A pair of cross coupled inverters are coupled to an equalizing transistor, an input current mirror and a reference current mirror, such that current flowing in the input current mirror is compared to the current flowing in the reference current mirror.
    Type: Grant
    Filed: March 4, 1999
    Date of Patent: December 28, 1999
    Assignee: Intel Corporation
    Inventors: Kevin W. Glass, Waleed Khalil, Bart R. McDaniel
  • Patent number: 5834953
    Abstract: A high speed current sense amplifier useful in memory devices, which includes a current-to-voltage amplifier that is coupled to a voltage amplifier. The current-to-voltage amplifier has an input impedance that is lower than its output impedance. The voltage amplifier has an input impedance that is larger than the input impedance of the current-to-voltage amplifier. The current sense amplifier can sense the current relationship between two current inputs in about 200 pico-seconds. Embodiments of the current sense amplifier enable current sensing either near the power supply voltage or near ground, thus eliminating the need for intermediate voltages. Embodiments of the current sense amplifier draw current from the current inputs only during the 200 pico-second sensing time and does not require external latching circuitry.
    Type: Grant
    Filed: November 25, 1996
    Date of Patent: November 10, 1998
    Assignee: Rockwell International Corporation
    Inventors: Kevin W. Glass, John R. Spence, Lester J. Pastuszyn, William W. Decker
  • Patent number: 5821785
    Abstract: The invention relates to a clock signal frequency multiplier circuit. The circuit multiplies the speed of a clock signal of an integrated circuit (IC) by a factor N to generate a times-N clock signal. The circuit first receives a clock signal. Next, the circuit replicates the clock signal into a plurality of N component signals. Each Jth component signal is delayed from the (J-1)th component signal by 1/N cycles, where J equals 1 to N. The (J=1)th component signal is the clock signal. The N component signals are referred to as phase-shifted components. Finally, the circuit logically combines the phase-shifted components into a times-N clock signal.
    Type: Grant
    Filed: August 2, 1996
    Date of Patent: October 13, 1998
    Assignee: Rockwell Int'l Corp.
    Inventors: Kevin W. Glass, Mehrdad Heshami
  • Patent number: 5363499
    Abstract: A content addressable memory has a plurality of entry locations. Each entry location includes a comparison field and an action field. Comparitors are provided for each entry location, so that an input provided to the memory is compared simultaneously to the comparison fields of every entry. The action fields of all entries which match the input value are combined to generate a single output value. Each entry includes a bit which indicates whether such entry is to be deleted when a match occurs with an input value. Each entry in the memory can be assigned an arbitrary label for use in direct accessing by a central processor unit.
    Type: Grant
    Filed: December 15, 1993
    Date of Patent: November 8, 1994
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventor: Kevin W. Glass
  • Patent number: 5260680
    Abstract: A comparator circuit is provided that determines whether a given value is within a selected compare range. The comparator circuit electronically implements a Ling Adder algorithm to perform comparisons. The circuit operates at a high speed and requires fewer components compared to circuitry implementing a conventional carry look ahead algorithm. The circuit may be implemented in CMOS technology.
    Type: Grant
    Filed: February 13, 1992
    Date of Patent: November 9, 1993
    Assignee: MOS Electronics Corp.
    Inventor: Kevin W. Glass
  • Patent number: 5199002
    Abstract: For enabling a static, random-access-memory (500) bit lines (556 and 558) pre-charging circuit (518), employed is an address-change-detection circuit (510) having a plurality of address-change-detectors (570 and 572) each for detecting a change in an associated SRAM addressing signal and, driven by the address-change detectors (570 and 572), a pulse generator (700) driving the pre-charging circuit (518).
    Type: Grant
    Filed: October 1, 1990
    Date of Patent: March 30, 1993
    Assignee: Integrated Device Technology, Inc.
    Inventors: Michael A. G. Ang, Kevin W. Glass, David J. Pilling
  • Patent number: 5192916
    Abstract: A charge-pump phase locked loop circuit is disclosed that is capable of operating with a high bandwidth while having a low associated noise jitter characteristic. In addition, the phase locked loop circuit has a high dynamic range and prevents against false locking to sub-harmonic frequencies. Furthermore, common mode noise rejection and other internal noise rejection characteristics are optimized.
    Type: Grant
    Filed: September 20, 1991
    Date of Patent: March 9, 1993
    Assignee: MOS Electronics Corporation
    Inventor: Kevin W. Glass
  • Patent number: 5148056
    Abstract: An output buffer circuit is disclosed that has optimized ground bounce characteristics while maintaining low propagation delay. The output buffer may be incorporated within an integrated circuit and may be embodied in either inverting or non-inverting and in either enabling and non-enabling configurations. The output buffer circuit includes a feedback means coupled to the output terminal of the output buffer and to a pull-down transistor. The feedback means provides a feedback voltage to the gate of the pull-down transistor to regulate the derivative of source current with respect to time. The feedback means includes a pair of field effect transistors and either an inverter gate or a NOR gate coupled across one of the feedback field effect transistors.
    Type: Grant
    Filed: March 27, 1991
    Date of Patent: September 15, 1992
    Assignee: MOS Electronics Corp.
    Inventors: Kevin W. Glass, Ashok Nagarajan