Patents by Inventor Pohsiang Hsu

Pohsiang Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11638017
    Abstract: A video codec uses fractional increments of quantization step size at high bit rates to permit a more continuous variation of quality and/or bit rate as the quantization scale changes. For high bit rate scenarios, the bit stream syntax includes an additional syntax element to specify fractional step increments (e.g., half step) of the normal quantizer scale step sizes.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: April 25, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Thomas W. Holcomb, Sridhar Srinivasan, Pohsiang Hsu, Chih-Lung Lin
  • Patent number: 11570451
    Abstract: With adaptive multiple quantization, a video or other digital media codec can adaptively select among multiple quantizers to apply to transform coefficients. The switch in quantizers can be signaled at the sequence level or frame level of the bitstream syntax, or can be implicitly specified in the syntax.
    Type: Grant
    Filed: December 15, 2021
    Date of Patent: January 31, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Thomas W. Holcomb, Chih-Lung Lin, Pohsiang Hsu, Sridhar Srinivasan
  • Publication number: 20220191518
    Abstract: A video codec uses fractional increments of quantization step size at high bit rates to permit a more continuous variation of quality and/or bit rate as the quantization scale changes. For high bit rate scenarios, the bit stream syntax includes an additional syntax element to specify fractional step increments (e.g., half step) of the normal quantizer scale step sizes.
    Type: Application
    Filed: March 7, 2022
    Publication date: June 16, 2022
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Thomas W. Holcomb, Sridhar Srinivasan, Pohsiang Hsu, Chih-Lung Lin
  • Publication number: 20220182647
    Abstract: With adaptive multiple quantization, a video or other digital media codec can adaptively select among multiple quantizers to apply to transform coefficients. The switch in quantizers can be signaled at the sequence level or frame level of the bitstream syntax, or can be implicitly specified in the syntax.
    Type: Application
    Filed: December 15, 2021
    Publication date: June 9, 2022
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Thomas W. Holcomb, Chih-Lung Lin, Pohsiang Hsu, Sridhar Srinivasan
  • Patent number: 11272194
    Abstract: A video codec uses fractional increments of quantization step size at high bit rates to permit a more continuous variation of quality and/or bit rate as the quantization scale changes. For high bit rate scenarios, the bit stream syntax includes an additional syntax element to specify fractional step increments (e.g., half step) of the normal quantizer scale step sizes.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: March 8, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Thomas W. Holcomb, Sridhar Srinivasan, Pohsiang Hsu, Chih-Lung Lin
  • Patent number: 11245910
    Abstract: With adaptive multiple quantization, a video or other digital media codec can adaptively select among multiple quantizers to apply to transform coefficients. The switch in quantizers can be signaled at the sequence level or frame level of the bitstream syntax, or can be implicitly specified in the syntax.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: February 8, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Thomas W. Holcomb, Chih-Lung Lin, Pohsiang Hsu, Sridhar Srinivasan
  • Publication number: 20210168382
    Abstract: A video codec uses fractional increments of quantization step size at high bit rates to permit a more continuous variation of quality and/or bit rate as the quantization scale changes. For high bit rate scenarios, the bit stream syntax includes an additional syntax element to specify fractional step increments (e.g., half step) of the normal quantizer scale step sizes.
    Type: Application
    Filed: February 17, 2021
    Publication date: June 3, 2021
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Thomas W. HOLCOMB, Sridhar SRINIVASAN, Pohsiang HSU, Chih-Lung LIN
  • Publication number: 20210092411
    Abstract: With adaptive multiple quantization, a video or other digital media codec can adaptively select among multiple quantizers to apply to transform coefficients. The switch in quantizers can be signaled at the sequence level or frame level of the bitstream syntax, or can be implicitly specified in the syntax.
    Type: Application
    Filed: December 4, 2020
    Publication date: March 25, 2021
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Thomas W. Holcomb, Chih-Lung Lin, Pohsiang Hsu, Sridhar Srinivasan
  • Patent number: 10958916
    Abstract: A video codec uses fractional increments of quantization step size at high bit rates to permit a more continuous variation of quality and/or bit rate as the quantization scale changes. For high bit rate scenarios, the bit stream syntax includes an additional syntax element to specify fractional step increments (e.g., half step) of the normal quantizer scale step sizes.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: March 23, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Thomas W. Holcomb, Sridhar Srinivasan, Pohsiang Hsu, Chih-Lung Lin
  • Patent number: 10931967
    Abstract: Techniques and tools for video coding/decoding with motion resolution switching and sub-block transform coding/decoding are described. For example, a video encoder adaptively switches the resolution of motion estimation and compensation between quarter-pixel and half-pixel resolutions; a corresponding video decoder adaptively switches the resolution of motion compensation between quarter-pixel and half-pixel resolutions. For sub-block transform sizes, for example, a video encoder adaptively switches between 8×8, 8×4, and 4×8 DCTs when encoding 8×8 prediction residual blocks; a corresponding video decoder switches between 8×8, 8×4, and 4×8 inverse DCTs during decoding.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: February 23, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Pohsiang Hsu, Chih-Lung Lin, Ming-Chieh Lee, Thomas W. Holcomb, Sridhar Srinivasan
  • Patent number: 10924749
    Abstract: With adaptive multiple quantization, a video or other digital media codec can adaptively select among multiple quantizers to apply to transform coefficients. The switch in quantizers can be signaled at the sequence level or frame level of the bitstream syntax, or can be implicitly specified in the syntax.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: February 16, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Thomas W. Holcomb, Chih-Lung Lin, Pohsiang Hsu, Sridhar Srinivasan
  • Publication number: 20200177891
    Abstract: With adaptive multiple quantization, a video or other digital media codec can adaptively select among multiple quantizers to apply to transform coefficients. The switch in quantizers can be signaled at the sequence level or frame level of the bitstream syntax, or can be implicitly specified in the syntax.
    Type: Application
    Filed: February 3, 2020
    Publication date: June 4, 2020
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Thomas W. Holcomb, Chih-Lung Lin, Pohsiang Hsu, Sridhar Srinivasan
  • Publication number: 20200177892
    Abstract: A video codec uses fractional increments of quantization step size at high bit rates to permit a more continuous variation of quality and/or bit rate as the quantization scale changes. For high bit rate scenarios, the bit stream syntax includes an additional syntax element to specify fractional step increments (e.g., half step) of the normal quantizer scale step sizes.
    Type: Application
    Filed: February 3, 2020
    Publication date: June 4, 2020
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Thomas W. Holcomb, Sridhar Srinivasan, Pohsiang Hsu, Chih-Lung Lin
  • Publication number: 20200169749
    Abstract: Techniques and tools for video coding/decoding with motion resolution switching and sub-block transform coding/decoding are described. For example, a video encoder adaptively switches the resolution of motion estimation and compensation between quarter-pixel and half-pixel resolutions; a corresponding video decoder adaptively switches the resolution of motion compensation between quarter-pixel and half-pixel resolutions. For sub-block transform sizes, for example, a video encoder adaptively switches between 8×8, 8×4, and 4×8 DCTs when encoding 8×8 prediction residual blocks; a corresponding video decoder switches between 8×8, 8×4, and 4×8 inverse DCTs during decoding.
    Type: Application
    Filed: January 28, 2020
    Publication date: May 28, 2020
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Pohsiang Hsu, Chih-Lung Lin, Ming-Chieh Lee, Thomas W. Holcomb, Sridhar Srinivasan
  • Patent number: 10567791
    Abstract: Techniques and tools for video coding/decoding with motion resolution switching and sub-block transform coding/decoding are described. For example, a video encoder adaptively switches the resolution of motion estimation and compensation between quarter-pixel and half-pixel resolutions; a corresponding video decoder adaptively switches the resolution of motion compensation between quarter-pixel and half-pixel resolutions. For sub-block transform sizes, for example, a video encoder adaptively switches between 8×8, 8×4, and 4×8 DCTs when encoding 8×8 prediction residual blocks; a corresponding video decoder switches between 8×8, 8×4, and 4×8 inverse DCTs during decoding.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: February 18, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Pohsiang Hsu, Chih-Lung Lin, Ming-Chieh Lee, Thomas W. Holcomb, Sridhar Srinivasan
  • Patent number: 10567753
    Abstract: Various techniques and tools for encoding and decoding (e.g., in a video encoder/decoder) binary information (e.g., skipped macroblock information) are described. In some embodiments, the binary information is arranged in a bit plane, and the bit plane is coded at the picture/frame layer. The encoder and decoder process the binary information and, in some embodiments, switch coding modes. For example, the encoder and decoder use normal, row-skip, column-skip, or differential modes, or other and/or additional modes. In some embodiments, the encoder and decoder define a skipped macroblock as a predicted macroblock whose motion is equal to its causally predicted motion and which has zero residual error. In some embodiments, the encoder and decoder use a raw coding mode to allow for low-latency applications.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: February 18, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Sridhar Srinivasan, Pohsiang Hsu
  • Publication number: 20190327487
    Abstract: Techniques and tools for video coding/decoding with motion resolution switching and sub-block transform coding/decoding are described. For example, a video encoder adaptively switches the resolution of motion estimation and compensation between quarter-pixel and half-pixel resolutions; a corresponding video decoder adaptively switches the resolution of motion compensation between quarter-pixel and half-pixel resolutions. For sub-block transform sizes, for example, a video encoder adaptively switches between 8×8, 8×4, and 4×8 DCTs when encoding 8×8 prediction residual blocks; a corresponding video decoder switches between 8×8, 8×4, and 4×8 inverse DCTs during decoding.
    Type: Application
    Filed: July 3, 2019
    Publication date: October 24, 2019
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Pohsiang Hsu, Chih-Lung Lin, Ming-Chieh Lee, Thomas W. Holcomb, Sridhar Srinivasan
  • Publication number: 20190327464
    Abstract: Various techniques and tools for encoding and decoding (e.g., in a video encoder/decoder) binary information (e.g., skipped macroblock information) are described. In some embodiments, the binary information is arranged in a bit plane, and the bit plane is coded at the picture/frame layer. The encoder and decoder process the binary information and, in some embodiments, switch coding modes. For example, the encoder and decoder use normal, row-skip, column-skip, or differential modes, or other and/or additional modes. In some embodiments, the encoder and decoder define a skipped macroblock as a predicted macroblock whose motion is equal to its causally predicted motion and which has zero residual error. In some embodiments, the encoder and decoder use a raw coding mode to allow for low-latency applications.
    Type: Application
    Filed: July 2, 2019
    Publication date: October 24, 2019
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Sridhar Srinivasan, Pohsiang Hsu
  • Patent number: 10390037
    Abstract: Techniques and tools for video coding/decoding with motion resolution switching and sub-block transform coding/decoding are described. For example, a video encoder adaptively switches the resolution of motion estimation and compensation between quarter-pixel and half-pixel resolutions; a corresponding video decoder adaptively switches the resolution of motion compensation between quarter-pixel and half-pixel resolutions. For sub-block transform sizes, for example, a video encoder adaptively switches between 8×8, 8×4, and 4×8 DCTs when encoding 8×8 prediction residual blocks; a corresponding video decoder switches between 8×8, 8×4, and 4×8 inverse DCTs during decoding.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: August 20, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Pohsiang Hsu, Chih-Lung Lin, Ming-Chieh Lee, Thomas W. Holcomb, Sridhar Srinivasan
  • Patent number: 10368065
    Abstract: Various techniques and tools for encoding and decoding (e.g., in a video encoder/decoder) binary information (e.g., skipped macroblock information) are described. In some embodiments, the binary information is arranged in a bit plane, and the bit plane is coded at the picture/frame layer. The encoder and decoder process the binary information and, in some embodiments, switch coding modes. For example, the encoder and decoder use normal, row-skip, column-skip, or differential modes, or other and/or additional modes. In some embodiments, the encoder and decoder define a skipped macroblock as a predicted macroblock whose motion is equal to its causally predicted motion and which has zero residual error. In some embodiments, the encoder and decoder use a raw coding mode to allow for low-latency applications.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: July 30, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Sridhar Srinivasan, Pohsiang Hsu