Patents by Inventor Robert L. Bruce
Robert L. Bruce has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11968913Abstract: A method for fabricating a semiconductor device includes forming air gaps within respective dielectric layer portions to reduce thermal cross-talk between adjacent bits. Each of the dielectric portions is formed on a substrate each adjacent to sidewall liners formed on sidewalls of a phase change memory (PCM) layer. The method further includes forming a pillar including the sidewall liners and the PCM layer, and forming a selector layer on the pillar and the dielectric portions.Type: GrantFiled: July 28, 2022Date of Patent: April 23, 2024Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wanki Kim, Fabio Carta, Chung H. Lam, Robert L. Bruce
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Publication number: 20240099163Abstract: Techniques for sidewall passivation and removal of redeposited materials and processing damage from phase change memory materials are provided. In one aspect, a phase change memory device includes: one or more phase change memory cells, where each of the phase change memory cells includes a phase change material between a bottom electrode and a top electrode; and a carbon and oxygen-containing passivation layer on sidewalls of the phase change material. An ovonic threshold switch can also be present between the bottom and top electrodes, in series with the phase change material, and the carbon and oxygen-containing passivation layer can also be present on sidewalls of the ovonic threshold switch. A method of fabricating the present phase change memory devices is also provided.Type: ApplicationFiled: September 20, 2022Publication date: March 21, 2024Inventors: Luxherta Buzi, Robert L. Bruce, John M. Papalia, Lynne Marie Gignac
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Publication number: 20240099166Abstract: Techniques for improving switching properties of phase change memory devices by boron surface passivation of the phase change memory material are provided. In one aspect, a phase change memory device includes: one or more phase change memory cells, each having a phase change material between a bottom electrode and a top electrode; and a boron-containing and nitrogen-containing bilayer on sidewalls of the phase change material to protect the phase change material from exposure to oxygen. An ovonic threshold switch can be implemented between the bottom electrode and the top electrode, in series with the phase change material. A method of fabricating the present phase change memory devices is also provided.Type: ApplicationFiled: September 20, 2022Publication date: March 21, 2024Inventors: Luxherta Buzi, ROBERT L. BRUCE, Charlie Tabachnick, Marinus Johannes Petrus Hopstaken
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Patent number: 11910731Abstract: A phase change memory cell for a semiconductor device that includes a heater element on a first conductive layer with a spacer surrounding sides of the heater element. The phase change memory cell includes a first dielectric layer on the conductive layer and on a bottom portion of the spacer surrounding the heater element and a second dielectric layer on the first dielectric layer surrounding a top portion of the heater element. The phase change memory cell includes a phase change material on a top surface of the heater element and on the second dielectric material.Type: GrantFiled: February 10, 2021Date of Patent: February 20, 2024Assignee: International Business Machines CorporationInventors: Jin Ping Han, Philip Joseph Oldiges, Robert L. Bruce, Ching-Tzu Chen
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Patent number: 11910734Abstract: A structure including a bottom electrode, a phase change material layer vertically aligned and an ovonic threshold switching layer vertically aligned above the phase change material layer. A structure including a bottom electrode, a phase change material layer and an ovonic threshold switching layer vertically aligned above the phase change material layer, and a first barrier layer physically separating the ovonic threshold switching layer from a top electrode. A method including forming a structure including a liner vertically aligned above a first barrier layer, the first barrier layer vertically aligned above a phase change material layer, the phase change material layer vertically aligned above a bottom electrode, forming a dielectric surrounding the structure, and forming an ovonic threshold switching layer on the first barrier layer, vertical side surfaces of the first buffer layer are vertically aligned with the first buffer layer, the phase change material layer and the bottom electrode.Type: GrantFiled: May 4, 2023Date of Patent: February 20, 2024Assignee: International Business Machines CorporationInventors: Nanbo Gong, Takashi Ando, Robert L. Bruce, Alexander Reznicek, Bahman Hekmatshoartabari
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Patent number: 11889771Abstract: A method for mitigating moisture driven degradation of silicon doped chalcogenides includes placing a silicon doped chalcogenide composition in a process chamber, passivating dangling silicon bonds of the silicon doped chalcogenide composition by flooding the process chamber with forming gas or with hydrogen plasma, purging the forming gas or the hydrogen plasma from the process chamber, and removing the passivated silicon doped chalcogenide composition from the process chamber.Type: GrantFiled: December 29, 2020Date of Patent: January 30, 2024Assignees: International Business Machines Corporation, Macronix International Co., Ltd.Inventors: Cheng-Wei Cheng, Huai-Yu Cheng, I-Ting Kuo, Robert L. Bruce, Martin Michael Frank, Hiroyuki Miyazoe
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Publication number: 20230371405Abstract: A structure comprising a top electrode and a bottom electrode. The structure further comprises a multilayer stack disposed between the top electrode and the bottom electrode, where the multilayer stack comprises alternating confinement layers and phase-change material layers, and where at least two of the phase-change material layers have different doping concentrations of at least one dopant.Type: ApplicationFiled: May 13, 2022Publication date: November 16, 2023Inventors: Kevin W. Brew, JIN PING HAN, Timothy Mathew Philip, Cheng-Wei Cheng, ROBERT L. BRUCE, Matthew Joseph BrightSky
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Publication number: 20230309422Abstract: A structure including a bottom electrode, a phase change material layer vertically aligned and an ovonic threshold switching layer vertically aligned above the phase change material layer. A structure including a bottom electrode, a phase change material layer and an ovonic threshold switching layer vertically aligned above the phase change material layer, and a first barrier layer physically separating the ovonic threshold switching layer from a top electrode. A method including forming a structure including a liner vertically aligned above a first barrier layer, the first barrier layer vertically aligned above a phase change material layer, the phase change material layer vertically aligned above a bottom electrode, forming a dielectric surrounding the structure, and forming an ovonic threshold switching layer on the first barrier layer, vertical side surfaces of the first buffer layer are vertically aligned with the first buffer layer, the phase change material layer and the bottom electrode.Type: ApplicationFiled: May 4, 2023Publication date: September 28, 2023Inventors: Nanbo Gong, Takashi Ando, Robert L. Bruce, Alexander Reznicek, Bahman Hekmatshoartabari
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Patent number: 11723293Abstract: Aspects of the present invention provide a semiconductor structure for a phase change memory device that includes a heater element on a bottom electrode that is surrounded by a dielectric material. The phase change memory device includes a metal nitride liner over the heater element, where the metal liner is oxide-free with a desired electrical resistance. The phase change memory device includes a phase change material is over the heater element and the dielectric material and a top electrode is over the phase change material.Type: GrantFiled: March 26, 2021Date of Patent: August 8, 2023Assignee: International Business Machines CorporationInventors: Robert L. Bruce, Cheng-Wei Cheng, Matthew Joseph BrightSky
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Publication number: 20230189670Abstract: A memory cell with a recessed bottom electrode and methods of forming the memory cell are described. A bottom electrode can be deposited on a layer of a structure. A first insulator and a second insulator can be deposited on top of the bottom electrode. The first insulator and the second insulator can be spaced apart from one another to form an opening on top of the bottom electrode. A recess can be etched in the bottom electrode. The recess can be etched in a portion of the bottom electrode that is underneath the opening. The recess and the opening can form a pore. Phase change material can be deposited in the pore to form a memory cell.Type: ApplicationFiled: December 9, 2021Publication date: June 15, 2023Inventors: Fabio Carta, Chung Hon Lam, Wanki Kim, Robert L. Bruce
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Publication number: 20230180636Abstract: A bottom electrode is deposited on a substrate. A dielectric layer is deposited on the bottom electrode. One or more structures are patterned within the dielectric layer. A liner layer is deposited on top of the dielectric layer and the bottom electrode. A selectivity promotion layer is deposited on top of the liner layer. The selectivity promotion layer is etched to expose a top surface of the dielectric layer and a portion of the bottom electrode. A phase change memory material layer is deposited within a void of the one or more structures between the selectivity promotion layer.Type: ApplicationFiled: December 6, 2021Publication date: June 8, 2023Inventors: Cheng-Wei Cheng, ROBERT L. BRUCE, Matthew Joseph BrightSky, Gloria Wing Yun Fraczak
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Patent number: 11665983Abstract: A structure including a bottom electrode, a phase change material layer vertically aligned and an ovonic threshold switching layer vertically aligned above the phase change material layer. A structure including a bottom electrode, a phase change material layer and an ovonic threshold switching layer vertically aligned above the phase change material layer, and a first barrier layer physically separating the ovonic threshold switching layer from a top electrode. A method including forming a structure including a liner vertically aligned above a first barrier layer, the first barrier layer vertically aligned above a phase change material layer, the phase change material layer vertically aligned above a bottom electrode, forming a dielectric surrounding the structure, and forming an ovonic threshold switching layer on the first barrier layer, vertical side surfaces of the first buffer layer are vertically aligned with the first buffer layer, the phase change material layer and the bottom electrode.Type: GrantFiled: December 11, 2020Date of Patent: May 30, 2023Assignee: International Business Machines CorporationInventors: Nanbo Gong, Takashi Ando, Robert L. Bruce, Alexander Reznicek, Bahman Hekmatshoartabari
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Publication number: 20220367797Abstract: A method for fabricating a semiconductor device includes forming air gaps within respective dielectric layer portions to reduce thermal cross-talk between adjacent bits. Each of the dielectric portions is formed on a substrate each adjacent to sidewall liners formed on sidewalls of a phase change memory (PCM) layer. The method further includes forming a pillar including the sidewall liners and the PCM layer, and forming a selector layer on the pillar and the dielectric portions.Type: ApplicationFiled: July 28, 2022Publication date: November 17, 2022Inventors: Wanki Kim, Fabio Carta, Chung H. Lam, Robert L. Bruce
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Publication number: 20220310912Abstract: Aspects of the present invention provide a semiconductor structure for a phase change memory device that includes a heater element on a bottom electrode that is surrounded by a dielectric material. The phase change memory device includes a metal nitride liner over the heater element, where the metal liner is oxide-free with a desired electrical resistance. The phase change memory device includes a phase change material is over the heater element and the dielectric material and a top electrode is over the phase change material.Type: ApplicationFiled: March 26, 2021Publication date: September 29, 2022Inventors: ROBERT L. BRUCE, Cheng-Wei Cheng, Matthew Joseph BrightSky
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Patent number: 11456417Abstract: A mushroom type phase change memory (PCM) cell includes a projection liner located between a PCM volume and a bottom electrode. The projection liner has been retained from a layer previously utilized as an etch stop layer during the fabrication of PCM cell and/or the fabrication of the higher level IC device. The projection liner may extend beyond the PCM sidewall(s) or side boundary. This section of the projection liner may be located or buried under a dielectric or an encapsulation spacer and may increase thickness uniformity of the projection liner below the PCM volume.Type: GrantFiled: November 25, 2020Date of Patent: September 27, 2022Assignee: International Business Machines CorporationInventors: Kevin W. Brew, Injo Ok, Iqbal Rashid Saraf, Nicole Saulnier, Matthew Joseph BrightSky, Robert L. Bruce
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Patent number: 11437571Abstract: A method for fabricating a semiconductor device includes forming air gaps within respective dielectric layer portions to reduce thermal cross-talk between adjacent bits. Each of the dielectric portions is formed on a substrate each adjacent to sidewall liners formed on sidewalls of a phase change memory (PCM) layer. The method further includes forming a pillar including the sidewall liners and the PCM layer, and forming a selector layer on the pillar and the dielectric portions.Type: GrantFiled: June 25, 2019Date of Patent: September 6, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wanki Kim, Fabio Carta, Chung H. Lam, Robert L. Bruce
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Publication number: 20220254995Abstract: A phase change memory cell for a semiconductor device that includes a heater element on a first conductive layer with a spacer surrounding sides of the heater element. The phase change memory cell includes a first dielectric layer on the conductive layer and on a bottom portion of the spacer surrounding the heater element and a second dielectric layer on the first dielectric layer surrounding a top portion of the heater element. The phase change memory cell includes a phase change material on a top surface of the heater element and on the second dielectric material.Type: ApplicationFiled: February 10, 2021Publication date: August 11, 2022Inventors: JIN PING HAN, Philip Joseph Oldiges, ROBERT L. BRUCE, Ching-Tzu Chen
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Publication number: 20220209113Abstract: A method for mitigating moisture driven degradation of silicon doped chalcogenides includes placing a silicon doped chalcogenide composition in a process chamber, passivating dangling silicon bonds of the silicon doped chalcogenide composition by flooding the process chamber with forming gas or with hydrogen plasma, purging the forming gas or the hydrogen plasma from the process chamber, and removing the passivated silicon doped chalcogenide composition from the process chamber.Type: ApplicationFiled: December 29, 2020Publication date: June 30, 2022Inventors: Cheng-Wei Cheng, Huai-Yu Cheng, I-Ting Kuo, Robert L. Bruce, Martin Michael Frank, Hiroyuki Miyazoe
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Publication number: 20220190238Abstract: A structure including a bottom electrode, a phase change material layer vertically aligned and an ovonic threshold switching layer vertically aligned above the phase change material layer. A structure including a bottom electrode, a phase change material layer and an ovonic threshold switching layer vertically aligned above the phase change material layer, and a first barrier layer physically separating the ovonic threshold switching layer from a top electrode. A method including forming a structure including a liner vertically aligned above a first barrier layer, the first barrier layer vertically aligned above a phase change material layer, the phase change material layer vertically aligned above a bottom electrode, forming a dielectric surrounding the structure, and forming an ovonic threshold switching layer on the first barrier layer, vertical side surfaces of the first buffer layer are vertically aligned with the first buffer layer, the phase change material layer and the bottom electrode.Type: ApplicationFiled: December 11, 2020Publication date: June 16, 2022Inventors: Nanbo Gong, Takashi Ando, ROBERT L. BRUCE, Alexander Reznicek, Bahman Hekmatshoartabari
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Patent number: 11355706Abstract: A cross-point memory array and stacked memory array structure. The memory array includes a plurality of first conductive line structures formed in a dielectric material layer; a plurality of memory elements, each memory element including a fill-in phase change memory (PCM) cell, and an access device enabling read or write access to said memory PCM structure; a plurality of second conductive line structures, the plurality of second conductive structures perpendicularly oriented relative to the plurality of first conductive structures. An individual memory element of the plurality of memory elements is conductively connected at a respective intersection between a first conductive line structure and a second conductive line structure. Each phase change memory (PCM) cell of a memory element at an intersection having a sub-lithographic conductive tuning liner disposed on only one sidewall of the PCM cell. The manufacturing maintains a minimal number of masking and processing steps.Type: GrantFiled: June 19, 2020Date of Patent: June 7, 2022Assignee: International Business Machines CorporationInventors: Robert L. Bruce, Matthew Joseph BrightSky, SangBum Kim