Patents by Inventor Rohit Bhatia
Rohit Bhatia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8538849Abstract: An exemplary aspect comprises receiving data related to an underlying asset; calculating values corresponding to near-term implied volatility and realized volatility for the underlying asset; and transmitting data sufficient to describe an index based on a difference between the values corresponding to the near-term implied volatility and the realized volatility for the underlying asset. Another exemplary aspect comprises receiving electronic data related to an underlying asset; calculating data sufficient to describe a plurality of call options and a plurality of put options related to the underlying asset and written on a first settlement date; crediting an account with proceeds from selling the call and put options; and debiting the account to settle one or more of the options that are in-the-money on a second settlement date. Other aspects are apparent from the description and claims.Type: GrantFiled: July 26, 2011Date of Patent: September 17, 2013Assignee: Barclays Capital Inc.Inventors: Michael Schmanske, Maneesh Deshpande, Rohit Bhatia, Yidong Ding, Pankaj Khandelwal
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Patent number: 8479029Abstract: Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.Type: GrantFiled: June 24, 2011Date of Patent: July 2, 2013Assignee: Intel CorporationInventors: Kevin Safford, Rohit Bhatia, Chris Bostak, Richard Blumberg, Blaine Stackhouse, Steve Undy
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Patent number: 8219780Abstract: Systems, methodologies, media, and other embodiments associated with mitigating the effects of context switch cache and TLB misses are described. One exemplary system embodiment includes a processor configured to run a multiprocessing, virtual memory operating system. The processor may be operably connected to a memory and may include a cache and a translation lookaside buffer (TLB) configured to store TLB entries. The exemplary system may include a context control logic configured to selectively copy data from the TLB to the data store for a first process being swapped out of the processor and to selectively copy data from the data store to the TLB for a second process being swapped into to the processor.Type: GrantFiled: September 16, 2005Date of Patent: July 10, 2012Assignee: Hewlett-Packard Development Company, L.P.Inventors: James R. Callister, Eric R. Delano, Rohit Bhatia, Shawn Kenneth Walker, Mark M. Gibson
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Publication number: 20120023036Abstract: An exemplary aspect comprises receiving data related to an underlying asset; calculating values corresponding to near-term implied volatility and realized volatility for the underlying asset; and transmitting data sufficient to describe an index based on a difference between the values corresponding to the near-term implied volatility and the realized volatility for the underlying asset. Another exemplary aspect comprises receiving electronic data related to an underlying asset; calculating data sufficient to describe a plurality of call options and a plurality of put options related to the underlying asset and written on a first settlement date; crediting an account with proceeds from selling the call and put options; and debiting the account to settle one or more of the options that are in-the-money on a second settlement date. Other aspects are apparent from the description and claims.Type: ApplicationFiled: July 26, 2011Publication date: January 26, 2012Inventors: MICHAEL SCHMANSKE, Maneesh Deshpande, Rohit Bhatia, Yidong Ding, Pankaj Khandelwal
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Publication number: 20110252255Abstract: Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.Type: ApplicationFiled: June 24, 2011Publication date: October 13, 2011Inventors: Kevin Safford, Rohit Bhatia, Chris Bostak, Richard Blumberg, Blaine Stackhouse, Steve Undy
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Patent number: 7992017Abstract: Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.Type: GrantFiled: September 11, 2007Date of Patent: August 2, 2011Assignee: Intel CorporationInventors: Kevin Safford, Rohit Bhatia, Chris Bostak, Richard Blumberg, Blaine Stackhouse, Steve Undy
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Patent number: 7930539Abstract: In a computer system including a plurality of resources, a device receives a request from a software program to access a specified one of the plurality of resources, determines whether the specified one of the plurality of resources is a protected resource. If the specified one of the plurality of resources is a protected resource, the device denies the request if the computer system is operating in a protected mode of operation, and processes the request based on access rights associated with the software program if the computer system is not operating in the protected mode of operation.Type: GrantFiled: August 3, 2004Date of Patent: April 19, 2011Assignee: Hewlett-Packard Development Company, L.P.Inventors: Donald C. Soltis, Jr., Rohit Bhatia, Eric R. DeLano
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Patent number: 7856636Abstract: Systems and methods of sharing processing resources in a multi-threading environment are disclosed. An exemplary method may include allocating a lock value for a resource lock, the lock value corresponding to a state of the resource lock. A first thread may yield at least a portion of the processing resources for another thread. The resource lock may be acquired for the first thread if the lock value indicates the resource lock is available.Type: GrantFiled: May 10, 2005Date of Patent: December 21, 2010Assignee: Hewlett-Packard Development Company, L.P.Inventors: Rohit Bhatia, Don C. Soltis, Jr.
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Patent number: 7634508Abstract: Duplicate record processing is enabled employing on customizable rules. Detected duplicate records are merged, deleted, deactivated, or moved based on one or more sets of customizable rules. Different rule sets may be used for each record type, or a rule set reused for different records. Hierarchical relationships between master and child records are adjusted upon duplicate processing based on rules and/or record attributes.Type: GrantFiled: March 29, 2007Date of Patent: December 15, 2009Assignee: Microsoft CorporationInventors: Rohit Bhatia, Subodh Kumar, Nitin Mukhija, Abhishek Agarwal
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Publication number: 20090070607Abstract: Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.Type: ApplicationFiled: September 11, 2007Publication date: March 12, 2009Inventors: Kevin Safford, Rohit Bhatia, Chris Bostak, Richard Blumberg, Blaine Stackhouse, Steve Undy
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Publication number: 20080243967Abstract: Duplicate record processing is enabled employing on customizable rules. Detected duplicate records are merged, deleted, deactivated, or moved based on one or more sets of customizable rules. Different rule sets may be used for each record type, or a rule set reused for different records. Hierarchical relationships between master and child records are adjusted upon duplicate processing based on rules and/or record attributes.Type: ApplicationFiled: March 29, 2007Publication date: October 2, 2008Applicant: Microsoft CorporationInventors: Rohit Bhatia, Subodh Kumar, Nitin Mukhija, Abhishek Agarwal
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Patent number: 7421689Abstract: Virtual-machine-monitor operation and implementation is facilitated by number of easily implemented features and extensions added to the features of a processor architecture. These features, one or more of which are used in various embodiments of the present invention, include a vmsw instruction that provides a means for transitioning between virtualization mode and non-virtualization mode without an interruption, a virtualization fault that faults on an attempt by a priority-0 routine in virtualization mode attempting to execute a privileged instruction, and a flexible highest-implemented-address mechanism to partition virtual address space into a virtualization address space and a non-virtualization address space.Type: GrantFiled: October 28, 2003Date of Patent: September 2, 2008Assignee: Hewlett-Packard Development Company, L.P.Inventors: Jonathan K. Ross, Dale Morris, Donald C. Soltis, Jr., Rohit Bhatia, Eric Delano
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Patent number: 7409524Abstract: The present invention relates to an improved microprocessor having a memory system with several caches that can be operated to provide virtual memory. Among the caches included in the microprocessor are conventional caches that store data and instructions to be utilized by the processes being performed by the microprocessor, and that are typically arranged in a cache hierarchy, as well as one or more translation lookaside buffer (TLB) caches that store a limited number of virtual page translations. The improved microprocessor also has an additional cache that serves to store a virtual hash page table (VHPT) that is accessed when TLB misses occur. The introduction of this VHPT cache eliminates or at least reduces the need for the microprocessor to look for information within the caches of the cache hierarchy or in other memory (e.g., main memory) outside of the microprocessor when TLB misses occur, and consequently enhances microprocessor speed.Type: GrantFiled: August 17, 2005Date of Patent: August 5, 2008Assignee: Hewlett-Packard Development Company, L.P.Inventors: Kevin Safford, Rohit Bhatia, Karl Brummel
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Publication number: 20070299679Abstract: A business system interface for accessing data from a Line-of-Business (LOB) system from within an information worker productivity (IWP) application is provided. The business system interface includes an embedded business system user interface contained within a user interface of the IWP application. Also included, is a business data access component that can retrieve data from the LOB system and provide the retrieved data to the embedded business system user interface. The embedded business system user interface and the business data access component contain at least some managed code components.Type: ApplicationFiled: August 23, 2006Publication date: December 27, 2007Applicant: Microsoft CorporationInventors: Amit Sudan, Manbhawan Prasad, Maninderjit Singh, Rohit Bhatia, Sandeep Sadanandan
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Patent number: 7213134Abstract: A processing unit of the invention has multiple instruction pipelines for processing multi-threaded instructions. Each thread may have an urgency associated with its program instructions. The processing unit has a thread switch controller to monitor processing of instructions through the various pipelines. The thread controller also controls switch events to move from one thread to another within the pipelines. The controller may modify the urgency of any thread such as by issuing an additional instruction. The thread controller preferably utilizes certain heuristics in making switch event decisions. A time slice expiration unit may also monitor expiration of threads for a given time slice.Type: GrantFiled: March 6, 2002Date of Patent: May 1, 2007Assignee: Hewlett-Packard Development Company, L.P.Inventors: Donald C. Soltis, Jr., Rohit Bhatia
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Publication number: 20070067602Abstract: Systems, methodologies, media, and other embodiments associated with mitigating the effects of context switch cache and TLB misses are described. One exemplary system embodiment includes a processor configured to run a multiprocessing, virtual memory operating system. The processor may be operably connected to a memory and may include a cache and a translation lookaside buffer (TLB) configured to store TLB entries. The exemplary system may include a context control logic configured to selectively copy data from the TLB to the data store for a first process being swapped out of the processor and to selectively copy data from the data store to the TLB for a second process being swapped into to the processor.Type: ApplicationFiled: September 16, 2005Publication date: March 22, 2007Inventors: James Callister, Eric Delano, Rohit Bhatia, Shawn Walker, Mark Gibson
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Publication number: 20070043929Abstract: The present invention relates to an improved microprocessor having a memory system with several caches that can be operated to provide virtual memory. Among the caches included in the microprocessor are conventional caches that store data and instructions to be utilized by the processes being performed by the microprocessor, and that are typically arranged in a cache hierarchy, as well as one or more translation lookaside buffer (TLB) caches that store a limited number of virtual page translations. The improved microprocessor also has an additional cache that serves to store a virtual hash page table (VHPT) that is accessed when TLB misses occur. The introduction of this VHPT cache eliminates or at least reduces the need for the microprocessor to look for information within the caches of the cache hierarchy or in other memory (e.g., main memory) outside of the microprocessor when TLB misses occur, and consequently enhances microprocessor speed.Type: ApplicationFiled: August 17, 2005Publication date: February 22, 2007Inventors: Kevin Safford, Rohit Bhatia, Karl Brummel
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Publication number: 20060259907Abstract: Systems and methods of sharing processing resources in a multi-threading environment are disclosed. An exemplary method may include allocating a lock value for a resource lock, the lock value corresponding to a state of the resource lock. A first thread may yield at least a portion of the processing resources for another thread. The resource lock may be acquired for the first thread if the lock value indicates the resource lock is available.Type: ApplicationFiled: May 10, 2005Publication date: November 16, 2006Inventors: Rohit Bhatia, Don Soltis
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Publication number: 20060136286Abstract: The method may include creating a marketing campaign, selecting a list to receive the marketing campaign, allowing the user to modify the list selected, allowing the user to add a work item to the marketing campaign and executing the marketing campaign.Type: ApplicationFiled: December 22, 2004Publication date: June 22, 2006Applicant: MICROSOFT CORPORATIONInventors: Prashant Gupta, Kulo Rajasekaran, Liju Thomas, Derek LaSalle, Rohit Bhatia, Amit Kumar
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Publication number: 20060031672Abstract: In one embodiment of the present invention, a computer-implemented method is provided for use in a computer system including a plurality of resources. The plurality of resources include protected resources and unprotected resources. The unprotected resources include critical resources and non-critical resources. The method includes steps of: (A) receiving a request from a software program to access a specified one of the unprotected resources; (B) granting the request if the computer system is operating in a non-protected mode of operation; and (C) if the computer system is operating in a protected mode of operation, performing a step of denying the request if the computer system is not operating in a protected diagnostic mode of operation.Type: ApplicationFiled: August 3, 2004Publication date: February 9, 2006Inventors: Donald Soltis, Rohit Bhatia, Eric DeLano, Bill Greene, Amy Santoni