Patents by Inventor Timothy Dalton
Timothy Dalton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240102605Abstract: A multi-legged equipment support, components thereof, and associated methods. The equipment support comprises a stand and an equipment holder. The stand includes a hub and multiple legs pivotable with respect to the hub. The legs are pivotable outward from stowed positions to preset operational pivoted positions. The user can select a preset operational pivoted position in which outward pivoting of a leg will stop based on moving an actuator between preset locations.Type: ApplicationFiled: December 11, 2023Publication date: March 28, 2024Applicant: AOB Products CompanyInventors: Brian Steere, Michael Cottrell, Timothy S. Kinney, James Tayon, Jason Nickerson, Justin Burke, Anthony Vesich, Dennis W. Cauley, JR., Mark Dalton, Kyle Smith
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Publication number: 20240077282Abstract: An anti-cant indicator assembly, components thereof, and associated methods. The anti-cant indicator assembly indicates the orientation of a weapon with respect to vertical. The anti-cant indicator assembly includes a mount configured to mount to the weapon, a level including a vial containing a bubble and a pivot connection connecting the level to the mount. The pivot connection is configured to permit movement of the level with respect to the mount about the pivot connection between an operational position in which the bubble can be referenced by the user for indicating orientation of the weapon with respect to vertical, and a stowed position different from the operational position. The pivot connection can include a retainer configured to releasably retain the level in at least one of the operational position or the stowed position. The level can be selectively movable with respect to the mount to calibrate the anti-cant indicator.Type: ApplicationFiled: November 10, 2023Publication date: March 7, 2024Applicant: AOB Products CompanyInventors: Mike Lindsay, Michael Cottrell, James Tayon, Timothy S. Kinney, Mark Dalton, Brian Steere, Justin Burke, Kyle Martin, Dennis W. Cauley, JR., Anthony Vesich, Ryan Varnum, Seth Wheeler, Brett Eckelkamp, Matthew Kinamore, Curtis Smith
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Publication number: 20220361888Abstract: Embolic coils with detachable segments that are separated by detachment capsules that are thermolytically degradable such that varying lengths of coil may be implanted into a vascular malformation to occlude same. The capsules are radiotransparent when compared to the adjoining coil segments to the location of the segments is easily seen. The capsules further include protruding electrical contacts that make positive contact with terminals on a delivery catheter. The terminals on the delivery catheter serve as markers so the relationship between the detachment capsules and the terminals is easily visible under x-ray.Type: ApplicationFiled: July 20, 2022Publication date: November 17, 2022Applicant: MicroVention, Inc.Inventors: Heath Bowman, Nga-Ting Wong, Joseph Rye, Timothy Dalton
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Patent number: 11439401Abstract: Embolic coils with detachable segments that are separated by detachment capsules that are thermolytically degradable such that varying lengths of coil may be implanted into a vascular malformation to occlude same. The capsules are radiotransparent when compared to the adjoining coil segments to the location of the segments is easily seen. The capsules further include protruding electrical contacts that make positive contact with terminals on a delivery catheter. The terminals on the delivery catheter serve as markers so the relationship between the detachment capsules and the terminals is easily visible under x-ray.Type: GrantFiled: November 15, 2019Date of Patent: September 13, 2022Assignee: MicroVention, Inc.Inventors: Heath Bowman, Nga-Ting Wong, Joseph Rye, Timothy Dalton
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Publication number: 20200155161Abstract: Embolic coils with detachable segments that are separated by detachment capsules that are thermolytically degradable such that varying lengths of coil may be implanted into a vascular malformation to occlude same. The capsules are radiotransparent when compared to the adjoining coil segments to the location of the segments is easily seen. The capsules further include protruding electrical contacts that make positive contact with terminals on a delivery catheter. The terminals on the delivery catheter serve as markers so the relationship between the detachment capsules and the terminals is easily visible under x-ray.Type: ApplicationFiled: November 15, 2019Publication date: May 21, 2020Applicant: MicroVention, Inc.Inventors: Heath Bowman, Nga-Ting Wong, Joseph Rye, Timothy Dalton
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Patent number: 9059000Abstract: Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.Type: GrantFiled: April 21, 2008Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: Deok-kee Kim, Kenneth T. Settlemyer, Jr., Kangguo Cheng, Ramachandra Divakaruni, Carl J. Radens, Dirk Pfeiffer, Timothy Dalton, Katherina Babich, Arpan P. Mahorowala, Harald Okorn-Schmidt
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Patent number: 8689152Abstract: A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.Type: GrantFiled: March 4, 2013Date of Patent: April 1, 2014Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Timothy Dalton, Jeffrey P. Gambino, Mark D. Jaffe, Paul D. Kartschoke, Stephen E. Luce, Anthony K. Stamper
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Patent number: 8471306Abstract: A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.Type: GrantFiled: July 28, 2011Date of Patent: June 25, 2013Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Timothy Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Stephen Ellinwood Luce, Anthony Kendall Stamper
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Patent number: 8421126Abstract: Semiconductor structures. The semiconductor structures include two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers or bonding them back to back utilizing an inter-substrate dielectric layer and a bonding layer between the buried oxide layers. The structures include contacts formed in the upper wafer to devices in the lower wafer and wiring levels formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.Type: GrantFiled: June 20, 2011Date of Patent: April 16, 2013Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Timothy Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Stephen Ellinwood Luce, Anthony Kendall Stamper
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Publication number: 20120292741Abstract: Interconnect structures that include a passive element, such as a thin film resistor or a metal-insulator-metal (MIM) capacitor, methods for fabricating an interconnect structure that includes a passive element, and design structures embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, such as a radiofrequency integrated circuit. A top surface of a dielectric layer is recessed relative to a top surface of a conductive feature in the dielectric layer. The passive element is formed on the recessed top surface of the dielectric layer and includes a layer of a conductive material that is coplanar with, or below, the top surface of the conductive feature.Type: ApplicationFiled: July 27, 2012Publication date: November 22, 2012Applicant: International Business Machines CorporationInventors: Timothy Dalton, Ebenezer E. Eshun, Sarah L. Grunow, Zhong-Xiang He, Anthony K. Stamper
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Patent number: 8024012Abstract: A system and methodology for intelligent power management of wirelessly networked devices. The system provides for reliable wireless communication via a wireless power charging method and, a method to maintain power capacity of batteries in a wireless device. The batteries are charged via an RF harvesting unit embedded inside the wireless device. An intelligent wireless power charging system further comprises at least two batteries and at least two RF adaptor devices coupled to an AC power line. The first adaptor is set for data communication while the second adaptor is used to transmit the power. In addition, when a first battery is in use during active mode, the second battery is subjected to wireless charging.Type: GrantFiled: June 11, 2008Date of Patent: September 20, 2011Assignee: International Business Machines CorporationInventors: Lawrence Clevenger, Timothy Dalton, Louis Hsu, Carl Radens
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Patent number: 7989312Abstract: A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.Type: GrantFiled: November 5, 2009Date of Patent: August 2, 2011Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Timothy Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Stephen Ellinwood Luce, Anthony Kendall Stamper
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Patent number: 7863734Abstract: An electronic device and method of packaging an electronic device. The device including: a first substrate, a second substrate and an integrated circuit chip having a first side and an opposite second side, a first set of chip pads on the first side and a second set of chip pads on the second side of the integrated circuit chip, chip pads of the first set of chip pads physically and electrically connected to corresponding substrate pads on the first substrate and chip pads of the second set of chip pads physically and electrically connected to substrate pads of the substrate.Type: GrantFiled: August 6, 2008Date of Patent: January 4, 2011Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Timothy Dalton, Timothy Harrison Daubenspeck, Jeffrey Peter Gambino, Mark David Jaffe, Christopher David Muzzy, Wolfgang Sauter, Edmund Sprogis, Anthony Kendall Stamper
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Patent number: 7820559Abstract: An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx— or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.Type: GrantFiled: June 23, 2008Date of Patent: October 26, 2010Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Stefanie R. Chiras, Timothy Dalton, James J. Demarest, Darren N. Dunn, Chester T. Dziobkowski, Philip L. Flaitz, Michael W. Lane, James R. Lloyd, Darryl D. Restaino, Thomas M. Shaw, Yun-Yu Wang, Chih-Chao Yang
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Publication number: 20100237467Abstract: Interconnect structures that include a passive element, such as a thin film resistor or a metal-insulator-metal (MIM) capacitor, methods for fabricating an interconnect structure that includes a passive element, and design structures embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, such as a radiofrequency integrated circuit. A top surface of a dielectric layer is recessed relative to a top surface of a conductive feature in the dielectric layer. The passive element is formed on the recessed top surface of the dielectric layer and includes a layer of a conductive material that is coplanar with, or below, the top surface of the conductive feature.Type: ApplicationFiled: December 10, 2009Publication date: September 23, 2010Applicant: International Business Machines CorporationInventors: Timothy Dalton, Ebenezer E. Eshun, Sarah L. Grunow, Zhong-Xiang He, Anthony K. Stamper
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Publication number: 20100044759Abstract: A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.Type: ApplicationFiled: November 5, 2009Publication date: February 25, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kerry Bernstein, Timothy Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Stephen Ellinwood Luce, Anthony Kendall Stamper
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Patent number: 7657995Abstract: A method of fabricating a MEMS switch that is fully integratable in a semiconductor fabrication line. The method consists of forming two posts, each end thereof terminating in a cap; a rigid movable conductive plate having a surface terminating in a ring in each of two opposing edges, the rings being loosely connected to guiding posts; forming upper and lower electrode pairs and upper and lower interconnect wiring lines connected and disconnected by the rigid movable conductive plate. The conductive plate moves up, shorting two upper interconnect wirings lines. Conversely, the conductive plate moves down when the voltage is applied to the lower electrode pair, while the upper electrode pair is grounded, shorting the two lower interconnect wiring lines and opening the upper wiring lines.Type: GrantFiled: July 12, 2007Date of Patent: February 9, 2010Assignee: International Business Machines CorporationInventors: Louis Hsu, Timothy Dalton, Lawrence Clevenger, Carl Radens, Kwong Hon Wong, Chih-Chao Yang
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Publication number: 20090312046Abstract: A system and methodology for intelligent power management of wirelessly networked devices. The system provides for reliable wireless communication via a wireless power charging method and, a method to maintain power capacity of batteries in a wireless device. The batteries are charged via an RF harvesting unit embedded inside the wireless device. An intelligent wireless power charging system further comprises at least two batteries and at least two RF adaptor devices coupled to an AC power line. The first adaptor is set for data communication while the second adaptor is used to transmit the power. In addition, when a first battery is in use during active mode, the second battery is subjected to wireless charging.Type: ApplicationFiled: June 11, 2008Publication date: December 17, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence Clevenger, Timothy Dalton, Louis Hsu, Carl Radens
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Publication number: 20090065925Abstract: An electronic device and method of packaging an electronic device. The device including: a first substrate, a second substrate and an integrated circuit chip having a first side and an opposite second side, a first set of chip pads on the first side and a second set of chip pads on the second side of the integrated circuit chip, chip pads of the first set of chip pads physically and electrically connected to corresponding substrate pads on the first substrate and chip pads of the second set of chip pads physically and electrically connected to substrate pads of the substrate.Type: ApplicationFiled: August 6, 2008Publication date: March 12, 2009Inventors: Kerry Bernstein, Timothy Dalton, Timothy Harrison Daubenspeck, Jeffrey Peter Gambino, Mark David Jaffe, Christopher David Muzzy, Wolfgang Sauter, Edmund Sprogis, Anthony Kendall Stamper
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Patent number: 7497959Abstract: Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.Type: GrantFiled: May 11, 2004Date of Patent: March 3, 2009Assignee: International Business Machines CorporationInventors: Deok-kee Kim, Kenneth T. Settlemyer, Jr., Kangguo Cheng, Ramachandra Divakaruni, Carl J. Radens, Dirk Pfeiffer, Timothy Dalton, Katherina Babich, Arpan P. Mahorowala, Harald Okorn-Schmidt