Abstract: A monitor program stored in a ROM of a microcomputer chip of a computer is operated both to (1) save power by disabling all external buses, turning off power to a communication port, deselecting all external memory devices, and turning off a fast clock oscillator and clocking all operations of the microcomputer chip at a slow second frequency, and also to (2) prioritize execution of a plurality of application programs located in external memory devices and/or internal memory of the microcomputer chip while also relying on the monitor program to effectuate normal initialization procedures. The monitor program also allows efficient access to slow external memory devices by dividing down the fast clock rate produced by the oscillator to a slower rate and accessing the slow memory at the slower rate, thereby saving power.

Abstract: A method of operating a CMOS microcomputer to minimize power dissipation while accessing a plurality of memories including a first memory operable at a first frequency, a second memory operable at a lower second frequency, including operating the entire CMOS microcomputer at the first frequency while accessing the first memory, causing the CMOS microcomputer to dissipate power at a first level, determining from a user program currently being executed that it is necessary to access the second memory, and operating the entire CMOS microcomputer at the lower second frequency while accessing the second memory to cause the CMOS microcomputer to dissipate power at a second level which is lower than the first level.

Abstract: A CMOS integrated circuit microcomputer is switchable under software control between high speed, high power operation and low speed, low power operation. The microcomputer includes asynchronous fast and slow clock oscillators. A synchronizing circuit coupled to the fast and slow clock oscillators receives a clock selection signal, and in response thereto produces a clock enable signal. The clock enable signal has the same frequency as and is synchronized with either the fast clock signal or the slow clock signal, depending on the state of the clock selection signal. The clock enable signal is input to gating circuitry that gates either the fast or the slow clock signal to provide a selectable speed clock signal to be used elsewhere in the microcomputer.

Abstract: The topography of an 84 lead CMOS microcomputer chip includes first, second, third, and fourth consecutive edges, with chip control logic being located along the upper left edge. The chip includes six multiplexed peripheral I/O port buffer circuits, a data bus buffer port, chip control logic, tone buffers, and system speed control circuitry located around the edge of the periphery of the chip. One of the six ports functions as a parallel interface bus. The microcomputer includes a sixteen bit W65C816S CMOS microprocessor, 576 bytes of SRAM, 8192 bytes of SROM, a plurality of edge interrupt inputs and level-sensitive interrupt inputs, four UARTs, eight timers, priority interrupt control circuitry, and two tone generators. The topography is arranged to provide convenient connection of terminals of the microcomputer when it is used as a "core" of a larger computer system chip including an external memory system, a serial communication system, and an interrupt and I/O system.

Abstract: A CMOS integrated circuit microcomputer system includes circuitry for sensing trinary logic states by using a tri-state driver circuit connected to both the input and output of a binary latch having only two states, both of which produce a high output impedance. A first trinary logic level is represented by a first logic level produced and maintained on the conductor by the external device, overpowering the binary latch. A second logic state is represented by a second logic level produced and maintained on the conductor by the external device. A third trinary state is represented by an off condition of the tri-state driver, in which case the binary latch holds whatever state is produced by the microcomputer of the connector.

Abstract: The topography of a CMOS microcomputer chip includes first, second, third, and fourth consecutive edges, with chip control logic being located along the upper left edge. Five peripheral I/O port buffer circuits are located around the edge of the periphery of the chip, except for an eight bit peripheral output port located along the lower right edge and multiplexed with chip select outputs. The microcomputer includes an eight bit W65CO2S CMOS microprocessor, 192 bytes of SRAM, 4096 bytes of SROM, 22 edge interrupt inputs, 3 level-sensitive interrupt inputs, a UART, serial interface buffer for effectuating correction to a local area token passing network, four timers, and priority interrupt control circuitry. The topography is arranged to provide convenient connection of terminals of the microcomputer when it is used as a "core" of a larger computer system chip including an external memory system, a serial communication system, and an interrupt and I/O system.

Abstract: An abort circuit for a microprocessor includes a circuit receiving and latching an external abort signal to produce an internal abort signal, and circuitry responsive to the internal abort signal for preventing register transfer circuitry from responding to register transfer signals during execution of a current instruction that would otherwise result in modifying information in internal non-addressable programmable registers during duration of the internal abort signal, and abort reset circuity for responding to a reset signal to cause the abort input circuitry to stop producing the internal abort signal at the end of the abort condition.

Abstract: A sixteen bit microprocessor includes an emulation bit that is loaded into an instruction register with 8 bit op codes. If the emulation bit is a "1", the 16 bit microprocessor operates internally as a 6502 type eight bit microprocessor, thereby emulating a 6502 microprocessor. If the emulation bit is set to a "0", the 16 bit microprocessor executes an instruction set of which the 6502 instruction set is a subset to effectuate internal 16 bit operation.

Abstract: The topography of a CMOS microprocessor chip includes address buffer circuitry along the bottom and lower left hand edges of the chip, data bus buffers disposed along the lower right hand edge of the chip, address register circuitry and an arithmetic logic unit contained in a register section adjacent to both the address buffer circuitry and data bus buffer circuitry, register transfer circuitry adjacent to and above the register section, P channel circuitry disposed directly above the register transfer circuitry for producing sum-of-minterm signals applied to the register transfer circuitry in response to the minterm signals produced by N channel circuitry disposed adjacent to and immediately above the P channel circuitry. Status register circuitry responsive to status register control logic disposed along the top edge of the chip is positioned in the register section for direct, low capacitance connection to the internal data bus.

Abstract: The topography of a sixteen bit CMOS microprocessor chip including circuitry for enabling it to emulate, under software control, a prior art 6502 microprocessor includes an N-channel minterm logic section including 498 "vertical" diffused minterm lines across which 32 "horizontal" metal lines from an instruction register and a timing generator pass and make selective contact to separate polycrystalline silicon gate electrodes to effectuate a first level of instruction op code decoding. The resulting minterm signals are inverted by a row of CMOS inverters, the outputs of which are connected to polycrystalline lines extending into an N-channel sum-of-minterm section. "Horizontal" metal sum-of-minterm conductors contact various N-channel field effect transistors in the sum-of-minterm region.

Abstract: The topography of a CMOS microprocessor chip includes address buffer circuitry along the bottom and lower left hand edges of the chip, data bus buffers disposed along the lower right hand edge of the chip, address register circuitry and an arithmetic logic unit contained in a register section adjacent to both the address buffer circuitry and data bus buffer circuitry, register transfer circuitry adjacent to and above the register section, P channel circuitry disposed directly above the register transfer circuitry for producing sum-of-minterm signals applied to the register transfer circuitry in response to the minterm signals produced by N channel circuitry disposed adjacent to and immediately above the P channel circuitry. Status register circuitry responsive to status register control logic disposed along the top edge of the chip is positioned in the register section for direct, low capacitance connection to the internal data bus.

Abstract: A digital system including a plurality of metal-oxide-semiconductor (MOS) chip random access memories (RAM), read only memories (ROM) and peripheral interface adaptors coupled to a common bidirectional data bus which is coupled to and controlled by a microprocessor unit (MPU). Each peripheral interface adaptor includes a control register loadable under program control. The contents of the control register control selection of several registers within the interface adaptor. The control register also controls other functions of the peripheral interface adaptor, including determining direction of data movement at the peripheral buffers of the interface adaptor. The contents of the control register of each interface adaptor are monitorable by the microprocessor unit.

Abstract: A peripheral interface adaptor (PIA) circuit for data processing systems contains memory elements or control registers allowing modification under program control of the logical functions of the PIA.The peripheral interface adaptor includes a plurality of system data bus buffer circuits coupled to a system data bus and further includes peripheral interface buffer circuits coupled to a bidirectional peripheral data bus. The direction of data flow in the peripheral data bus is controlled by a data direction register. Data from the system data bus buffer is entered into an input register, and is transferred from there to an input bus coupled to the control register, a data direction register and a data register. Data from the peripheral data bus, the data direction register and the control register are transferred via an output bus to the system data bus buffers.

Abstract: An interval timer in a MOS IC microprocessor system uses a countdown register of as many stages as the data bus lines (8) but effectively doubles the capacity of that register, without increasing the number of data bus lines or repetitive loading, by interposing a prescale divide-down register between the system clock and the countdown register. The prescale register divides the system clock by one of several selectable factors equal to non-contiguous powers of two (e.g., by 1, 8, 64 or 1,024) to establish respective prescale time periods (of 1, 8, 64 or 1024 system clocK pulses). One of the several possible prescaling factors is selected by a pair of lines from the system address bus. As a result, the interval timer can be configured with one load operation for an interval within a range which was possible in the prior art only with double the number of data lines and double the length of the countdown register.

Abstract: A digital system includes a microprocessor coupled to a data bus and an address bus. A memory for storing data and instructions is connected to the data bus and the address bus. A peripheral device is connected to an interface adaptor. The interface adaptor is connected to the data bus and the address bus, and performs the function of interfacing between the digital system and a peripheral device, such as a printer or a display device. The microprocessor includes logic circuitry for generating a Valid Memory Address (VMA) output. The VMA output is used to generate an enable signal applied to the memory and the adaptor to enable the memory and the adaptor to be accessed by the microprocessor when the binary address on the address bus is valid and to prevent the memory and the adaptor from being accessed by the microprocessor when the binary address on the address bus is not valid with respect to the microprocessor.

Abstract: A microprocessor system includes a microprocessor, a memory, and an interface adaptor all coupled to a data bus. The interface adaptor is coupled between the data bus and a peripheral device, such as a teleprinter. A first interrupt conductor is connected to the peripheral device and to interrupt logic circuitry in the interface adaptor. A second interrupt conductor is connected to the microprocessor and the interrupt logic circuitry. The interrupt logic circuitry is also coupled to and interrogatable by the microprocessor via the data bus. The interrupt logic circuitry stores interrupt contrl information from the data bus, and generates a second interrupt signal on the second interrupt conductor in response to the stored interrupt control information and an interrupt signal generated on the first interrupt conductor by the peripheral device.

Abstract: An interface adaptor suitable for use in a microprocessor system includes an input register coupled to a bidirectional data bus of the microprocessor system. The interface adaptor includes a plurality of registers, including a control register and a data register, coupled to the input register by means of an internal input bus. Each of the plurality of registers includes flip-flops which are coupled as slave flip-flops to corresponding flip-flops of the input register. The corresponding flip-flops of the input register function as master flip-flops. The interface adaptor also includes register selection logic circuitry for selecting one of the plurality of registers by electrically coupling its slave flip-flop to the corresponding master flip-flops of the input register.

Abstract: Disclosed is an integrated circuit microprocessor with a parallel binary adder whose output can be corrected on-the-fly to provide decimal results. The correction is by logical gating which operates selectively and on-the-fly, that is, while the sum from the output of the binary adder is being transferred to an accumulator. As a result, the same binary adder can provide the binary sum of the operands supplied to it, or the binary coded decimal sum of bcd operands, or the binary coded decimal difference of bcd operands, in a single operating cycle and without the need to recycle the sum of the operands through the adder. This single cycle correction significantly speeds up the operation of the invented microprocessor as compared to known prior art microprocessors which recycle the adder output when a binary coded decimal sum or difference is required.

Abstract: The chip architecture of an MOS peripheral interface adaptor chip includes data bus buffers arranged along one edge of the chip, peripheral interface buffers arranged along an opposite edge of the chip and a register section centrally located on the chip. Separate power supply buses are used to supply a ground voltage to the buffer and register sections. Data bus buffers are arranged to allow the pins of the enclosing semiconductor package to correspond to data bus pins of a separate microprocessor chip. Register sections are offset on the surface of the peripheral interface adaptor chip in such a way as to facilitate nesting of the conductors coupled to the buffer circuit section. Identical buffer cells and custom drawn cells are both utilized so as to optimize use of semiconductor chip area.