Patents by Inventor Zhihong CHENG

Zhihong CHENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160233296
    Abstract: An integrated semiconductor device includes a substrate of a first conductivity type, a buried layer located over the substrate, an isolated region located over a first portion of the buried layer, and an isolation trench located around the isolated region. A punch-through structure is located around at least a portion of the isolation trench. The punch-through structure includes a second portion of the buried layer, a first region located over the second portion of the buried layer, the first region having a second conductivity type, and a second region located over the first region, the second region having the first conductivity type.
    Type: Application
    Filed: April 19, 2016
    Publication date: August 11, 2016
    Inventors: XU CHENG, DANIEL J. BLOMBERG, ZHIHONG ZHANG, JIANG-KAI ZUO
  • Patent number: 9401452
    Abstract: A light emitting device includes a p-side heterostructure having a short period superlattice (SPSL) formed of alternating layers of AlxhighGa1-xhighN doped with a p-type dopant and AlxlowGa1-xlowN doped with the p-type dopant, where xlow?xhigh?0.9. Each layer of the SPSL has a thickness of less than or equal to about six bi-layers of AlGaN.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: July 26, 2016
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: John E. Northrup, Bowen Cheng, Christopher L. Chua, Thomas Wunderer, Noble M. Johnson, Zhihong Yang
  • Patent number: 9343526
    Abstract: An integrated semiconductor device includes a substrate of a first conductivity type, a buried layer located over the substrate, an isolated region located over a first portion of the buried layer, and an isolation trench located around the isolated region. A punch-through structure is located around at least a portion of the isolation trench. The punch-through structure includes a second portion of the buried layer, a first region located over the second portion of the buried layer, the first region having a second conductivity type, and a second region located over the first region, the second region having the first conductivity type.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: May 17, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Xu Cheng, Daniel J. Blomberg, Zhihong Zhang, Jiang-Kai Zuo
  • Patent number: 9331991
    Abstract: Techniques are provided for improving security in a single-sign-on context by providing, to a user's client system, two linked authentication credentials in separate logical communication sessions and requiring that both credentials be presented to a host system. Only after presentation of both credentials is the user authenticated and permitted to access applications on the host system.
    Type: Grant
    Filed: October 7, 2009
    Date of Patent: May 3, 2016
    Assignee: Citrix Systems, Inc.
    Inventors: Yan Cheng, Zhihong Zhang
  • Patent number: 9191021
    Abstract: A pipelined analog-to-digital converter (ADC) that converts an analog input voltage signal Vin into a digital output value Dout. The ADC has a sequence of stages including a first calibrated stage having: (1) an ADC sub-module that receives Vin and provides an ADC sub-module digital output value based on Vin, (2) a DAC sub-module that receives the ADC sub-module digital output value and outputs a corresponding analog voltage signal VDAC, (3) a first difference module that generates an analog residual-voltage signal based on a difference between Vin and VDAC, and (4) an artificial-noise-insertion module that inserts an analog artificial-noise voltage signal into the residual voltage signal to generate an analog combined voltage signal. The analog combined voltage signal is used to calibrate the first calibrated stage. The artificial-noise-insertion module generates the polarity of the artificial-noise voltage signal based on the polarity of the corresponding residual voltage signal.
    Type: Grant
    Filed: April 26, 2015
    Date of Patent: November 17, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Zhiling Sui, Zhijun Chen, Zhihong Cheng, Yanping Zhang
  • Patent number: 9166585
    Abstract: A low power inverter circuit includes first and second transistors that receive an input signal at their gate terminals. The first and second transistors are connected by way of their source terminals to third and fourth transistors, respectively. The third and fourth transistors are connected in parallel with fifth and sixth transistors, respectively. The third and fourth transistors are continuously switched on, and the fifth and sixth transistors are controlled in such a way to reduce short circuit current flowing through the first and second transistors when the input signal transitions from one state to another.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: October 20, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Amit Roy, Zhihong Cheng, Amit Kumar Dey, Vijay Tayal, Chetan Verma
  • Patent number: 9148149
    Abstract: A latch circuit has a tri-state gate and a reverse tri-state gate that share the same complementary controls. The reverse tri-state gate locks an output of the tri-state gate when the tri-state gate is shut-off. The complementary control signals include a first undoped polysilicon strip. The output of the reverse tri-state gate may be coupled to the output of the tri-state gate via a second undoped polysilicon strip.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: September 29, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Zhihong Cheng, Peidong Wang
  • Publication number: 20150102839
    Abstract: A low power inverter circuit includes first and second transistors that receive an input signal at their gate terminals. The first and second transistors are connected by way of their source terminals to third and fourth transistors, respectively. The third and fourth transistors are connected in parallel with fifth and sixth transistors, respectively. The third and fourth transistors are continuously switched on, and the fifth and sixth transistors are controlled in such a way to reduce short circuit current flowing through the first and second transistors when the input signal transitions from one state to another.
    Type: Application
    Filed: August 20, 2014
    Publication date: April 16, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Amit Roy, Zhihong Cheng, Amit Kumar Dey, Vijay Tayal, Chetan Verma
  • Publication number: 20150091626
    Abstract: A state retention power gated cell includes a logic cell arranged in two or more rows. The logic cell has an active layer including at least a first well and a second well disposed in first and second rows, respectively. In a normal operation mode, the first well is powered with a first bias voltage, the second well is powered with a second bias voltage, the first power supply line is powered with VDDC, and the second power supply line is powered with VDD. In a standby mode, the first well preferably is powered down, the second well is powered with the second bias voltage, the first power supply line is powered with VDDC, and the second power supply line is powered down.
    Type: Application
    Filed: May 15, 2014
    Publication date: April 2, 2015
    Inventors: Miaolin Tan, Zhihong Cheng, Juan Fu, Peidong Wang, Yali Wang
  • Publication number: 20150084680
    Abstract: A state retention power gated (SRPG) cell includes a retention circuit coupled to a power gated circuit. The retention circuit stores state information of the power gated circuit before a low power period is started. A gated power supply coupled to the power gated circuit and to a first end of a power supply switch supplies a gated supply voltage to the power gated circuit during a non-low power period. A local power supply coupled to the retention circuit and to a second end of the power supply switch is coupled to the gated power supply in the non-low power period, and a non-gated power supply is coupled to the local power supply via an isolation element to isolate the non-gated power supply from the local power supply during the non-low power period, and to couple the non-gated power supply to the local power supply during the low power period.
    Type: Application
    Filed: February 26, 2014
    Publication date: March 26, 2015
    Inventors: Zhihong Cheng, Zhijun Chen, Huabin Du, Peidong Wang, Shayan Zhang
  • Patent number: 8987786
    Abstract: A state retention power gated cell includes a logic cell arranged in two or more rows. The logic cell has an active layer including at least a first well and a second well disposed in first and second rows, respectively. In a normal operation mode, the first well is powered with a first bias voltage, the second well is powered with a second bias voltage, the first power supply line is powered with VDDC, and the second power supply line is powered with VDD. In a standby mode, the first well preferably is powered down, the second well is powered with the second bias voltage, the first power supply line is powered with VDDC, and the second power supply line is powered down.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: March 24, 2015
    Assignee: Freescale Semiconductor, Inc
    Inventors: Miaolin Tan, Zhihong Cheng, Juan Fu, Peidong Wang, Yali Wang
  • Patent number: 8941429
    Abstract: In a master-slave flip-flop, the master latch has first and second three-state stages, and a first feedback stage. The slave latch has third and fourth three-state stages, and a second feedback stage. First and second clock switches having opposite phases are provided. The first clock switch is configured in one of the first and fourth three-state stages, and the other stage shares the first clock switch. The second clock switch is configured in one of the second and third three-state stages, and the other stage shares the second clock switch. The second three-state stage has an additional pair of complementary devices having signal paths connected in series with each other with both being gated by a data output of the slave latch. The flip-flop reduces the number of clock switches and clock switch power consumption.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: January 27, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Zhihong Cheng
  • Patent number: 8884669
    Abstract: An electronic device has a power control module for causing selected functional blocks to run in a low power mode of operation, while leaving other functional blocks supplied continuously with power. A power mode control distribution network includes serially connected chains of buffers in a distribution tree for distributing power mode control signals received at a common input end to respective output ends which are connected to respective functional blocks. In the low power mode of operation the power control module causes power to be supplied continuously to output buffers at the output ends of the chains while causing power supplied to other buffers to be reduced or cut-off. The output buffers include feedback paths for causing the states of the output buffers prior to the low power mode of operation to latch during the low power mode of operation.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: November 11, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xiaoxiang Geng, Zhihong Cheng, Huabin Du, Miaolin Tan
  • Publication number: 20140285236
    Abstract: A latch circuit has a tri-state gate and a reverse tri-state gate that share the same complementary controls. The reverse tri-state gate locks an output of the tri-state gate when the tri-state gate is shut-off. The complementary control signals include a first undoped polysilicon strip. The output of the reverse tri-state gate may be coupled to the output of the tri-state gate via a second undoped polysilicon strip.
    Type: Application
    Filed: February 7, 2014
    Publication date: September 25, 2014
    Inventors: Zhihong Cheng, Peidong Wang
  • Publication number: 20140240017
    Abstract: In a master-slave flip-flop, the master latch has first and second three-state stages, and a first feedback stage. The slave latch has third and fourth three-state stages, and a second feedback stage. First and second clock switches having opposite phases are provided. The first clock switch is configured in one of the first and fourth three-state stages, and the other stage shares the first clock switch. The second clock switch is configured in one of the second and third three-state stages, and the other stage shares the second clock switch. The second three-state stage has an additional pair of complementary devices having signal paths connected in series with each other with both being gated by a data output of the slave latch. The flip-flop reduces the number of clock switches and clock switch power consumption.
    Type: Application
    Filed: August 6, 2013
    Publication date: August 28, 2014
    Inventor: Zhihong Cheng
  • Publication number: 20140210523
    Abstract: An electronic device has a power control module for causing selected functional blocks to run in a low power mode of operation, while leaving other functional blocks supplied continuously with power. A power mode control distribution network includes serially connected chains of buffers in a distribution tree for distributing power mode control signals received at a common input end to respective output ends which are connected to respective functional blocks. In the low power mode of operation the power control module causes power to be supplied continuously to output buffers at the output ends of the chains while causing power supplied to other buffers to be reduced or cut-off. The output buffers include feedback paths for causing the states of the output buffers prior to the low power mode of operation to latch during the low power mode of operation.
    Type: Application
    Filed: August 12, 2013
    Publication date: July 31, 2014
    Inventors: Xiaoxiang Geng, Zhihong Cheng, Huabin Du, Miaolin Tan
  • Publication number: 20140096103
    Abstract: A system for optimizing the number of dies that can be fabricated on a wafer uses a die number optimization (DNO) routine to determine a maximum number of dies for a target die area (TDA), and generate an initial result list of die shapes that have the maximum number of dies for the TDA. Optionally, a die size optimization (DSO) routine can be executed to determine a list of die shapes having a maximum die area corresponding to the maximum number of dies, a first list of optimized die shapes having a maximum area utilization (AU) for a decreased TDA, and/or a second list of optimized die shapes having a minimum AU for an increased TDA. A candidate list (CL) of the various die shapes can be generated, and entries from the CL automatically selected and/or displayed to indicate proposed wafer layouts.
    Type: Application
    Filed: December 21, 2012
    Publication date: April 3, 2014
    Inventors: Peidong Wang, Zhijun Chen, Zhihong Cheng, Li Ying
  • Patent number: 8671381
    Abstract: A system for optimizing the number of dies that can be fabricated on a wafer uses a die number optimization (DNO) routine to determine a maximum number of dies for a target die area (TDA), and generate an initial result list of die shapes that have the maximum number of dies for the TDA. Optionally, a die size optimization (DSO) routine can be executed to determine a list of die shapes having a maximum die area corresponding to the maximum number of dies, a first list of optimized die shapes having a maximum area utilization (AU) for a decreased TDA, and/or a second list of optimized die shapes having a minimum AU for an increased TDA. A candidate list (CL) of the various die shapes can be generated, and entries from the CL automatically selected and/or displayed to indicate proposed wafer layouts.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: March 11, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Peidong Wang, Zhijun Chen, Zhihong Cheng, Li Ying
  • Patent number: 8650327
    Abstract: A processor with programmable virtual ports includes a plurality of in/out (IO) pins for transmitting and receiving data. The IO pins are grouped into a plurality of predefined ports, each of which has a physical address stored in one of a memory location of a memory map. The IO pins may be remapped to one or more virtual ports.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: February 11, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Shixiang Nie, Zhijun Chen, Zhihong Cheng
  • Patent number: 8569992
    Abstract: A stepper motor controller includes control circuitry with control outputs and individual driver pulse width modulation (PWM) circuitry with individual driver PWM outputs and modulation control inputs coupled to the control outputs. There is a group of individual drivers, each one having an input coupled to one of the PWM outputs, and an output coupled to an individual driver terminal of the controller. There is common driver PWM circuitry having a common driver PWM output. A common driver having a common driver input is coupled to the common driver PWM output and a common driver output is coupled to a common driver terminal of the controller. When a coil is connected between respective driver terminals and the common driver terminal, individual PWM driver currents are supplied to the coils from the individual driver terminals and a common PWM driver current is supplied to the coils from the common driver terminal.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: October 29, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Zhihong Cheng, Zhijun Chen, Shixiang Nie