Patents by Inventor Zhihong CHENG

Application number: 20140264724
Abstract: An integrated semiconductor device includes a substrate of a first conductivity type, a buried layer located over the substrate, an isolated region located over a first portion of the buried layer, and an isolation trench located around the isolated region. A punch-through structure is located around at least a portion of the isolation trench. The punch-through structure includes a second portion of the buried layer, a first region located over the second portion of the buried layer, the first region having a second conductivity type, and a second region located over the first region, the second region having the first conductivity type.
Type: Application
Filed: March 13, 2013
Issued: September 18, 2014
Assignee: Freescale Semiconductor, Inc.
Inventors: Xu Cheng, Daniel J. Blomberg, Zhihong Zhang, Jiang-Kai Zuo
Application number: 20140240017
Abstract: In a master-slave flip-flop, the master latch has first and second three-state stages, and a first feedback stage. The slave latch has third and fourth three-state stages, and a second feedback stage. First and second clock switches having opposite phases are provided. The first clock switch is configured in one of the first and fourth three-state stages, and the other stage shares the first clock switch. The second clock switch is configured in one of the second and third three-state stages, and the other stage shares the second clock switch. The second three-state stage has an additional pair of complementary devices having signal paths connected in series with each other with both being gated by a data output of the slave latch. The flip-flop reduces the number of clock switches and clock switch power consumption.
Type: Application
Filed: August 6, 2013
Issued: August 28, 2014
Inventor: Zhihong Cheng
Application number: 20140231745
Abstract: A light emitting device includes a p-side heterostructure having a short period superlattice (SPSL) formed of alternating layers of AlxhighGa1-xhighN doped with a p-type dopant and AlxlowGa1-xlowN doped with the p-type dopant, where xlow?xhigh?0.9. Each layer of the SPSL has a thickness of less than or equal to about six bi-layers of AlGaN.
Type: Application
Filed: September 14, 2012
Issued: August 21, 2014
Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
Inventors: John E. Northrup, Bowen Cheng, Christopher L. Chua, Thomas Wunderer, Noble M. Johnson, Zhihong Yang
Application number: 20140210523
Abstract: An electronic device has a power control module for causing selected functional blocks to run in a low power mode of operation, while leaving other functional blocks supplied continuously with power. A power mode control distribution network includes serially connected chains of buffers in a distribution tree for distributing power mode control signals received at a common input end to respective output ends which are connected to respective functional blocks. In the low power mode of operation the power control module causes power to be supplied continuously to output buffers at the output ends of the chains while causing power supplied to other buffers to be reduced or cut-off. The output buffers include feedback paths for causing the states of the output buffers prior to the low power mode of operation to latch during the low power mode of operation.
Type: Application
Filed: August 12, 2013
Issued: July 31, 2014
Inventors: Xiaoxiang Geng, Zhihong Cheng, Huabin Du, Miaolin Tan
Application number: 20140096103
Abstract: A system for optimizing the number of dies that can be fabricated on a wafer uses a die number optimization (DNO) routine to determine a maximum number of dies for a target die area (TDA), and generate an initial result list of die shapes that have the maximum number of dies for the TDA. Optionally, a die size optimization (DSO) routine can be executed to determine a list of die shapes having a maximum die area corresponding to the maximum number of dies, a first list of optimized die shapes having a maximum area utilization (AU) for a decreased TDA, and/or a second list of optimized die shapes having a minimum AU for an increased TDA. A candidate list (CL) of the various die shapes can be generated, and entries from the CL automatically selected and/or displayed to indicate proposed wafer layouts.
Type: Application
Filed: December 21, 2012
Issued: April 3, 2014
Inventors: Peidong Wang, Zhijun Chen, Zhihong Cheng, Li Ying
Patent number: 8671381
Abstract: A system for optimizing the number of dies that can be fabricated on a wafer uses a die number optimization (DNO) routine to determine a maximum number of dies for a target die area (TDA), and generate an initial result list of die shapes that have the maximum number of dies for the TDA. Optionally, a die size optimization (DSO) routine can be executed to determine a list of die shapes having a maximum die area corresponding to the maximum number of dies, a first list of optimized die shapes having a maximum area utilization (AU) for a decreased TDA, and/or a second list of optimized die shapes having a minimum AU for an increased TDA. A candidate list (CL) of the various die shapes can be generated, and entries from the CL automatically selected and/or displayed to indicate proposed wafer layouts.
Type: Grant
Filed: December 21, 2012
Issued: March 11, 2014
Assignee: Freescale Semiconductor, Inc.
Inventors: Peidong Wang, Zhijun Chen, Zhihong Cheng, Li Ying
Patent number: 8650327
Abstract: A processor with programmable virtual ports includes a plurality of in/out (IO) pins for transmitting and receiving data. The IO pins are grouped into a plurality of predefined ports, each of which has a physical address stored in one of a memory location of a memory map. The IO pins may be remapped to one or more virtual ports.
Type: Grant
Filed: September 6, 2012
Issued: February 11, 2014
Assignee: Freescale Semiconductor, Inc.
Inventors: Shixiang Nie, Zhijun Chen, Zhihong Cheng
Patent number: 8569992
Abstract: A stepper motor controller includes control circuitry with control outputs and individual driver pulse width modulation (PWM) circuitry with individual driver PWM outputs and modulation control inputs coupled to the control outputs. There is a group of individual drivers, each one having an input coupled to one of the PWM outputs, and an output coupled to an individual driver terminal of the controller. There is common driver PWM circuitry having a common driver PWM output. A common driver having a common driver input is coupled to the common driver PWM output and a common driver output is coupled to a common driver terminal of the controller. When a coil is connected between respective driver terminals and the common driver terminal, individual PWM driver currents are supplied to the coils from the individual driver terminals and a common PWM driver current is supplied to the coils from the common driver terminal.
Type: Grant
Filed: March 15, 2011
Issued: October 29, 2013
Assignee: Freescale Semiconductor, Inc.
Inventors: Zhihong Cheng, Zhijun Chen, Shixiang Nie
Application number: 20130147534
Abstract: In a master-slave D flip-flop, the master latch has first and second three-state stages and a feedback stage for positive feedback from the data outputs of the first and second three-state stages to the data input of the second three-state stage. The slave latch has third and fourth three-state stages and a feedback stage for positive feedback from the data outputs of the third and fourth three-state stages to the data input of the fourth three-state stage. Clock signals are applied from a clock signal source to the clock inputs of a clock switch element in one of the three-state stages whose clock signal is shared with another of the three-state stages, reducing the number of clock switches and clock switch power consumption. Data inverters also may be shared between a three-state stage of the master latch and a three-state stage of the slave latch.
Type: Application
Filed: September 6, 2012
Issued: June 13, 2013
Assignee: FREESCALE SEMICONDUCTOR, INC.
Inventors: Zhihong Cheng, Shixiang Nie, Yang Wang
Application number: 20130111099
Abstract: A processor with programmable virtual ports includes a plurality of in/out (IO) pins for transmitting and receiving data. The IO pins are grouped into a plurality of predefined ports, each of which has a physical address stored in one of a memory location of a memory map. The IO pins may be remapped to one or more virtual ports.
Type: Application
Filed: September 6, 2012
Issued: May 2, 2013
Assignee: FREESCALE SEMICONDUCTOR, INC
Inventors: Shixiang NIE, Zhijun Chen, Zhihong Cheng
Application number: 20110291604
Abstract: A stepper motor controller includes control circuitry with control outputs and individual driver pulse width modulation circuitry. The individual driver pulse width modulation circuitry has individual driver pulse width modulation outputs and modulation control inputs coupled to the respective control outputs. The controller has a group of individual drivers, where each one has an individual driver input coupled to a respective one of the individual driver pulse width modulation outputs, and an individual driver output coupled to an individual driver terminal of the controller. The stepper motor controller has common driver pulse width modulation circuitry having a common driver pulse width modulation output. There is also a common driver having a common driver input coupled to the common driver pulse width modulation output and a common driver output coupled to a common driver terminal of the controller.
Type: Application
Filed: March 15, 2011
Issued: December 1, 2011
Assignee: FREESCALE SEMICONDUCTOR, INC.
Inventors: Zhihong CHENG, Zhijun CHEN, Shixiang NIE