Metal word lines for three dimensional memory devices
A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of insulating first material and sacrificial second material different from the first material over a major surface of the substrate, forming a front side opening in the stack, forming at least one charge storage region in the front side opening and forming a tunnel dielectric layer over the at least one charge storage region in front side opening. The method also includes forming a semiconductor channel over the tunnel dielectric layer in the front side opening, forming a back side opening in the stack and selectively removing at least portions of the second material layers to form back side recesses between adjacent first material layers. The method also includes forming electrically conductive clam shaped nucleation liner regions in the back side recesses and selectively forming ruthenium control gate electrodes through the back side opening in the respective electrically conductive clam shaped nucleation liner regions.
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The present disclosure relates generally to the field of semiconductor devices and specifically to three dimensional vertical NAND strings and other three dimensional devices and methods of making thereof.
BACKGROUNDThree dimensional vertical NAND strings are disclosed in an article by T. Endoh, et. al., titled “Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEDM Proc. (2001) 33-36.
SUMMARYAn embodiment relates to a method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of insulating first material and sacrificial second material different from the first material over a major surface of the substrate, forming a front side opening in the stack, forming at least one charge storage region in the front side opening and forming a tunnel dielectric layer over the at least one charge storage region in front side opening. The method also includes forming a semiconductor channel over the tunnel dielectric layer in the front side opening, forming a back side opening in the stack and selectively removing at least portions of the second material layers to form back side recesses between adjacent first material layers. The method also includes forming electrically conductive clam shaped nucleation liner regions in the back side recesses and selectively forming ruthenium control gate electrodes through the back side opening in the respective electrically conductive clam shaped nucleation liner regions.
Another embodiment relates to a monolithic three dimensional NAND string including a semiconductor channel. At least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate. The NAND string also includes a plurality of ruthenium control gate electrodes extending substantially parallel to the major surface of the substrate. The plurality of control gate electrodes include at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level. The NAND string also includes electrically conductive clam shaped nucleation liner regions located in contact with the plurality of ruthenium control gate electrodes, a blocking dielectric located in contact with the electrically conductive clam shaped nucleation liner regions, at least one charge storage region located in contact with the blocking dielectric and a tunnel dielectric located between the at least one charge storage region and the semiconductor channel.
The present inventors have realized that selectively deposited ruthenium control gate electrodes of three dimensional NAND string memory devices are unexpectedly advantageous over conventional tungsten control gate electrodes and word lines. The present inventors have further realized that excess control gate material in the back side openings may generate undesirable stress on the NAND device and underlying substrate, leading to warping of the substrate. However, the present inventors have also realized that when using an atomic layer deposition process for the deposition of ruthenium, the ruthenium can be selectively deposited inside recesses in the NAND stack to form control gate electrodes/word lines without depositing ruthenium in the back side openings. As discussed in more detail below, the ruthenium may be selectively deposited in the recesses by first forming a nucleation liner that is only located in the recesses and not in the back side opening. The liner may be thinner than the control gate electrodes, which results in a lower metal volume in the back side opening. Furthermore, the selective ruthenium deposition in the recesses also avoids the ruthenium etching from the back side opening which increases the process throughput and decreases the process cost.
A monolithic three dimensional memory array is one in which multiple memory levels are formed above a single substrate, such as a semiconductor wafer, with no intervening substrates. The term “monolithic” means that layers of each level of the array are directly deposited on the layers of each underlying level of the array. In contrast, two dimensional arrays may be formed separately and then packaged together to form a non-monolithic memory device. For example, non-monolithic stacked memories have been constructed by forming memory levels on separate substrates and adhering the memory levels atop each other, as in Leedy, U.S. Pat. No. 5,915,167, titled “Three Dimensional Structure Memory.” The substrates may be thinned or removed from the memory levels before bonding, but as the memory levels are initially formed over separate substrates, such memories are not true monolithic three dimensional memory arrays.
In some embodiments, the monolithic three dimensional NAND string 150 comprises a semiconductor channel 1 having at least one end portion extending substantially perpendicular to a major surface 100a of a substrate 100, as shown in
Alternatively, the semiconductor channel 1 may have a U-shaped pipe shape, as shown in
The semiconductor channel 1 may be a cylinder containing an insulating material 2, such as SiO2 located in the middle region (e.g., core region), as shown in
A first source electrode (or source line) 102a is located in the first dielectric filled slit trench 84a and a second source electrode 102b is located in the second dielectric filled slit trench 84b in each block 400, as shown in
As discussed above, each NAND string 150 contains a NAND memory cell region in the memory device levels 70 which includes the semiconductor channel 1 which contains a portion 1a which extends substantially perpendicular to the major surface 100a of the substrate 100. A bottom portion 1c of the channel 1 is located in or over the major surface 100a of the substrate 100, and extends toward the doped source region 1d substantially parallel to the major surface of the substrate. A drain region 1e is located in the upper part of the channel portion 1a in contact with a respective drain line 103, as shown in
The device contains a plurality of control gate electrodes 3 that extend substantially parallel to the major surface 100a of the substrate 100 in the memory device levels 70 from the memory region 200 to the stepped word line contact region 300. The portions of the control gate electrodes 3 which extend into region 300 may be referred to as “word lines” herein. The drain electrode (e.g., bit line) 202 electrically contacts an upper portion of the semiconductor channel 1 via drain lines 103.
Furthermore, each NAND string 150 contains at least one memory film 13 which is located adjacent to the semiconductor channel 1 (e.g., at least next to portion 1a of the channel) in the memory device levels 70, as shown in
As used herein a “clam” shape is a side cross sectional shape configured similar to an English letter “C”. A clam shape has two segments which extend substantially parallel to each other and to the major surface 100a of the substrate 100. The two segments are connected to each other by a third segment which extends substantially perpendicular to the first two segments and the surface 100a. Each of the three segments may have a straight shape (e.g., a rectangle side cross sectional shape) or a somewhat curved shape (e.g., rising and falling with the curvature of the underlying topography). The term substantially parallel includes exactly parallel segments as well as segments which deviate by 20 degrees or less from the exact parallel configuration. The term substantially perpendicular includes exactly perpendicular segments as well as segments which deviate by 20 degrees or less from the exact perpendicular configuration. The clam shape preferably contains an opening bounded by the three segments and having a fourth side open.
Each part of the memory film 13, such as the tunnel dielectric 11, the charge storage region 9, and/or the blocking layer 7 may be comprised of one or more layers (e.g., one or more dielectric layers) made of different materials. The charge storage region 9 may comprise a plurality of discrete floating gates or a continuous charge storage dielectric layer.
As shown in
The substrate 100 can be any semiconducting substrate known in the art, such as monocrystalline silicon, IV-IV compounds such as silicon-germanium or silicon-germanium-carbon, III-V compounds, II-VI compounds, epitaxial layers over such substrates, or any other semiconducting or non-semiconducting material, such as silicon oxide, glass, plastic, metal or ceramic substrate. The substrate 100 may include integrated circuits fabricated thereon, such as driver circuits for a memory device.
Any suitable semiconductor materials can be used for semiconductor channel 1, for example silicon, germanium, silicon germanium, or other compound semiconductor materials, such as III-V, II-VI, or conductive or semiconductive oxides, etc. The semiconductor material may be amorphous, polycrystalline or single crystal. The semiconductor channel material may be formed by any suitable deposition methods. For example, in one embodiment, the semiconductor channel material is deposited by low pressure chemical vapor deposition (LPCVD). In some other embodiments, the semiconductor channel material may be a recrystallized polycrystalline semiconductor material formed by recrystallizing an initially deposited amorphous semiconductor material.
The insulating fill material 2 may comprise any electrically insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or other high-k insulating materials. Alternatively, the core fill material 2 may be omitted and the channel 1 may comprise a solid silicon rod, as shown in
The monolithic three dimensional NAND string further comprise a plurality of ruthenium control gate electrodes 3, as shown in
A blocking dielectric 7 is located adjacent to the control gate(s) 3 and may surround the control gate electrodes 3, as shown in
The monolithic three dimensional NAND string also comprise a charge storage region 9. The charge storage region 9 may comprise one or more continuous layers which extend the entire length of the memory cell portion of the NAND string, as shown in
Alternatively, the charge storage region may comprise a plurality of discrete charge storage regions 9, as shown in
The tunnel dielectric 11 of the monolithic three dimensional NAND string is located between charge storage region 9 and the semiconductor channel 1.
The blocking dielectric 7 and the tunnel dielectric 11 may be independently selected from any one or more same or different electrically insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, or other insulating materials. The blocking dielectric 7 and/or the tunnel dielectric 11 may include multiple layers of silicon oxide, silicon nitride and/or silicon oxynitride (e.g., ONO layers) and/or high-k materials such as aluminum oxide, hafnium oxide or combinations thereof. For example, the blocking dielectric 7 may comprise at least one inner blocking dielectric layer (e.g. made of silicon oxide) adjacent to the charge storage region 9 and an outer metal oxide layer (e.g., aluminum oxide) adjacent to the ruthenium control gate 3. For example, the blocking dielectric 7 may comprise a plurality of clam shaped regions 72, such as metal oxide regions, and the plurality of ruthenium control gate electrodes 3 are located in respective openings in respective metal oxide clam shaped regions 72, as shown in
The blocking dielectric 7, charge storage region(s) 9 and the tunnel dielectric 11 together is also referred to herein as a memory film 13, as shown in
In summary, at least the portion 1a of the semiconductor channel 1 comprises cylinder shaped channel. The tunnel dielectric 11 comprises a cylinder which surrounds the semiconductor channel 1 (e.g., at least portion 1a of channel 1). As described above, the tunnel dielectric 11 may comprise a single insulating layer or a stack of a plurality of insulating layers comprised of different materials. The at least one charge storage region 9 comprises a cylinder shaped plurality of vertically spaced apart floating gates or a cylinder shaped dielectric charge storage layer which surrounds the tunnel dielectric 11. The blocking dielectric 7 comprises a cylinder which surrounds the at least one charge storage region 9. As described above, the blocking dielectric may comprise a single insulating layer or a stack of a plurality of insulating layers comprised of different materials. The control gate electrodes 3 surround the blocking dielectric 7.
If desired, a top insulating layer 19t may have a greater thickness and/or a different composition from the other insulating layers 19. For example, the top insulating layer 19t may comprise a cover silicon oxide layer made using a TEOS source while the remaining layers 19 may comprise thinner silicon oxide layers may using a different source. The method includes forming front side openings 81 by RIE or another suitable etching method. The stack 120 includes a plurality of front side openings 81 (e.g. a plurality of cylindrical memory holes shown in
As shown in
Alternatively, the blocking dielectric 7 and/or the charge storage region(s) 9 may be formed from the back side through the back side opening 84 and back side recesses as shown in
If desired, an optional cover layer 73, such as an amorphous silicon layer, is formed over the tunnel dielectric portion of the memory film 13, as shown in
Then, as shown in
Then, as shown in
Then, the ruthenium control gate electrodes 3, and optionally the blocking dielectric 7 and/or the charge storage region(s) 9 may be formed by a replacement process through a back side opening 84, as shown in
Then, at least a portion of the sacrificial second material layers 121 are selectively removed through the back side openings 84 selectively etching the silicon nitride layers 121 to form back side recesses 182 between the first material layers 19, as shown in
Alternatively, the blocking dielectric 7 may be formed from the back side in the back side recesses prior to the control gate electrodes 3. In this embodiment, forming the blocking dielectric layer 7 comprises forming the blocking dielectric layer 7 in the back side opening 84 and in the back side recesses 182.
If desired, the at least one charge storage region 9 may be formed through either the front side opening 81 or the back side opening 84. Thus, the step of forming the at least one charge storage region 9 comprises at least one of forming the at least one charge storage region 9 prior to forming the blocking dielectric 7 in the back side opening 84 or forming the at least one charge storage region 9 over the blocking dielectric 7 in the front side opening 81 or over the sidewall in the front side opening 81 (if the blocking dielectric 7 is formed through the back side opening 84).
Ruthenium control gate electrodes 3 may then formed in the back side recesses 182 through the back side openings 84, as shown in
Next, as illustrated in
Then, as illustrated in
As illustrated in
Next, as illustrated in
The ruthenium control gate material is may be deposited by atomic layer deposition (ALD). The ruthenium material may be formed by supplying a volatile ruthenium precursor, such as RuO4. One or more RuO2 monolayers may be formed using atomic layer deposition. The one or more RuO2 monolayers may be exposed to a reducing atmosphere to fully or partially reduce the deposited one or more RuO2 monolayers to one or more Ru monolayers. The RuO2 deposition and Ru reducing steps (i.e., 1 ALD cycle) may be repeated multiple times to form the plurality of control gate electrodes 3. A hydrogen based forming gas, such as 4% hydrogen and 96% nitrogen, may be supplied as the reducing atmosphere for the ruthenium oxide. The atomic layer deposition may be performed by cycling, such as with more than 25 cycles, such as 25-40 cycles, to form continuous strips of Ru. In an embodiment, the ALD process optionally further includes annealing the ruthenium layer using rapid thermal annealing at a temperature between 900 and 1000 C.
Next, an insulating layer 205, such as a silicon oxide layer, is formed on sidewalls and bottom of the back side trenches 84, as shown in
The source electrode 102 is then formed in the back side trench 84 in contact with the source region 1d in the p-well 110 in the substrate 100, as shown in
In an embodiment, at least one charge storage region 9 comprises a plurality of floating gates or a charge storage dielectric layer formed in the front side opening 81. The semiconductor channel 1 comprises polysilicon or amorphous silicon. The blocking dielectric 7 comprises a metal oxide (e.g., aluminum oxide) blocking dielectric. The first material layers 19 comprise silicon oxide layers. The second material layers 121 comprise silicon nitride or polysilicon layers.
Without wishing to be bound by a particular theory, the mechanism of the selective ruthenium deposition process of
ALD is a surface sensitive deposition process, i.e., the film growth is strongly dependent on the underlying surface characteristics. Without wishing to be bound by a particular theory, it is conjectured that the difference in nucleation is a function of the hydrophobicity of the surfaces, which results in different contact angles for different surfaces. That is, the more hydrophilic the surface, the lower contact angle. Further, a lower contact angle results in a thinner film region. In one embodiment, the conductive nucleation liner regions 42 (e.g., tungsten, tungsten nitride, titanium nitride, ruthenium nitride, tantalum nitride, etc.) can be more hydrophobic than the surfaces of the dielectric layers 19 or 7.
In case the insulating layers 19 comprise silicon oxide, it is believed that less than 25 cycles of RuO2 deposition steps and ruthenium reduction steps results in negligibly small deposition of ruthenium on the surfaces of the insulating layers 19, while continuous portions of ruthenium can be formed on more hydrophobic surfaces such as the nucleation liner surfaces. In one embodiment, the nucleation liner can be a material that is more hydrophobic than silicon oxide layers 19 or aluminum oxide blocking dielectric 7. With less than 25 cycles of the ALD process, ruthenium does not form any contiguous material portion on surfaces of the insulating layer 19, and grows only from the liner regions 42.
Next, as illustrated in
In an embodiment, horizontal portions of the electrically conductive clam shaped nucleation liner regions 42 have a smaller thickness in a direction perpendicular to the major surface 100a of the substrate 100 than the ruthenium control gate electrodes 3. In an embodiment, the electrically conductive clam shaped nucleation liner regions 42 have a thickness of 2 to 5 nm, the ruthenium control gate electrodes 3 have a thickness of 10 to 25 nm in a direction perpendicular to the major surface 100a of the substrate 100 and the back side recesses 182 have thickness of 15 to 30 nm in the direction perpendicular to the major surface 100a of the substrate 100 before the liner regions 42 are formed. In an embodiment, the ruthenium control gate electrodes 3 are selectively formed by atomic layer deposition for a first number of atomic layer deposition cycles. The first number of atomic layer deposition cycles is greater than or equal to a number of cycles required to completely fill recesses in the electrically conductive clam shaped nucleation liner regions 42 with ruthenium. The first number of cycles is also less than a number of cycles at which ruthenium incubation delay on the dielectric surfaces (e.g., edges of first material layers 19 or blocking dielectric 7 exposed in the back side opening 84) after which ruthenium deposits on the dielectric surfaces.
The nucleation liner regions 42 are more continuous in the recesses 182 towards the bottom of the trench 84, as shown in
Although the foregoing refers to particular preferred embodiments, it will be understood that the disclosure is not so limited. It will occur to those of ordinary skill in the art that various modifications may be made to the disclosed embodiments and that such modifications are intended to be within the scope of the disclosure. All of the publications, patent applications and patents cited herein are incorporated herein by reference in their entirety.
Claims
1. A method of making a monolithic three dimensional NAND string, comprising:
- forming a stack of alternating layers of insulating first material and a sacrificial second material different from the first material over a major surface of a substrate;
- forming a front side opening in the stack;
- forming at least one charge storage region in the front side opening;
- forming a tunnel dielectric layer over the at least one charge storage region in the front side opening;
- forming a semiconductor channel over the tunnel dielectric layer in the front side opening;
- forming a back side opening in the stack;
- selectively removing at least portions of the second material layers to form back side recesses between adjacent first material layers;
- forming an electrically conductive nucleation layer in the back side opening and in the back side recesses;
- removing vertical portions of the electrically conductive nucleation layer from inside the back side opening while not removing portions of the electrically conductive nucleation layer located within the backside recesses, wherein remaining portions of the electrically conductive nucleation layer constitute electrically conductive clam shaped nucleation liner regions that are located entirely within the back side recesses; and
- selectively forming ruthenium control gate electrodes through the back side opening in the respective electrically conductive clam shaped nucleation liner regions after removal of the vertical portions of the electrically conductive nucleation layer from inside the back side opening by depositing ruthenium directly on the electrically conductive claim shaped nucleation liner regions while ruthenium is not deposited over sidewalls of the first material layers within the back side opening.
2. The method of claim 1, further comprising forming a blocking dielectric between the control gate electrodes and the at least one charge storage region.
3. The method of claim 2, wherein:
- the step of selectively removing at least portions of the second material layers comprises selectively etching the second material layers through the back side opening to form the back side recesses;
- the step of forming the blocking dielectric comprises forming the blocking dielectric in the front side opening over the at least one charge storage region, or through the back side opening in the back side recesses on exposed portions of the at least one charge storage region; and
- the step of selectively forming the ruthenium control gate electrodes comprises selectively forming ruthenium regions on respective the electrically conductive clam shaped nucleation liner regions without forming ruthenium on sidewalls of the first material layers exposed in the back side opening in the stack.
4. The method of claim 3, wherein sidewalls of the first material layers are physically exposed in the back side opening after removing the vertical portions of the nucleation liner from inside the back side opening.
5. The method of claim 4, wherein selectively forming the ruthenium control gate electrodes comprises selectively forming the ruthenium control gate electrodes by atomic layer deposition.
6. The method of claim 5, wherein:
- the electrically conductive clam shaped nucleation liner regions comprise at least one of tungsten, tungsten nitride, titanium nitride, ruthenium nitride or tantalum nitride; and
- the first material layers comprise silicon oxide layers.
7. The method of claim 6, wherein horizontal portions of the electrically conductive clam shaped nucleation liner regions have a smaller thickness in a direction perpendicular to the major surface of the substrate than the ruthenium control gate electrodes.
8. The method of claim 6, wherein:
- the electrically conductive clam shaped nucleation liner regions have a thickness of 2 to 5 nm;
- the ruthenium control gate electrodes have a thickness of 10 to 25 nm in a direction perpendicular to the major surface of the substrate; and
- the back side recesses have thickness of 15 to 30 nm in the direction perpendicular to the major surface of the substrate.
9. The method of claim 6, wherein a thickness of the ruthenium control gate electrodes in the direction perpendicular to the major surface of the substrate is less than twice a thickness at which onset of growth of ruthenium begins on the first material layers exposed in the back side opening or on the blocking dielectric if the blocking dielectric is exposed in the back side opening.
10. The method of claim 6, wherein:
- the ruthenium control gate electrodes are selectively formed by atomic layer deposition for a first number of atomic layer deposition cycles;
- the first number of atomic layer deposition cycles is greater than or equal to a number of cycles required to completely fill recesses in the electrically conductive clam shaped nucleation liner regions with ruthenium; and
- the first number of cycles is less than a number of cycles at which ruthenium incubation delay on the first material layers ends, and at which ruthenium deposits on the first material layers.
11. The method of claim 5, wherein selectively forming the ruthenium control gate electrodes by atomic layer deposition comprises:
- (a) using a RuO4 precursor to deposit one or more RuO2 monolayers using atomic layer deposition;
- (b) exposing the one or more RuO2 monolayers to a reducing atmosphere to reduce the deposited one or more RuO2 monolayers to one or more Ru monolayers; and
- (c) repeating steps (a) and (b) a plurality of times to selectively form the ruthenium control gate electrodes.
12. The method of claim 2, wherein:
- the at least one charge storage region comprises a plurality of floating gates or a charge storage dielectric layer formed in the front side opening;
- the semiconductor channel comprises polysilicon or amorphous silicon;
- the blocking dielectric comprises a metal oxide blocking dielectric;
- the first material layers comprise silicon oxide layers; and
- the second material layers comprise silicon nitride or polysilicon layers.
13. The method of claim 1, further comprising:
- forming a source region of the NAND string in or over the substrate through the back side opening;
- forming an insulating layer in the back side opening;
- removing a bottom portion of the insulating layer to expose the source region; and
- forming a source line in the back side opening in contact with the source region.
14. The method of claim 13, wherein:
- the substrate comprises a silicon substrate;
- the monolithic three dimensional NAND string is located in an array of monolithic three dimensional NAND strings over the silicon substrate;
- the control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level;
- at least one memory cell in the first device level of the three dimensional array of NAND strings is located over another memory cell in the second device level of the three dimensional array of NAND strings; and
- the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon.
15. The method of claim 1, wherein the at least one charge storage region is formed in the front side opening prior to selectively removing at least portions of the second material layers.
16. The method of claim 1, wherein the tunnel dielectric layer is formed after formation of the at least one charge storage region and directly on a sidewall of the at least one charge storage region.
17. The method of claim 1, wherein the semiconductor channel is formed directly on the tunneling dielectric layer prior to selectively removing at least portions of the second material layers.
18. The method of claim 1, wherein the electrically conductive nucleation layer includes a material selected from tungsten nitride, titanium nitride, ruthenium nitride, and tantalum nitride.
19. The method of claim 1, wherein the electrically conductive nucleation layer includes a tungsten layer, and the ruthenium control gate electrodes are formed by nucleating and depositing ruthenium on surfaces of the tungsten layer.
20. The method of claim 1, wherein each of the electrically conductive clam shaped nucleation liner region is separated from each other in a direction perpendicular to the major surface of the substrate by the first material layers.
21. The method of claim 1, further comprising:
- forming a blocking dielectric in the front side opening; and
- forming a memory film including the at least one charge storage region is formed directly on the blocking dielectric in the front opening.
22. The method of claim 21, wherein at least one of the electrically conductive clam shaped nucleation liner regions includes a vertical portion that physically contacts the blocking dielectric, an upper horizontal portion that physically contacts an overlying first material layer, and an lower horizontal portion that physically contacts an underlying first material layer.
23. The method of claim 1, further comprising forming a backside blocking dielectric layer in the backside recesses and in the back side opening prior to forming the electrically conductive nucleation layer, wherein sidewalls of the backside blocking dielectric layer are physically exposed after removing the vertical portions of the electrically conductive nucleation layer from inside the back side opening.
24. The method of claim 23, wherein at least one of the electrically conductive clam shaped nucleation liner regions includes a vertical portion that physically contacts a vertical portion of the backside blocking dielectric layer, an upper horizontal portion that physically contacts an overlying horizontal portion of the backside blocking dielectric layer, and an lower horizontal portion that physically contacts an underlying horizontal portion of the backside blocking dielectric layer.
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Type: Grant
Filed: Nov 25, 2014
Date of Patent: Feb 14, 2017
Patent Publication Number: 20160148945
Assignee: SANDISK TECHNOLOGIES LLC (Plano, TX)
Inventors: Rahul Sharangpani (Fremont, CA), Raghuveer S. Makala (Campbell, CA), Senaka Krishna Kanakamedala (Milpitas, CA), Sateesh Koka (Milpitas, CA), Yao-Sheng Lee (Tampa, FL), George Matamis (Danville, CA)
Primary Examiner: Robert Carpenter
Application Number: 14/553,207
International Classification: H01L 27/115 (20060101); H01L 29/788 (20060101); H01L 21/28 (20060101); H01L 29/49 (20060101); H01L 21/285 (20060101); H01L 21/02 (20060101);