Abstract: A negative electron affinity device has acceptor dopant concentration increased proximate the emitter face of the III-V semiconductor layer and within the depletion zone effected by an overlying CsO negative electron affinity coating. Methods to accomplish dopant concentration include diffusion, ion implantation and doping during crystal growth.
Type:
Grant
Filed:
June 18, 1993
Date of Patent:
October 11, 1994
Assignee:
ITT Corporation
Inventors:
Robert J. Field, Michael E. Givens, Mary A. Whisenant
Abstract: Semiconductor layers having a p-n junction are formed over the surface of a semiconductor substrate except for a partial surface. On the partial surface of the semiconductor substrate, a region of an electrode to be connected with an external terminal is formed with an insulating film interposed between the same. Bonding connection with the external terminal is performed on the region for connection, to reduce mechanical damage of the semiconductor layers having the p-n junction while improving photoelectric conversion efficiency and reliability of the device.
Abstract: Present invention is to provide a process for producing an opto-electronic integrated circuit comprising a field effect transistor as an electronic device and a photo-diode as an optical device both formed on an InP substrate,the field effect transistor comprising a high electron mobility transistor having:a GaInAs layer epitaxially grown in the InP substrate in a preset region thereof, a n-AlInAs layer epitaxially grown on the GaInAs layer, a gate electrode formed on the AlInAs layer, and a source electrode and a drain electrode formed on the AlInAs layer with the gate electrode therebetween, andthe photo-diode comprising a PIN photo-diode having:the GaInAs layer epitaxially grown on the InP substrate near the region of the field effect transistor simultaneously with the growth of that of the field effect transistor, the n-AlInAs layer epitaxially grown on the GaInAs layer simultaneously with the growth of that of the field effect transistor, a n-InP layer epitaxially grown on the n-AlInAs layer, an undoped
Abstract: A semiconductor photodetector, such as a PIN photodiode and an avalanche photodiode, comprising an InP substrate, a first InP layer, a GaInAs or GaInAsP light absorbing layer, and a second InP layer. All of the layers are successively grown by a vapor phase epitaxial process wherein the lattice constant of the GaInAs (GaInAsP) layer is larger than that of the InP layer at room temperature. The photodetector has a low dark current.