Abstract: In a method for manufacturing an LDD-structured MOS transistor and a bipolar transistor, a gate insulating layer is formed on a MOS transistor region and a bipolar transistor region. Then, a gate electrode is formed on the MOS transistor region. Then, an insulating layer is formed on the entire surface, and as etched back by a reactive ion etching process to form a sidewall spacer. The MOS transistor region and the bipolar transistor region are etched by a wet etching process using the gate electrode and its sidewall spacer as a mask.

Abstract: A method for forming a diode for use within an integrated circuit, and a diode formed through the method. There is first provided a semiconductor substrate. There is then formed over the semiconductor substrate a dielectric layer. There is then formed upon the dielectric layer a first polysilicon layer, where the first polysilicon layer has a first dopant polarity and a first dopant concentration. There is then formed at least in part overlapping and at least in part in contact with the first polysilicon layer a second polysilicon layer. The second polysilicon layer has a second dopant polarity and a second dopant concentration, where the second dopant polarity is opposite to the first dopant polarity. A first portion of the second polysilicon layer overlapping and in contact within a first portion of the first polysilicon layer forms a junction diode.

Abstract: A method for forming electrodes on a semiconductor includes introducing at least one reactive oxidizing gas selected from the group consisting of ozone, atomic oxygen, nitrogen dioxide, oxygen ion and oxygen plasma to an oxide semiconductor surface and depositing electrode material on the oxide semiconductor surface without exposing the surface to the outside atmosphere.

Abstract: A method for making a nonvolatile memory device having a field effect transistor for storing information, and a Schottky diode in series with the field effect transistor. The field effect transistor includes source and drain regions in a semiconductor substrate, with a channel region interposed between them and a gate electrode above the channel region. A ferroelectric gate film is sandwiched between the channel region and the gate electrode. In the method, a conductive barrier meterial is deposited in contact with the source region of the field effect transistor to make the Schottky diode. In reading information from the memory device, voltage is applied to a serial circuit consisting of the field effect transistor and the Schottky diode to turn the Schottky diode on.

Abstract: A method of producing a semiconductor device including a Schottky barrier diode (SBD) comprising the steps of: selectively forming an insulating layer having a first contact hole and a second contact hole, on a (100) silicon semiconductor substrate; selectively forming a polysilicon layer extending from the first contact hole to the second contact hole, the polysilicon layer having a viahole within the first contact hole for selectively exposing the silicon semiconductor substrate; and selectively depositing a refractory metal (tungsten or molybdenum) layer on the polysilicon layer and an exposed portion of the substrate within the viahole by a selective CVD process, so that the SBD is formed between the exposed portion and the metal layer. The refractory metal layer is formed on the silicon of the exposed portion of the substrate and the polysilicon layer and is not formed on the insulating layer, and thus it is unnecessary to perform a photolithography process for patterning the refractory metal layer.

Abstract: A Schottky diode circuit 20 is formed on a semiconductor layer 24. A conductive contact 36 on the surface of the semiconductor layer 24 forms a Schottky barrier 40 at the junction of the conductive contact 36 and the semiconductor layer 24. A guard ring 26 in the semiconductor layer 24 is adjacent to the Schottky barrier 40 and is separated from the conductive contact 36 by a portion of the semiconductor layer 24. No direct electrical path exists between the guard ring 26 and the conductive contact 36.

Abstract: Group II-VI thin film transistors, a method of making same and a monolithic device containing a detector array as well as transistors coupled thereto wherein, according to a first embodiment, there is provided a group II-VI insulating substrate, a doped layer of a group II-VI semiconductor material disposed over the substrate, an insulating gate region disposed over the doped layer, a pair of spaced contacts on the doped layer providing source and drain contacts, a gate contact disposed over the insulating gate region, an insulating layer disposed over exposed regions of the substrate, doped layer, insulating gate region and contacts and metallization disposed on the insulating layer and extending through the insulating layer to the contacts. The thickness of the doped layer is less than the maximum depletion region thickness thereof.

Abstract: A process for fabricating gold/gallium arsenide structures, in situ, on molecular beam epitaxially grown gallium arsenide. The resulting interface proves to be Ohmic, an unexpected result which is interpreted in terms of increased electrode interdiffusion. More importantly, the present invention surprisingly permits the fabrication of Ohmic contacts in a III-V semiconductor material at room temperature. Although it may be desireable to heat the Ohmic contact to a temperature of, for example, 200 degrees Centigrade if one wishes to further decrease the resistance of the contact, such low temperature annealing is much less likely to have any deleterious affect on the underlying substrate. The use of the term "in situ" herein, contemplates continuously maintaining an ultra-high vacuum, that is a vacuum which is at least 10.sup.-8 Torr, until after the metallization has been completed.

Abstract: A method of producing a field effect transistor includes depositing a first insulating film and a refractory metal on a semiconductor substrate, forming a first aperture penetrating the first insulating film and the refractory metal film to provide a gate electrode production region, depositing a second insulating film on the refractory metal film, etching the second insulating film in a direction perpendicular to the surface of the substrate leaving portions of the second insulating film on opposite side walls of the first aperture to form a second aperture, defining a gate length, depositing a gate metal, and patterning the gate metal layer, the first insulating film, and the refractory metal film in a prescribed width to form a T-shaped gate structure. During etching the second insulating film, since the refractory metal film serves as a etch stopping layer, the first insulating film is not etched and its thickness remains as deposited.

Abstract: An improved Schottky diode structure (4) is formed by retrograde diffusing an N.sup.+ concentration of relatively fast diffusing atoms, preferably Phosphorus atoms, to form a localized diode NWell (6) as the diode substrate for the diode. A buried diode layer (5) formed of relatively slow diffusing N type atoms, preferably Antimony atoms, underlies the diode NWell and electrically couples the diode junction (7) to the diode ohmic contact (9). A diode ohmic contact region (31) underlies the ohmic contact, further coupling the diode junction to the ohmic contact. Preferably, the diode junction is a Platinum-Silicide junction.

Abstract: A method for manufacturing a semiconductor device with a Schottky electrode includes the steps of subjecting the surface of a GaAs substrate to a sputtering etching process in a sputtering processing chamber of a sputtering device; and depositing Schottky electrode material by sputtering on the surface of the substrate to form a Schottky electrode in the processing chamber without exposing the substrate to the atmosphere.

Abstract: A Schottky diode is formed with a layer of intrinsic polysilicon separating a metal silicide layer from an n conductivity type active region. This structure avoids the necessity for a process step which opens a window in the intrinsic polysilicon layer and reduces the portion of surface area needed for formation of a Schottky diode, compared to previous devices. The Schottky diode can be formed as part of an overall process for forming an integrated circuit and can be positioned in parallel across the collector/base junction of a bipolar transistor to form a Schottky barrier diode-clamped transistor.

Abstract: A method of fabricating an integrated circuit comprises providing a heavily compensated substrate having a source region, a drain region and a third region, each of a first conductivity type, and introducing dopant of a second conductivity type into the substrate to surround the third region.

Abstract: A semiconductor device such as a Schottky-barrier rectifier diode is disclosed which has a barrier electrode formed on a semiconductor substrate of gallium arsenide or the like. Formed around the barrier electrode is an annular resistive layer, typically of titanium oxide, creating a Schottky barrier at its interface with the semiconductor substrate. The resistive layer has a sheet resistance of more than 10 kilohms per square. In order to prevent preliminary breakdowns from taking place at the peripheral part of the resistive layer before final breakdown of the device, the sheet resistance of the resistive layer is made higher as it extends away from the barrier electrode. For the ease of manufacture, the resistive layer can be divided into two or more annular regions of distinctly different sheet resistances.

Abstract: The method of manufacturing the metal-semiconductor junction in accordance with the present invention includes the step of forming a 2.times.2 surface superstructure in an ultrahigh vacuum by removing an oxide layer by means of a heat cleaning at temperatures not lower than 600.degree. C. while irradiating a (111) A or (111) B surface of a zincblende-type III-V compound semiconductor substrate with a beam of a group V element, the step of cooling the substrate down to room temperature while maintaining the surface superstructure and the step of depositing a metal on the surface.

Abstract: A semiconductor device includes a semiconductor body and a metal contact forming a Schottky barrier with said body, the metal contact including a layer of nickel disposed on the semiconductor body, an aluminum layer disposed on the nickel layer, and a nickel aluminum alloy disposed at the interface of the layers. The alloy is formed by heating the metal layers.

Abstract: A method and structures are described for fabricating junctions having metal electrodes separated by polycrystalline barriers with arbitrarily-chosen but controlled barrier height and shape is accomplished by varying the composition and doping of polycrystalline multinary compound semiconductor materials in the barrier, hence varying the Fermi level pinning position such that the Fermi level is fixed and controlled at and everywhere in between the two metal-insulator interfaces. It is known that Schottky barrier heights at metal/compound semiconductor interfaces are determined by a Fermi level pinning mechanism rather than by the electronic properties of the applied metallurgy. The present invention exploits the knowledge that the same type of Fermi level pinning occurs at semiconductor dislocations and grain boundaries. The present invention uses polycrystalline compound semiconductor alloys in which the pinning position is varied over a large range in metal/semiconductor structures.

Abstract: In a display device including active switching units, lateral Schottky diodes are used as switching elements. In the lateral Schottky diodes a sub-micron distance between the Schottky electrode and the opposing electrode contacting the semiconductor body is obtained by anodizing the Schottky metal and subsequently doping the exposed portion of the semiconductor body, for example, by ion implantation.

Abstract: A Schottky-type diode is fabricated by a process that enables the diodes conductor-to-semiconductor barrier height .phi..sub.B to be controlled by adjusting the thickness of a metal silicide layer (22) which forms a rectifying junction (20) with an N-type semiconductor (24). In fabricating one version of the diode, a metallic layer (70) consisting of two or more metals such as platinum and nickel is deposited on an N-type silicon semiconductor (68) and heated to create a metal silicide layer (72) consisting of a lower layer (62) and an upper layer (74) of different average composition. A portion of the upper layer is then removed, allowing .phi..sub.B to be adjusted suitably.

Abstract: Transition metal silicide semiconductor electromagnetic radiation source and detectors have a thin film of semiconducting silicide grown or deposited on a silicon wafer. The transition metals are chosen from a group consisting of iron, iridium, manganese, chromium, rhenium, barium, calcium, magnesium and osmium. The detectors are intrinsic and can be formed either as discrete devices, monolithically or in array on a silicon chip to provide an integrated detector. The transition metal silicide semiconductors are efficient detectors at wavelengths which mate with the transmission capabilities of certain optical fibers enhancing the combination of infra-red detectors and optical fiber transmission previously unknown. Iron disilicide is useful as an infra-red radiation source and as an extrinsic detector as well.

Abstract: The thickness of a selected layer in an epitaxial heterojunction transistor is initially set to the exact desired value upon its formation, preferably by molecular beam epitaxy, and its thickness is left virtually unaltered during the rest of the fabrication process. Means are provided to prevent alteration of this thickness during subsequent exposure of the selected layer.

Abstract: A method for the manufacture of a MESFET comprising a gate that is self-aligned both with respect to the source and drain regions as well as with respect to the appertaining metallizations, whereby a first metal layer (21), a first dielectric layer (31), and a first lacquer mask layer are applied following doping of the carrier substrate. A trench producing an outer recess in the doping layer (11) is formed by anisotropic etching. A second dielectric layer is isotropically deposited and is anisotropically re-etched except for spacers (51/52) whereby an inner recess (double recess) is produced in the doping layer and, finally, the gate metal (22) is applied.

Abstract: The invention is a layered nonalloyed ohmic contact structure for use on n type gallium arsenide including a layer of germanium or silicon of the order of 10 .ANG. thick evaporated onto the gallium arsenide; a diffusion barrier layer of material 100-200 .ANG. thick over the germanium or silicon selected from non-metallic conducting compounds, including metal compounds ofarsenidephosphidecarbideboridenitridesilicideand non-metallic conducting elements; with the diffusion barrier layer material characterized by resistivity of the order of 1 ohm cm or less; and a conducting metal overlayer on the diffusion barrier layer. The invention includes the method for manufacturing the contact structure.

Abstract: A method of fabrication of non-linear control elements as applicable to electrooptical displays and in particular to large-area liquid-crystal displays of the flat-panel type, in which the following layers are stacked successively on a substrate: a first layer of metallic material, a first layer of undoped amorphous semiconductor material, a layer of doped amorphous semiconductor material, a second layer of undoped amorphous semiconductor material, and a second layer of metallic material.

Abstract: The manufacture of a self-aligned gate contact having a very short gate length measuring, for example, 0.3 to 0.1 micron wherein photolithography is carried out together with isotropic deposition to produce a gate contact having an extremely low lead resistance, the method utilizing a masking element which is removed by a lift-off technique.

Abstract: There is disclosed a film field effect transistor which can be operated at fast switching rates for use, for example, in video display applications. The transistor includes a body of silicon semiconductor material having a structure more ordered than amorphous material and less ordered than single crystalline material. The source and drain of the transistor comprise rectifying contacts formed on the body of silicon semiconductor material. Also disclosed are a method of making the transistor and an electronically addressable array system utilizing the transistor to advantage.

Abstract: The invention relates to a process for the fabrication of a field-effect transistor as described in German Patent Application No. P 35 35 002.4, corresponding to U.S. application Ser. No. 06/914,540 comprises first covering a semiconductor member with a layer which forms the channel region and part of which is covered with a passivation layer. Impurities are implanted into the exposed regions of the semiconductor surface and form underneath the channel region highly doped source and drain regions. A surface layer of the passivation layer is then removed in a section adjacent to the source region and a gate electrode is formed on the thus exposed narrow area of the channel region.

Abstract: A process for producing a semiconductor device includes depositing a layer of insulator material onto a supporting substrate of the type having a surface which includes a channel region below the surface thereof containing a carrier concentration of a desired conductivity type, removing selected portions of the insulator material to form a substitutional gate on the substrate surface, forming side walls bounding substitutional gate to define an effective masking area in cooperation with the substitutional gate, ion implanting a dopant into the unmasked region of the substrate, removing the side walls, annealing the resultant device, removing the substitutional gate, depositing gate metal and first and second ohmic contacts in correct positional relation to one another on the substrate, and depositing metallic interconnects in electrical communication with the ohmic contacts to produce a semiconductor device.

Abstract: In the manufacture of a Schottky gate field effect transistor, an insulating film is deposited on the main surface of a semiconductor substrate and is then selectively removed to form therein a window through which the substrate surface region for forming an active layer is exposed to a space in which the gate will ultimately be provided. A metal which forms a Schottky junction between it and the semiconductor of the active layer and can be removed by anisotropic etching and a metal which can be used as a mask for the etching of the above metal are deposited in layers on the insulating film and the substrate surface exposed through the window. The overlying metal layer thus deposited is planarized to leave in the window alone. The underlying metal layer is selectively removed by anisotropic etching through the overlying metal layer remaining in the window, thus forming a gate electrode made up of the overlying and underlying metal layers.

Abstract: During the deposition of a metallic layer on an N-type semiconductive region to form a Schottky diode in a structure placed in a highly evacuated chamber, at least one selected gas is introduced into the chamber to control the forward voltage across the diode.

Abstract: An integrated injection logic (I.sup.2 L) semiconductor structure is disclosed which may be advantageously implemented in a group III-V compound semiconductor such as gallium arsenide. The base region of the lateral transistor is made extremely thin (less than one-tenth micron) by use of "regrowth" techniques. The structure of the vertical transistor is simplified by using a Schottky collector.

Abstract: An improved Schottky barrier device and method of manufacture is disclosed. The device has a semiconductor layer of first conductivity type; an insulating layer covering one face of the semiconductor layer, and has an opening therein. A conductor layer covers the semiconductor layer where the semiconductor layer is exposed by the opening and there forms a recitifying junction with the semiconductor layer. A first region of opposite conductivity type is at the one face of semiconductor layer and extends from where the conductor layer meets the insulating layer and below the conductor layer. A second region of opposite conductivity type is at the one face of semiconductor layer and begins where the conductor layer meets the insulating layer and extending below the insulating layer.

Abstract: A Schottky barrier diode is made from a substrate of semiconductor material by forming, on a major surface of the wafer, a layer of dielectric material defining a restricted opening through which the semiconductor material is exposed. A metal which forms with the semiconductor material a single phase compound which is inherently stable at temperatures up to 600 deg. C. is deposited into the opening, into contact with the exposed semiconductor material. By heating the substrate and the metal deposited thereon, the metal reacts with the semiconductor material to form a body of the single phase compound. A layer of refractory metal which reacts with the dielectric material is deposited over the dielectric material and the body of single phase compound.

Abstract: A method for manufacturing a semiconductor device of the invention comprises the steps of(a) forming a gate insulating film on a surface of a silicon substrate, and a gate electrode on said gate insulating film;(b) forming a self-aligned insulating film at least on a side wall of said gate electrode;(c) forming a self-aligned metal or metal silicide film on a region on which an insulating film is not formed, said region including a source region, a drain region and a diffusion interconnection region which is an extended part of at least one of said source region and said drain region, or prospective regions for said source, drain and diffusion interconnection regions; and(d) forming said source region, said drain region and said diffusion interconnected region which is the extended part of at least one of said source region and said drain region, by doping at least one time said substrate with an impurity which has a conductivity type opposite to a conductivity type of said silicon substrate any time after st

Abstract: A method of producing a high frequency III-V FET and the resultant structure is described wherein a doped layer is formed on a wafer of undoped, semi-insulating III-V material. The structure is then etched to form a mesa after which, a channel region is regrown from an exposed portion of the III-V substrate. The formation of the channel region defines the source and drain regions. Ohmic contacts are then made to the source and drain regions after which a Schottky contact is made to the channel region.