Transmutation Doping Patents (Class 148/DIG165)
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Patent number: 5259917Abstract: A method for producing a semiconductor crystal which is highly transparent in the 1-3 .mu. spectral range is described which comprises the steps of exposing the crystal to high energy ionizing gamma radiation to produce within the crystal energetic photo electrons which produces defect donors to cancel acceptors existing in the as-grown crystal.Type: GrantFiled: July 28, 1992Date of Patent: November 9, 1993Assignee: The United States of America as represented by the Secretary of the Air ForceInventor: Melvin C. Ohmer
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Patent number: 5212100Abstract: About 6 to 20 micrometer resistivity N- (600 ohm-cm and above) silicon is epitaxially deposited on N+ (0.01 to 0.1 ohm-cm) substrates. The resistivity of the epitaxial layer is lowered to 5 to 60 ohm-cm using neutron activated doping. A 1 micrometer p-well process is utilized to build natural (unadjusted) PMOS transistors in the bulk silicon. These transistors operate in the subthreshold region where the threshold or turn on voltages have to match closely across a large device. N-channel transistors are fabricated in a P-well. The advantage of using neutron activated doped silicon is that the carrier concentration is very uniform and therefore threshold variations are much smaller than in transistors built in conventional doped silicon. The use of a neutron doped epitaxial layer on a P-well CMOS process provides a novel approach to control dopant uniformity and thus uniform transistor characteristics as well as providing a heavily doped conventional substrate to enhance resistance to CMOS latch-up.Type: GrantFiled: December 4, 1991Date of Patent: May 18, 1993Assignee: Texas Instruments IncorporatedInventors: Emily A. Groves, Gary J. Grant
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Patent number: 4910156Abstract: A silicon wafer and a method of producing a silicon wafer comprising a phosphor-doping method of doping phosphor into a single silicon crystals by transmuting isotope Si.sup.30 contained in said single silicon crystals made by the CZ method or the MCZ method into p.sup.31 under neutron irradiation to said single silicon crystals.Type: GrantFiled: December 22, 1987Date of Patent: March 20, 1990Assignee: Toshiba Ceramics Co., Ltd.Inventors: Shin'ichiro Takasu, Michihiro Ohwa, Kazuhiko Kashima, Eiichi Toji, Kazumoto Homma
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Patent number: 4728371Abstract: A method for manufacturing regions having adjustable uniform doping in silicon crystal wafers by neutron irradiation according to the reaction Si.sup.30 (n,.gamma.) Si.sup.31 .beta..sup.- P.sup.31 includes the steps of covering the silicon crystal wafer with neutron-absorbing materials of different thicknesses during the irradiation, and selecting materials having isotopes having a high absorption cross-section which yield stable isotopes in the nuclear reaction having small or short-lived activity. Suitable isotopes are B.sup.10, Cd.sup.113, Sm.sup.149, Gd.sup.155 and Gd.sup.157. The regions are generated photolithographically. By such specific material selection, very small layer thicknesses can be used and microfine surface zones or areas can be doped with high geometrical precision and large penetration depth. The method is particularly suited for manufacturing power thyristors.Type: GrantFiled: March 11, 1986Date of Patent: March 1, 1988Assignee: Siemens AktiengesellschaftInventors: Ernst W. Haas, Joachim Martin, Heinz Mitlehner, Reinhold Kuhnert
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Patent number: 4684413Abstract: A method for decreasing the turnoff time in a crystalline semiconductor region within a semiconductor device comprises initially providing a semiconductor region having a predetermined density of pinning centers. The semiconductor region is then irradiated so as to yield crystal damage that is equivalent to or greater than that which would be produced by irradiating with 1 MeV neutrons at a fluence greater than approximately 10.sup.13 cm.sup.-2. The region is then annealed at a temperature of approximately 350.degree. to 450.degree. C. for approximately 15 minutes to one hour so as to yield a density of stable recombination centers correlating with the pinning centers that provides a stable minority carrier lifetime within the semiconductor region.Type: GrantFiled: October 7, 1985Date of Patent: August 4, 1987Assignee: RCA CorporationInventors: Alvin M. Goodman, Lawrence A. Goodman, John P. Russell, Paul H. Robinson
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Patent number: 4639276Abstract: A thyristor having a high tolerable voltage V.sub.Bo comprising a first emitter layer (3), a first base layer (1), a second base layer (2), a second emitter layer (4) covering the surface except for a gate region (5) of the second emitter layer, said layers being of alternating semiconductivity types, a first emitter electrode (6), a second emitter electrode (7) and a gate electrode (8) overlaying the gate region, wherein the gate region is formed over an area of the first base region having a higher impurity concentration than any other area of the first base layer. The area of highest impurity concentration may be formed by a process of pulling an ingot of silicon from the melt with a magnetic field applied perpendicular to the convection of silicon with the temperature at the desired area being higher than elsewhere or by a process of neutron irradiating a wafer of float-zone silicon with the highest neutron dose at the desired area.Type: GrantFiled: September 19, 1985Date of Patent: January 27, 1987Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Tsutomu Nakagawa