Abstract: A control element for a magnetomechanical EAS marker is formed of an amorphous metalloid that has been annealed so as to be at least partially crystallized while remaining substantially flat. The annealing is preferably a two-stage process applied to induce semi-hard magnetic characteristics in an amorphous metallic material that is magnetically soft as cast. The two stages include a first stage in which the material is annealed for at least one hour at a temperature that is below a crystallization temperature of the material. The first stage results in a reduction in the volume of the material. The second stage is carried out at a temperature that is above the crystallization temperature and for a time sufficient to crystallize the bulk of the material and give it semi-hard magnetic properties. The two-stage annealing process prevents deformation of the material which has resulted from conventional crystallization processes.

Abstract: The present invention provides a method of manufacturing a semiconductor wafer whereby (1) deterioration of a micro-roughness in a low temperature range in hydrogen atmospheric treatment and increase of resistivity due to outward diffusion of an electrically active impurity in a high temperature range are prevented; (2) in the heat treatment in a hydrogen gas atmosphere, the concentration of gas molecules in the atmosphere, such as water, oxygen and the like, are brought to 5 ppm or less in water molecule conversion; and a reaction is suppressed in which a substrate surface is oxidized unequally and the micro-roughness deteriorates; and (3) the same kind of impurity as the electrically active impurity contained in a Si substrate is mixed into the atmosphere and the outward diffusion of the impurity in the vicinity of the Si substrate surface is prevented to prevent variation of the resistivity.

Abstract: A method for reaction bonding surfaces at low temperatures in which polished and cleaned surfaces are bombarded with a mixture of oxygen and fluorine ions to produce activated surfaces. The activated surfaces are then cleaned to remove particulates, then contacted at room temperature to affect a reaction bond therebetween. The bond energy of the reaction bonded surfaces increase with time at room temperature. The rate at which the bond energy of the reaction bonded surfaces increases may be enhanced by moderate heating at a low temperature below a temperature which would be detrimental to any part of the reaction bonded structure. A satisfactory bond energy for silicon wafers can be achieved in four hours at room temperature and in less than 10 minutes at 50.degree. C.

Abstract: `Unintentionally` doped P type GaAs is grown on silicon by a metal organic chemical vapor deposition process in which the molecular ratio of arsenic to gallium in the growth ambient is reduced to a value that is sufficiently low to cause the creation of donor (As) site vacancies in the grown GaAs layer, which become occupied by acceptor (carbon) atoms in the metal organic compound, thereby resulting in the formation of a buffer GaAs layer having a P type majority carrier characteristic. Preferably, the silicon substrate has its growth surface inclined from the [100] plane toward the [011] direction is initially subjected to an MOCVD process (e.g. trimethyl gallium, arsine chemical vapor deposition) at a reduced temperature (e.g. 425.degree. C.) and at atmospheric pressure, to form a thin (400 Angstroms) nucleation layer. During this growth step the Group V/Group III mole ratio (of arsenic to gallium) is maintained at an intermediate value. The temperature is then ramped to 630.degree. C.

Abstract: For the growth of strain-layer materials and high quality single and multiple quantum wells, the instantaneous control of growth front stoichiometry is critical. The process of the invention adjusts the offset or phase of MBE control shutters to program the instantaneous arrival or flux rate of In and As.sub.4 reactants to grow InAs. The interrupted growth of first In, then As.sub.4, is also a key feature.

Abstract: An improved system and method for annealing indium antimonide ion implanted junctions employing an open-tube benign annealing environment. A furnace having a hollow chamber therein is maintained continuously at a predetermined annealing temperature and wafers of indium antimonide to be annealed are inserted into the chamber through a resealable airlock at one end of the chamber. A source of molten indium saturated with antimony is provided within the chamber to maintain desired partial pressures of indium and antimony within the chamber. Hydrogen gas is continuously flushed through the chamber to purge contaminants and maintain the chamber at a desired slight overpressure over atmospheric. At the conclusion of annealing, the indium antimonide wafer is removed from the chamber into the airlock which is flushed with hydrogen gas. The wafer is allowed to cool to room temperature and removed from the airlock for subsequent processing steps.

Abstract: A method of annealing a wafer in a rapid thermal annealer is disclosed. The walls of the chamber are heated more rapidly than is the wafer. In a preferred embodiment, the interior of the graphite walls of the annealer is lined with a molybdenum sheet which is open toward the lamps that heat the chamber. Thus, the walls heat very rapidly to a temperature greater than the condensation point of arsenic, preventing arsenic condensation on the walls. Effective annealing can be achieved at wall temperatures in the range of 500.degree. to 600.degree. C. Prior to the heat ramp up, an arsenic atmosphere, preferably trimethylarsenic (TMAs) at an appropriate overpressure is introduced. This overpressure is maintained both during the heating and cooling cycle. By the use of this method, the exposure time for annealing can be reduced from prior times of as much as 20 minutes to as little as 10 seconds.

Abstract: The disclosure relates to a method of forming in situ phosphorous doped polysilicon wherein a surface upon which phosphorous doped polysilicon is to be deposited is placed in a vacuum furnace and, after low pressure HCl cleaning of the surface and furnace, a predetermined ratio of silane and a gaseous phosphorous containing compound taken from the class consisting of phosphorous trichloride, tertiary butyl phosphine, isobutyl phosphine, trimethyl phosphate and tetramethyl phosphate are simultaneously passed through the furnace at predetermined pressure and temperature to provide a uniformly phosphorous doped layer of polysilicon on the surface.

Abstract: This invention concerns a production method and a processing apparatus for semiconductor devices, as well as an evacuating apparatus used for the processing apparatus. According to this invention, since the evacuation system of pressure-reduction processing apparatus for conducting various wafer processings during production steps of semi-conductor devices is constituted only with oil-free vacuum pump, deleterious oil contaminations or carbonation products of oils produced from oils upon heating are not present in the pressure-reducing processing chamber as compared with conventional pressure-reducing processing apparatus using a vacuum oil pump as an evacuation pump and the production method of semiconductor devices using such apparatus.

Abstract: The disclosure relates to a method for producing single crystal silicon from a polycrystalline silicon melt wherein dopants such as oxygen and nitrogen are uniformly distributed in the crystal both along the crystal axis and radially therefrom. This is accomplished by identifying the correct species in the melt and above the melt and determining the thermochemical equilibrium between the two chemical species which lead to a change of the composition of the silicon single crystal during the entire growth process. This approach effectively circumvents the segregation coefficient during the growth process through the control of the concentration of the dopants in the melt.

Abstract: Disclosed is a method of making ohmic and/or Schottky barrier contacts to a silicon semiconductor substrate in which before depositing the metal on silicon semiconductor substrates containing integrated circuits which are covered by a mask having contact windows, the metal is initially deposited on freshly cleaned blank silicon semiconductor substrates mounted in the same vacuum chamber. In this manner any traces of oxygen present in the vacuum chamber are chemisorbed by the blank substrate resulting in deposition of a high quality oxide-free metal contacts on the device substrates.

Abstract: A method and apparatus is described for activating implants in gallium arsenide incorporating crushed gallium arsenide and hydrogen to form a gas mixture to provide an atmosphere for the gallium arsenide to be activated and a furnace for heating the crushed gallium arsenide to a first temperature and the gallium arsenide to be activated to a second temperature. The invention overcomes the problem of wafer loss at the surface by evaporation during anneal and activation of gallium arsenide.