Abstract: A selective sidewall diffusion process using doped SOG. A substrate is processed to form raised portions or pedestals, having sidewalls, and trenches. A first layer, either a doped SOG layer or undoped oxide layer, may be deposited onto the substrate adjacent the sidewalls. The first layer is densified. A second layer may be deposited on the first layer. The second layer is a doped SOG layer. The second layer is densified and the dopant is driven into the sidewalls to form shallow junctions.

Abstract: HgCdTe semiconductor material having an n-type epitaxial layer is grown on a substrate. A graded p-type epitaxial layer is grown on the n-type layer. The p-type layer is graded such that the large bandgap region is adjacent the heterojunction with the narrow bandgap region at the surface of this layer. The periphery of the p-type layer is then etched to expose the large bandgap material. A HgCdTe passivation layer may then be formed on the p-type layer. A resultant structure is then mesa etched. A metal, such as indium, is formed along the walls of the mesa structure. Indium is selected to form a good ohmic contact with the n-type layer and a Schottky barrier with the large bandgap exposed edge of the p-type layer. In this way, the PN junction is passivated at the large bandgap material. The remaining narrow bandgap material in the p-type will form a good ohmic contact to a metal contact formed on this layer.

Abstract: In a semiconductor device according to the present invention, a pair of element regions of a second conductivity type are formed so as to be electrically isolated from each other on a semiconductor substrate of a first conductivity type, a complementary MOS transistor is formed in one of the element regions of the second conductivity type, and a double-diffused MOS transistor is formed in the other element region of the second conductivity type. The complementary MOS transistor is of a surface channel type in which N- and P-channel MOS transistors are respectively formed in a pair of well diffusion layers of the first and second conductivity types formed in the element region of the second conductivity type, and conductivity types of the respective gate electrodes of the N- and P-channel MOS transistors are different from those of the respective well diffusion layers.

Abstract: An EEPROM design featuring narrow linear electrodes including a source, a drain, a thin oxide, channel and floating gate. A pair of linear, opposed field oxide barrier walls form widthwise boundaries of the active structure which can be very closely spaced. The drain electrode, implanted in the substrate, abuts both opposed field oxide lateral walls, but does not extend under either wall. The source, drain and channel are formed in a single implant followed by diffusion after the field oxide barrier walls are formed, but prior to formation of the floating gate. All but opposed field oxide walls in a stripe design. A control gate is disposed over the floating gate. The combination of opposed field oxide barrier walls, a stripe electrode design, and single step implant for electrode formation results in a very compact cell, utilizing a simplified EEPROM process.

Abstract: A buried contact between the gate of a transistor device formed at the surface of a semiconductor substrate and a diffusion region formed in the surface of the substrate remote from the transistor device. The buried contact includes a polysilicon interconnect structure formed after shaping of the gate layer and the gate insulator. The polysilicon interconnect structure engages a side edge and an adjoining lower surface of the gate layer at a location where the gate insulator has been removed by isotropic etching from between the gate layer and the surface of the substrate. The polysilicon interconnect layer also contacts the surface of the substrate beneath an overhanging edge of the gate layer so as to form a surface current pathway interface. Below the surface current pathway interface a migration region is formed by heat-induced movement of ions from the gate layer through the polysilicon interconnect structure.

Abstract: A method for making a self-aligned IID structure for an LED (10) is provided. This self-aligned IID structure is accomplished by depositing a dopant layer (17) over the LED structure. A polymeric material is deposited over layer (17). The polymeric layer and dopant containing layer (17) are etched to a predetermined position. The remaining polymeric material is removed from the LED (10) structure. The LED (10) structure is annealed to produce an IID structure by laterally diffusing dopants from layer (17) into at least one side wall of the LED (10).

Abstract: SOI islands having doped edges are formed by providing over the surface of a layer of single crystalline silicon on an insulating substrate a masking layer formed of two layers, the lowermost layer adjacent the silicon layer being silicon oxide and the uppermost layer being silicon nitride. The masking layer is defined using standard photolithographic techniques and etching to form the masking layer over only the areas of the silicon layer which are to form the islands. The uncovered portion of the silicon layer is then removed by etching to form the islands. The lowermost layer of the masking layer is then etched laterally away from the edges of the island to expose a portion of the surface of the silicon layer adjacent the edges of the islands. After removing the uppermost layer of the masking layer, the exposed edge portions of the surface of the silicon layer are doped by ion implantation to form the islands with doped edges.

Abstract: A semiconductor body (10) has at one major surface (15) a step (14) defining a device area (13) of the semiconductor body above a buried region (12) provided within the semiconductor body (10). A protective insulating layer (24) is provided on a side wall (14a) of the step (14) and an insulating region (22) on an area (15a) of the one major surface adjoining the side wall (14a) of the step. Silicon is deposited over the one surface (15) with the anti-oxidation layer (24) on the side wall (14a) of the step (14) to define over the area (15a) of the one surface (15) an intermediate silicon region (23c) which is isolated from the side wall (14a) of the step and which leaves a window area (14'a) of the side wall (14a) exposed. The protective insulating layer (24a) is then removed from the window area (14'a) of the side wall (14a).

Abstract: Methods of fabricating heavily doped edges of mesa structures in silicon-on-sapphire and silicon-on-insulator semiconductor devices. The methods are self-aligning and require a minimum of masking steps to achieve. The disclosed methods reduce edge leakage and resolve N-channel threshold voltage instability problems. Mesa structures are formed that comprise N-channel and P-channel regions having a thermal oxide layer deposited thereover. A doping layer of borosilicate glass, or alternatively, an undoped oxide layer that is subsequently implanted, is deposited over the mesa structures. In the first method, the doping layer is etched by means of an anisotropic plasma etching procedure to form oxide spacers at the edges of the mesa structures. The doping layer is removed from the N-mesa structures using an N-channel mask and wet oxide etching procedure. The structure is then heated to a relatively high temperature to drive the dopant into the edges of the N-channel mesa structures.

Abstract: A CMOS and bipolar fabrication process wherein a silicon dioxide layer initially formed over a silicon substrate is etched for forming separate collector and base/emitter regions for a bipolar device, and PMOS and NMOS regions for corresponding PMOS and NMOS devices. Buried layer implants are performed using a minimum number of masks, and then an epitaxial layer is grown over the exposed portions of the silicon substrate. The silicon dioxide walls between the devices provide full dielectric isolation between the devices, as well as between the collector and base/emitter regions of the bipolar device. Nonetheless, the oxide wall between the collector and base/emitter of the bipolar device is sufficiently small to allow the buried layer implants to joint under the wall for forming a conventional buried layer for the bipolar device. Because of the oxide walls, the minimum distance between devices may be 0.5 microns or less.

Abstract: A method for suppressing ionization avalanches in a single wafer dry etch reactor is provided. An electron scavenging agent is mixed with helium gas in a container (32). The mixture of helium and the agent is introduced through an inlet (34) to a chamber (30) formed between a wafer (24), an O-ring (26) and a powered cathode (16). As free electrons are accelerated through a potential drop in the inlet and outlet (34 and 40), the electron scavenging agent combines with electrons to form anions. Partially due to the fact that anions are too massive to reach the energy level required to ionize helium, ionization avalanches of helium are suppressed and, thus, there is no arcing in the inlet and outlet (34 and 40).

Abstract: The invention relates to a method of manufacturing a Bi-CMOS semiconductor IC device in which the bipolar transistor structure contained therein has a flat PN plane junction between its base and emitter regions, said device having improved breakdown voltage characteristics.The improved method involves preparing a silicon substrate having a P-type base region formed in an N-type collector region, forming a thick silicon oxide layer over the suface of a bipolar transistor region on said substrate, selectively removing the silicon oxide layer to form a first window exposing a part of the collector region and a second window exposing a part of the base region, diffusing phosporus atoms into the base region and collector region through said first and second windows to form an emitter region in the base region and a collector contact in the collector region, subjecting the structure thus-obtained to an oxidation process in a wet oxygen atmosphere at a temperature of 940.degree. C..+-. 20.degree. C.