Abstract: A process for making a vertical PNP transistor and a transistor made by the process includes providing a highly doped semiconductor substrate (10) of P conductivity type. A first lightly doped P- layer (12) is epitaxially grown on the substrate (10). An N+ type buried layer impurity (18) is introduced into a surface region of the first lightly doped layer (12) that will underlie and define an island in which the vertical transistor will be constructed. A second lightly doped P- layer (16) is epitaxially grown on the first lightly doped layer (12) and the buried layer impurity (18). An N+ type isolation impurity is diffused into the second layer to form wells to laterally enclose an island (22) of the second layer (16) above the buried layer impurity (18). An N type base impurity (28) is diffused into the island (22) region of the second layer (16), and a P type emitter impurity (30) is diffused into the base region (28).

Abstract: In a method for producing a diode, a first, strongly positively doped silicon wafer is bonded in accordance with the silicon fusion method to a second, weakly negatively doped silicon wafer, and subsequently the weakly negatively doped second silicon wafer is ground down to a predetermined thickness. A chromium layer which contains a small percentage of arsenic is used for resistive contact-making on the negatively doped second silicon wafer. In this way, a diode is obtained which has a small forward voltage in conjunction with a precise breakdown voltage.

Abstract: A method for reproducibly fabricating a thin base region of a vertical bipolar transistor therein, which has a high transfer speed and increases a current driving force, and a method for increasing the isolating effect of the vertical bipolar transistor through forming a second buried layer implanting N-type impurity into an upper peripheral portion of first buried layer and activating the implanted N-type impurity, then out-diffusing the activated N-type impurity at the same time as growing the epitaxial layer, so the second buried layer definitely separates the elements of the transistor. Both the first buried layer and the second buried layer define a portion of epitaxial layer to form an active region which functions as a collector region. A subcollector region is formed above first buried layer in active region, and a base region is formed at a first upper portion of the active region to overlay the subcollector region.

Abstract: An interconnect structure, and method for forming same, is suitable for use in integrated circuits such as SRAM devices. The structure uses masking of a polycrystalline silicon interconnect level to move a P-N junction to a region within a polycrystalline silicon interconnect line, rather than at the substrate. This P-N junction can then be shorted out using a refractory metal silicide formed on the polycrystalline silicon interconnect structure.

Abstract: An interconnect structure, and method for forming same, is suitable for use in integrated circuits such as SRAM devices. The structure uses masking of a polycrystalline silicon interconnect level to move a P-N junction to a region within a polycrystalline silicon interconnect line, rather than at the substrate. This P-N junction can then be shorted out using a refractory metal silicide formed on the polycrystalline silicon interconnect structure.

Abstract: A method for the formation of buried gates in a semiconductor device using epitaxial growing method combined with diffusion method or diffusion by an additional heat treatment. The buried gate has smaller gate resistance by providing relatively high impurity concentration and also having good reverse characteristic by providing relatively low impurity concentration at the top of the buried gates.