Emitter Dip Patents (Class 148/DIG47)
  • Patent number: 5035957
    Abstract: Disclosed are coated metal articles having protective coatings which are applied to substrate metals by coating the metal surface, e.g. by dipping the substrate metal in a molten alloy of the coating metals, and then exposing the coating at an elevated temperature to an atmosphere containing a reactive gaseous species which forms an oxide, a nitride, a carbide, a boride or a silicide. The coating material is a mixture of the metals M.sub.1 and M.sub.2, M.sub.1 being zirconium and/or titanium, which forms a stable oxide, nitride, carbide, boride or silicide under the prevailing conditions. The metal M.sub.2 does not form a stable oxide, nitride, carbide, boride or silicide. M.sub.2 serves to bond the oxide, etc. of M.sub.1 to the substrate metal. Mixtures of M.sub.1 and/or M.sub.2 metals may be employed. Eutectic alloys of M.sub.1 and M.sub.2 which melt substantially lower than the melting point of the substrate metal are preferred.
    Type: Grant
    Filed: February 23, 1990
    Date of Patent: July 30, 1991
    Assignee: SRI International
    Inventors: Robert W. Bartlett, Paul J. Jorgensen, Ibrahim M. Allam, David J. Rowcliffe
  • Patent number: 4849344
    Abstract: An improved process for fabricating modified isoplanar integrated circuits with enhanced density incorporates a number of interactive and co-acting process steps. First, oxide isolation of epitaxial islands is effected in a two step process, forming a thin thermally grown oxide layer (32), over the surfaces of shallow trenches and then filling the shallow trenches with deposited low temperature oxide (34). Second, an enhanced single polycrystalline or polysilicon layer process uses a blanket implant, eliminates certain masking and etching steps, and defines the polycrystalline layer. Third, a new method and structure is provided for dielectrically isolating and separating contact locations on different surface levels of the integrated circuit structure adjacent to step locations between the surface levels. Finally, a new method constitutes all of the electrical contact locations for the elements of the integrated circuit structure at the same substantially isoplanar level.
    Type: Grant
    Filed: October 27, 1988
    Date of Patent: July 18, 1989
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Donald J. Desbiens, John W. Eldridge, Paul J. Howell