Graded Energy Gap Patents (Class 148/DIG67)
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Patent number: 5810924Abstract: A multi-layered structure and process for forming it arc described, incorporating a single crystal substrate, a plurality of epitaxial layers having graded composition wherein the layers have changing lattice spacings not exceeding about 2 percent per 1000 .ANG. of thickness whereby misfit dislocations are formed to relieve strain and then move to the edges of respective layers. The invention overcomes the problem of large numbers of misfit dislocations threading to the surface of the top layer, especially during device processing at temperatures in a range from 700 to 900 degrees Celsius. Fully relaxed, incommensurate structures having low defect densities are obtained, where arbitrary combinations of materials can be used.Type: GrantFiled: June 7, 1995Date of Patent: September 22, 1998Assignee: International Business Machines CorporationInventors: Francoise Kolmer Legoues, Bernard Steele Meyerson
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Patent number: 5484737Abstract: Disclosed is a fabrication of a bipolar transistor with a super self-aligned vertical structure in which emitter, base and collector are vertically self-aligned, the fabrication method comprising the steps of forming a conductive buried collector region in a silicon substrate by using ion-implantation of an impurity and thermal-annealing; sequentially forming several layers; selectively removing the nitride and polysilicon layers to form a pattern; sequentially forming a silicon oxide layer, a third layer and a silicon oxide layer thereon; forming a patterned photoresist layer thereon to define active and inactive regions and removing several layers on the active region to form an opening; forming a side wall on both sides of the opening; forming a collector on a surface portion of the buried collector region up to a lower surface of the polysilicon layer; removing the side wall and the third nitride layer to expose a side surface of the second polysilicon layer; selectively forming a base on an upper surfaceType: GrantFiled: December 13, 1994Date of Patent: January 16, 1996Assignees: Electronics & Telecommunications Research Institute, Korea Telecommunication AuthorityInventors: Byung-Ryul Ryum, Tae-Hyeon Han, Soo-Min Lee, Deok-Ho Cho, Seong-Hearn Lee, Jin-Young Kang
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Patent number: 4944811Abstract: A material for a light emitting element most suited for a light emitting diode or laser diode which emits visible light of 550 to 650 nm band wavelength. The material provides an at least two-layered structure composed of a GaAs substrate and a Sn doped InGaP layer developed on the substrate without forming a gradient layer therebetween. The mixed crystal composition of the Sn doped InGaP layer as expressed by the molar fraction of GaP is 0.50 to 0.75.According to the method for developing mixed crystals of InGaP, GaP and InP are dissolved in Sn to make a solution. The solution is allowed to come in contact with a GaAs substrate so that InGaP crystals are developed directly on the GaAs substrate without a gradient layer for coordinating the lattice constant formed on the GaAs substrate.Type: GrantFiled: August 9, 1989Date of Patent: July 31, 1990Assignees: Tokuzo Sukegawa, Mitsubishi Cable Industries, Ltd.Inventors: Tokuzo Sukegawa, Kazuyuki Tadatomo
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Patent number: 4865655Abstract: An epitaxial wafer for producing arrays of GaAsP-LEDs comprises, in the GaAs.sub.1-x P.sub.x layer with varying X, a layer region(s) with a discontinuous variance of x along the thickness of the GaAs.sub.1-x P.sub.x layer. This layer region(s) contribute to a uniformity in the brightness of the light emission of LEDs formed in the epitaxial wafer.Type: GrantFiled: November 18, 1987Date of Patent: September 12, 1989Assignees: Mitsubishi Monsanto Chemical Co., Ltd., Mitsubishi Chemical Industries, Ltd.Inventors: Hisanori Fujita, Masaaki Kanayama, Takeshi Okano
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Patent number: 4861393Abstract: A molecular beam epitaxy method of growing Ge.sub.x Si.sub.1-x films on silicon substrate is described. Semiconductor heterostructures using Ge.sub.x Si.sub.1-x layers grown on either Ge or Si substrates are described.Type: GrantFiled: May 28, 1987Date of Patent: August 29, 1989Assignee: American Telephone and Telegraph Company, AT&T Bell LaboratoriesInventors: John C. Bean, Leonard C. Feldman, Anthony T. Fiory
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Patent number: 4716445Abstract: The heterojunction bipolar transistor has a structure of wide band-gap transistor and comprises a collector region having an N-type GaAs layer, a base region having a P-type germanium layer formed on the N-type GaAs layer, and an emitter region having an N-type semiconductor layer of mixed crystal of silicon and germanium formed on the P-type germanium layer. The mixed crystal of the N-type semiconductor layer may have a uniform distribution of silicon or a graded distribution of silicon in which a content of silicon is zero at the surface facing the P-type germanium layer and is continuously increased with distance from the surface facing the P-type germanium layer.Type: GrantFiled: January 20, 1987Date of Patent: December 29, 1987Assignee: NEC CorporationInventor: Jun'ichi Sone
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Patent number: 4644381Abstract: An integrated injection logic (I.sup.2 L) semiconductor structure is disclosed which may be advantageously implemented in a group III-V compound semiconductor such as gallium arsenide. The base region of the lateral transistor is made extremely thin (less than one-tenth micron) by use of "regrowth" techniques. The structure of the vertical transistor is simplified by using a Schottky collector.Type: GrantFiled: April 8, 1985Date of Patent: February 17, 1987Assignee: Siemens Corporate Research & Support, Inc.Inventor: Chan-Long Shieh
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Patent number: 4548658Abstract: A method is disclosed for growing an epitaxial layer composed of semiconductor material belonging to the cubic crystal system on a substrate, where the lattice constant of the epitaxial layer is graded from an initial lattice constant adjacent to the substrate to a final lattice constant on the surface of the epitaxial layer. Growth surfaces are formed on the substrate, and the epitaxial layer is grown as its lattice constant changes from the initial lattice constant to the final lattice constant.Type: GrantFiled: January 30, 1985Date of Patent: October 22, 1985Inventor: Melvin S. Cook
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Patent number: RE33671Abstract: The mobility of a relatively narrow bandgap semiconductor material can be significantly enhanced by incorporating it into a multilayered structure (10) comprising a first plurality of relatively narrow bandgap layers (12) of the material and a second plurality of wider bandgap semiconductor layers (14) interleaved with and contiguous with the first plurality. The wide bandgap and narrow bandgap layers are substantially lattice-matched to one another, and the wide bandgap layers are doped such that the impurity concentration-thickness product therein is greater than the same product in the narrow bandgap layers. The fabrication of the structure by MBE to enhance the mobility of GaAs is specifically described. In this case, the narrow bandgap layers (12) comprise GaAs and are unintentionally doped to about 10.sup.14 /cm.sup.3, whereas the wide bandgap layers (14) comprise AlGaAs doped n-type to about 10.sup.16 to 10.sup.18 /cm.sup.3. The incorporation of this structure in an FET is also described.Type: GrantFiled: May 26, 1987Date of Patent: August 20, 1991Assignee: AT&T Bell LaboratoriesInventors: Raymond Dingle, Charles Gossard, Horst L. Stormer