Abstract: A multi-layered structure and process for forming it arc described, incorporating a single crystal substrate, a plurality of epitaxial layers having graded composition wherein the layers have changing lattice spacings not exceeding about 2 percent per 1000 .ANG. of thickness whereby misfit dislocations are formed to relieve strain and then move to the edges of respective layers. The invention overcomes the problem of large numbers of misfit dislocations threading to the surface of the top layer, especially during device processing at temperatures in a range from 700 to 900 degrees Celsius. Fully relaxed, incommensurate structures having low defect densities are obtained, where arbitrary combinations of materials can be used.

Abstract: The present invention broadly concerns layered structures of substantially-crystalline materials and processes for making such structures. More particularly, the invention concerns epitaxial growth of a substantially-crystalline layer of a first material on a substantially-crystalline second material different from the first material utilizing an approximately one monolayer thick monovalent surfactant element.

Abstract: A mixed crystal ratio difference is introduced in a gallium arsenide phosphide mixed crystal layer having a desired constant mixed crystal ratio, thereby reducing the amount of stress remaining within the resulting epitaxial wafer. This is less likely or unlikely to crack, and so can be well used for LED fabrication.

Abstract: A method of controlling a misfit dislocation in a process of producing an epitaxial semiconductor wafer comprising a semiconductor substrate and an epitaxial layer deposited on the semiconductor substrate, an impurity concentration of the epitaxial layer differing from that of the semiconductor substrate, has the step of controlling the amount of an extrinsic strain caused on the back surface of the semiconductor substrate prior to the step of depositing the epitaxial layer, thereby controlling an occurrence of misfit dislocation caused in and near the interface between the semiconductor substrate and the epitaxial layer.

Abstract: A high transconductance HFET (21) utilizes nonalloy semiconductor materials (26) to form a strained channel layer (26) that has a deep quantum well (38). The materials utilized for layers adjacent to the channel layer (26) apply strain to the channel layer (26) and create an excess of high mobility carriers in the channel layer (26). The materials also form a deep quantum well (38) that confines the high mobility carriers to the channel (26). The high mobility carriers and the high confinement provide an HFET (21) that has high transconductance, high frequency response, and sharp pinch-off characteristics.

Abstract: In order to grow single crystal, solid state devices onto a mismatched substrate, a secondary substrate is obtained by growing an epilayer divided into mesas (21) onto the primary substrate. The epilayer is annealed and this relieves the strain and causes dislocations to terminate preferentially on the sides of the mesas.

Abstract: Heterostructures having a large lattice mismatch between an upper epilayer and a substrate and a method of forming such structures having a thin intermediate layer are disclosed. The strain due to a lattice mismatch between the intermediate layer and the substrate is partially relieved by the formation of edge type dislocations which are localized and photoelectrically inactive. Growth of the intermediate layer is interrupted before it reaches the thickness at which the left over strain is relieved by 60 degree type threading dislocations. The upper epilayer is then grown in an unstrained and defect-free condition upon the intermediate layer where the unstrained lattice constant of the epilayer is about the same as the partially relieved strain lattice constant or the intermediate layer. An unstrained defect-free epilayer of InGaAs has been grown on a GaAs substrate with an intermediate layer 3-10 nm in thickness of InAs.

Abstract: A semiconductor device and processing technique is provided for monolithic integration of a single crystal compound element semiconductor on a ceramic substrate. A high resistivity semi-insulating buffer layer is epitaxially grown on the ceramic substrate and has an elastically transitional lattice constant matching at its lower surface the lattice constant of the ceramic substrate, and matching at its upper surface the lattice constant of the semiconductor layer.

Abstract: `Unintentionally` doped P type GaAs is grown on silicon by a metal organic chemical vapor deposition process in which the molecular ratio of arsenic to gallium in the growth ambient is reduced to a value that is sufficiently low to cause the creation of donor (As) site vacancies in the grown GaAs layer, which become occupied by acceptor (carbon) atoms in the metal organic compound, thereby resulting in the formation of a buffer GaAs layer having a P type majority carrier characteristic. Preferably, the silicon substrate has its growth surface inclined from the [100] plane toward the [011] direction is initially subjected to an MOCVD process (e.g. trimethyl gallium, arsine chemical vapor deposition) at a reduced temperature (e.g. 425.degree. C.) and at atmospheric pressure, to form a thin (400 Angstroms) nucleation layer. During this growth step the Group V/Group III mole ratio (of arsenic to gallium) is maintained at an intermediate value. The temperature is then ramped to 630.degree. C.

Abstract: Interstitial incorporation of Group III or Group V dopants, such as As, Sb, Ga, Al or B, in a III-V semiconductor, such as GaAs or Al.sub.x Ga.sub.1-x As, in the absence of any substitutional doping via a Group IV or Group VI dopant, will substantially eliminate, if not completely suppress, the formation of deep donor levels or DX centers in the III-V semiconductor.

Abstract: A method of growing a GaAs crystalline layer on a Si substrate by means of which mechanical stresses causing microcracks in the materials when cooled due to the difference in their thermal coefficients are reduced and the location of the microcrack is controlled to predetermined sites. Microcracks are deliberately induced in the GaAs layer at locations where the operation of the ultimate electronic device created on the material is not affected by applying to the substrate a SiO.sub.2 mask providing a deposition opening or window for the GaAs layer, which masks defines along the opening boundary at least one vertex in the cleavage direction of the GaAs crystals. The vertices in the mask create notches in the periphery of the deposited layer which determines the location of any microcracks.

Abstract: Dislocation densities are reduced in growing semiconductors from the vapor phase by employing a technique of interrupting growth, cooling the layer so far deposited, and then repeating the process until a high quality active top layer is achieved. The method of interrupted growth, coupled with thermal cycling, permits dislocations to be trapped in the initial stages of epitaxial growth.

Abstract: This is a method of fabricating a high-performance semiconductor device. The method comprises: forming a first insulating structure, preferably a layer of silicon nitride (e.g. region 24 in FIG. 2) on a layer of thermally grown oxide (e.g. region 22), on a substrate (e.g. region 20), preferably silicon; patterning and anisotropically etching the first insulating structure to expose a portion of the substrate and sidewalls of the first insulating structure; forming a second insulating structure, preferably a layer of oxide (e.g. region 28 in FIG. 3) on a layer of nitride (the bottom second insulating layer is preferably an etch-stop layer with respect to the removal of the top second insulating layer) (e.g. region 26 in FIG. 3), on the patterned first insulating structure, along the sidewalls of the first insulating structure, and on the exposed semiconductor substrate; anisotropically removing portions of the second insulating structure leaving a sidewall region of the second insulating structure (e.g.

Abstract: A method of fabricating a semiconductor heterostructure includes the growth of a quantum well active region that is highly lattice-mismatched relative to a substrate. A buffer layer having a thickness above a critical value is grown on the substrate whereby the stress due to a lattice constant mismatch between the buffer layer and substrate is relieved through the formation of misfit dislocations. A strained superlattice structure is grown on the buffer layer in order to terminate any upwardly-propagating dislocations. An unstrained barrier layer is subsequently grown on the superlattice structure. The fabrication method concludes with the growth of a quantum well structure on the unstrained layer wherein a lattice constant mismatch between the quantum well structure and the unstrained barrier layer is smaller than the lattice constant mismatch between the quantum well structure and the substrate.

Abstract: A heteroepitaxial growth method wherein a III-V group compound semiconductor is formed on a silicon substrate. A first amorphous III-V group compound semiconductor layer is formed on the silicon substrate before forming a III-V group compound semiconductor crystal layer on the amorphous III-V group compound semiconductor layer. A second amorphous III-V group semiconductor layer having a thickness greater than the crystal layer is formed on the III-V group compound semiconductor crystal layer and subjected to a solid phase epitaxial growth whereby the second amorphous III-V group compound semiconductor layer is made a single crystalline layer.

Abstract: A method for growing a superlattice structure on a substrate. First, a periodic array of monoatomic surface steps are created on the surface of the substrate at an area to have the superlattice structure grown thereon. There is apparatus for creating a beam of a material being input thereto and for selectively including or not including respective ones of a plurality of materials within the beam. The beam is directed at the steps of the substrate. Finally, logic causes control apparatus to include and not include respective ones of the materials within the beam in a pre-established pattern of time periods which will cause the materials to be deposited on the steps in a series of stacked monolayers. Tilted Superlattices (TSLs) and Coherent Tilted Superlattices (CTSLs) are created. The method can create pseudo ternary semiconductor alloys as part of a CTSL by employing at least two binary compound semiconductor alloys in the deposition process.

Abstract: A method for growing high quality epitaxial films using low pressure MOCVD that includes providing a substrate that is misoriented from a singular plane, placing the substrate into an MOCVD reactor at a total pressure of less than 0.2 atmospheres and then growing an epitaxial film on the substrate. When providing a misoriented gallium arsenide substrate, the MOCVD reactor is set at a temperature in the range of 650 to 750 degrees centigrade to grow an aluminum gallium arsenide film. This temperature is substantially lower than that at which aluminum gallium arsenide epitaxial films are commonly grown and the resulting film has a smooth surface morphology and enhanced photoluminesence properties.

Abstract: An image photodetector includes a photosensor unit, a charge storage unit, and a switch unit, all of them are formed on a single-crystal semiconductor film grown from a single nucleus such that crystal formation is performed on a substrate having a free surface including a non-nucleus formation surface and a nucleus formation surface adjacent thereto. The non-nucleus formation surface has a low nucleation density. The nucleus formation surface has a sufficiently small area to allow growth of only the single nucleus and has a higher nucleation density that that of the non-nucleus formation surface.

Abstract: The presence of oval defects on MBE-grown compound semiconductor (e.g., GaAs, InP, or InGaAs) epitaxial layers has proven to be a serious obstacle to the use of such material for the manufacture of integrated circuits (ICs), even though the use of such material potentially could result in ICs having superior performance. One particularly prevalent type of oval defect is generally referred to as .alpha.-type. It has now been discovered that compound semiconductor epitaxial layers that are essentially free of .alpha.-type oval defects can be grown by MBE if first at least a portion of the Ga and/or In metal crucible is coated with an appropriate second metal. The second metal is chosen from the group of metals that are wetted by the first metal and that are less electronegative than the first metal. Aluminum is a currently preferred second metal.

Abstract: A method of manufacturing a semiconductor device comprising at least the step of forming by a so-called method of deposition from the chloride vapour phase two superimposed epitaxial layers, the lower layer being made of a ternary compound and the upper layer being made of a binary compound, both of a semiconductor material of the III-V group, characterized in that the operating conditions of deposition temperature and molar fractions of the compounds required to form the layers are chosen so that both the lower layer of ternary material and the upper layer of binary material have before, during and after the transient state corresponding to the passage from the lower layer to the upper layer a maximum rate of coverage with chlorine (Cl) atoms.Application: hetero-structure GaInAs/InP for optoelectronic integrated circuits.

Abstract: An InP semiconductor thin film is formed by a process in which an amorphous GaAs buffer layer having a good surface flatness, and then an amorphous InP buffer layer having a good surface flatness are formed on an Si substrate, and then an InP monocrystalline thin film is grown on the InP buffer layer. GaAS has a lattice constant intermediate between Si used as the substrate and InP, so the lattice mismatch is reduced.

Abstract: A semiconductor wafer having an epitaxial GaAs layer, including a monocrystalline Si substrate having a major surface which is inclined at an off angle between 0.5.degree. and 5.degree. with respect to (100); and at least one intermediate layer epitaxially grown on the major surface of the monocrystalline Si substrate, as a buffer layer for accommodating a lattice mismatch between the Si substrate and the epitaxial GaAs layer which is epitaxially grown on a major surface of the top layer of the at least one intermediate layer. The at least one intermediate layer may comprise one or mor GaP/GaAsP, GaAsP/GaAs superlattice layers. the wafer may be used to produce a seimconductor light emitting element which has a plurality of crystalline gaAs layers including a light emitting layer epitaxially grown on the GaAs layer on the intermediate layer.

Abstract: An improved method of fabricating a defect-free semiconductor layer and a semiconductor on insulator structure is provided by forming an isoelectronically doped semiconductor layer between a substrate and an semiconductor layer. The isoelectronic dopant atoms are different in atomic size than the atoms of the semiconductor material, thus misfit dislocations are created at the interface of the isoelectronically doped semiconductor layer due to lattice mismatch. Impurities and defects are not only gettered to the misfit dislocation sites, but are also prevented from propagating to the epitaxial layer. These misfit dislocations are thermally stable and are confined in a plane parallel to the interfaces of the isoelectronically doped semiconductor layer, thus very effective gettering agents. If the isoelectroncially doped semiconductor layer us also a heavily doped buried layer, no misfit dislocations are desired because the buried layer is an active device layer.

Abstract: Films of Hg.sub.1-x Cd.sub.x Te grown at low temperatures by MBE or MOCVD are homogenized by annealing at about 350.degree. C. for 1.25 to 3 hours.

Abstract: A method of selective epitaxial growth includes a step of selectively forming an insulator film on a predetermined region of a semiconductor substrate and a step of evaporating a starting material containing a Group III element in vacuum in the presence of a Group V element to grow epitaxially a III-V compound semiconductor selectively on the semiconductor substrate under the condition where the partial pressure of the Group III element just above the semiconductor substrate is greater than the equilibrium vapor pressure of the Group III element contained in the III-V compound semiconductor existing on the semiconductor substrate and is smaller than the equilibrium vapor pressure of the Group III element contained in the III-V compound semiconductor existing on the insulator film.When InAs is grown epitaxially and selectively on a GaAs substrate, the GaAs substrate is kept at 500.degree. to 650.degree. C.

Abstract: A semiconductor apparatus is disclosed, in which the entire or part of an electron active region is formed by a superlattice structure semiconductor layer in which a plurality of different semiconductor layers, less than 8 monolayers, and containing a fraction or a binary compound semiconductor layers are alternately and epitaxially grown and a main current direction is selected to be in the direction perpendicular to the laminae of said superlattice layers.

Abstract: Intermediate buffer films having a low plastic deformation threshold are provided for absorbing defects due to lattice mismatch and/or thermal coefficient of expansion mismatch between a substrate or layer support and an overlayer while concurrently providing a good template for subsequent crystalline growth at the overlayer. This is accomplished for diamond cubic structure substrates, such as Si or Ge or Si on sapphire or crystalline Si on glass, upon which are to be deposited lattice mismatch overlayers, such as, GaAs or ZnSe. Also, zinc blend type substrates, such as GaAs or InP may be employed with such intermediate buffer films. A characteristic of these intermediate buffer films is a substantially lower plastic deformation threshold compared to either the substrate support or the overlayer to be grown heteroepitaxially thereon.

Abstract: A method of passivating Group III-V or II-VI semiconductor compound surfaces. The method includes selecting a passivating material having a lattice constant substantially mismatched to the lattice constant of the semiconductor compound. The passivating material is then grown as an ultrathin layer of passivating material on the surface of the Group III-V or II-VI semiconductor compound. The passivating material is grown to a thickness sufficient to maintain a coherent interface between the ultrathin passivating material and the semiconductor compound. In addition, a device formed from such method is also disclosed.

Abstract: A semiconductor epitaxial device structure is described in which there are alternate single crystal layers of semiconductor, insulator and semiconductor. A typical example is InP/CaF.sub.2 /InP. A process for producing such a structure is also described.

Abstract: A compound semiconductor device comprises a substrate formed from a single crystal of silicon, a layer of an insulator formed on a portion of a surface of the substrate, at least one layer of a high resistance compound semiconductor formed on the insulator layer, and at least one layer of a single crystal of a compound semiconductor formed on a different portion of the substrate surface from the insulator layer. The device can be manufactured by forming an insulator layer on one portion of a surface of a single crystal silicon substrate, and growing a compound semiconductor by epitaxy on the insulator layer and on the different portion from the insulator layer. One of useful applications is a hybrid semiconductor device having a compound semiconductor formed from e.g. GaAs on a silicon substrate.

Abstract: A low dislocation density semiconductor device includes a first semiconductor layer of a III-V or II-VI semiconductor compound and alloying atoms on a non-metal substrate. The semiconductor compound usually has a large dislocation density. A predetermined position of the alloying atoms in the compound lattice structure can substantially reduce the compound dislocation density. Energy is applied to the alloying atoms so they are at the predetermined positions. The number of alloying atoms causes the semiconductor compound solubility limit to be exceeded. The layer is formed on a substrate of the III-V or II-VI semiconductor, such as gallium arsenide or another semiconductor, such as silicon or on an insulator such as sapphire. In the latter cases, the layer is formed on an intermediate layer having a lattice constant between that of the substrate and semiconductor compound.

Abstract: Disclosed is a process for the production of a semiconductor element by introducing a gas of an organic metal compound of an element of the group III and a gas containing an element of the group V into a reaction chamber in which a substrate of a single crystal of alumina is arranged and epitaxially growing a III.V compound semiconductor by the thermal decomposition vapor deposition of the compound of the elements of the groups III.V, said process comprises, in combination, the steps of (A) heating the substrate at a temperature of 400.degree. to 550.degree. C., introducing the gas of the organic metal compound of the element of the group III and the gas containing the element of the group V into the reaction chamber and forming a film of a compound of the elements of the groups III.V on the surface of the substrate by the vapor deposition, (B) heating the substrate obtained at the step (A) at a temperature higher than 550.degree. C. but lower than 750.degree. C.

Abstract: A semiconductor photodetector, such as a PIN photodiode and an avalanche photodiode, comprising an InP substrate, a first InP layer, a GaInAs or GaInAsP light absorbing layer, and a second InP layer. All of the layers are successively grown by a vapor phase epitaxial process wherein the lattice constant of the GaInAs (GaInAsP) layer is larger than that of the InP layer at room temperature. The photodetector has a low dark current.

Abstract: A method for producing wafers having deposited layers of III-V materials on Si or Ge/Si substrates is disclosed. The method involves the use of multiple in situ and ex situ annealing steps and the formation of a thermal strain layer to produce wafers having a decreased incidence of defects and a balanced thermal strain. The wafers produced thereby are also disclosed.

Abstract: A GaAs layer having a high crystallinity can be grown over an Si substrate without warping, by process for growing a GaAs layer on an Si substrate, said process comprising: forming a first GaAs layer in the amorphous state on the Si substrate at a first temperature, the first GaAs layer being formed with a thickness allowing formation of a single crystalline layer having a thickness of one to three monomolecular layers; heating the first GaAs layer to change the amorphous state of the first GaAs layer to a single crystalline state; forming an Si layer on the first GaAs layer at a second temperature higher than the first temperature, the Si layer being formed with a thickness having one to six monoatomic layers; forming a second GaAs layer in the amorphous state on the Si layer at the first temperature, the second GaAs layer being formed with a thickness substantially the same as the thickness of the first GaAs layer; heating the second GaAs layer the change the amorphous state of the second GaAs layer to a si

Abstract: Polycrystalline silicon is deposited in a film onto the surface of a substrate which has been carefully prepared to eliminate any defects or contaminants which could nucleate crystal growth on the substrate. The deposition is carried out by low pressure decomposition of silane at substantially 580.degree. C. to cause a film of fine grained crystals of polysilicon to be formed having grain sizes averaging less than about 300 Angstroms after annealing. Such a film is very uniform and smooth, having a surface roughness less than about 100 Angstroms RMS. Annealing of the film and substrate at a low temperature results in a compressive strain in the field that decreases over the annealing time, annealing at high temperatures (e.g., over 1050.degree. C.) yields substantially zero strain in the film, and annealing at intermediate temperatures (e.g., 650.degree. C. to 950.degree. C.) yields tensile strain at varying strain levels depending on the annealing temperature and time.

Abstract: A semiconductor substrate and process for making are disclosed. The substrate is suitable for use in manufacturing large scale integrated circuits. The process comprises the steps of heating a semiconductor substrate at a temperature not lower than 1100.degree. C., implanting electrically inert impurities into the major surface of the substrate, heating the substrate at a temperature ranging from 600.degree. to 900.degree. C. and providing a single crystal semiconductor layer.

Abstract: A method of forming a semiconductor thin layer on a silicon substrate comprising the steps of depositing a first amorphous layer of a compound semiconductor (e.g., GaAs) on the silicon substrate, and growing a first epitaxial layer of the compound semiconductor on the amorphous layer, characterized in that the method comprises the steps of: after the epitaxial growth step, depositing a second amorphous layer of the compound semiconductor on the first epitaxial layer, and growing a second epitaxial layer of the compound semiconductor on the second amorphous layer. The obtained GaAs/Si substrate has a reduced dislocation density.

Abstract: The invention relates to a method of growing a GaAs film on the surface of a Si or GaAs substrate by exposing the growing surface of the substrate in a vacuum to at least one vapor beam containing the Ga elementary component of the GaAs compound, and to at least one vapor beam containing the As elementary component of the GaAs compound. The method is characterized by the steps of (A) growing a GaAs buffer layer by alternately applying the elements of the GaAs compound to the surface of a substrate heated to a first temperature one atom layer at a time, whereby in the formation of each atom layer the growing surface is exposed to a vapour beam containing one elementary component of the GaAs compound only; and (B) heating the substrate to a second temperature higher than the first temperature, and growing another GaAs layer on the buffer layer by applying both of the elementary components of the GaAs compound simultaneously.

Abstract: A heteroepitaxial growth method comprising growing a semiconductor single-crystal film on a semiconductor single-crystal substrate with a lattice constant different from that of the semiconductor single-crystal film by chemical vapor deposition, the epitaxial orientation of the semiconductor single-crystal film being inclined at a certain angle with respect to the semiconductor single-crystal substrate.

Abstract: An epitaxial wafer for producing arrays of GaAsP-LEDs comprises, in the GaAs.sub.1-x P.sub.x layer with varying X, a layer region(s) with a discontinuous variance of x along the thickness of the GaAs.sub.1-x P.sub.x layer. This layer region(s) contribute to a uniformity in the brightness of the light emission of LEDs formed in the epitaxial wafer.

Abstract: In organometallic vapor phase hetero-epitaxial processes for growing Al.sub.x Ga.sub.1-x N films on a sapphire substrate, the substrate is subjected to a preheat treatment of brief duration, such as less than 2 minutes, at relatively low temperatures in an atmosphere comprising Al-containing organometallic compound, NH.sub.3 and H.sub.2 gases, prior to the hetero epitaxial growth of Al.sub.x Ga.sub.1-x N films. Thus, single crystalline Al.sub.x Ga.sub.1-x N layers of high uniformity and high quality having smooth, flat surfaces are provided. Multi-layers grown according to the process of the invention are free from cracks and have preferable UV or blue light emission properties.

Abstract: A method for producing wafers having deposited layers of III-V materials on Si or Ge/Si substrates is disclosed. The method involves the use of multiple in situ and ex situ annealing steps and the formation of a thermal strain layer to produce wafers having a decreased incidence of defects and a balanced thermal strain. The wafers produced thereby are also disclosed.

Abstract: Group III-V multi-alloy semiconductors, such as ternary, quaternary, and pentanary semiconductors, grown on a binary group III-V compound semiconductor substrate, are used as an active layer in opto-devices, high electron mobility transistors, etc. A method of growing multilayers, lattice-matched to the binary substrate and having specific energy band gaps, includes a molecular beam epitaxy (MBE) process. The present invention includes growing a quaternary or pentanary semiconductor layer using a minimum number of effusion cells and eliminating readjustment of molecular beam intensities from one layer to another layer during a series of epitaxial growth steps. As an example of quaternary growth, four effusion cells are utilized and two combinations of three effusion cells are alternately operated, one including an Al effusion cell and the other including a Ga effusion cell. Each of the three effusion cells is capable of growing a ternary semiconductor lattice-matched to the substrate.

Abstract: A method, and products formed by such method, of providing a substantially planar surface to a layer of semiconducting material (24) formed on a first surface of a substrate (20), the substrate having a second surface opposite the first surface. The method comprising forming a layer (22) of a first material on the second surface of the substrate; forming a layer of the semiconducting material (24) on the first surface of the substrate; whereby said layer of said first material exerts a tensioning force on said second surface of the substrate (20) which countereffects a tensioning force exerted on said first surface of said substrate by said layer of semiconductor material (24) so that said first surface of said substrate has a substantially planar form. In some embodiments tensioning forces arise due to differential thermal expansion of said first material and said substrate and said semiconductor material and said substrate.

Abstract: A thin film bilayer composite source comprises a deposited impurity source layer, e.g. Si or Sb, heavily doped with a diffusion enabling agent, e.g. As, and capped with a passivating layer, e.g. Si.sub.3 N.sub.4, SiO.sub.2, AlN or SiO.sub.x N.sub.y. In a preferred embodiment, a thin film bilayer composite source comprises a Si layer on the surface of said structure vapor deposited at a temperature in excess of 500.degree. C. in the presence of a source of As to hevily dope the layer in the range of 5%-20% atomic weight and a thin cap layer of Si.sub.3 N.sub.4 deposited on the Si layer at a temperature in excess of 500.degree. C. having a thickness only sufficient to prevent the outdiffusion of Ga and As, which thickness may be about 400 .ANG.-700 .ANG.. An important aspect of the employment of this bilayer composite source as a diffusion source for III-V structures is that the composite source is initially deposited at high temperatures, above 500.degree.0 C., i.e.

Abstract: A method of making a semiconductor laser from a gallium arsenide substrate of a first conductivity type by depositing a first layer of semiconductor material having the composition Al.sub.x Ga.sub.1-x As of first conductivity type on the substrate and a thin second layer of semiconductor material for quantum confinement having the composition In.sub.y Ga.sub.1-y As on the first layer. This layer experiences sufficient strain in the semiconductor structure so as to minimize the threshold current density. The device is completed by depositing a third layer of semiconductor material having the composition Al.sub.x Ga.sub.1-x As and of second conductivity type on the second layer, and depositing a fourth layer of semiconductor material having the composition GaAs and of second conductivity type on the third layer.

Abstract: A component of semiconductor material deposited by epitaxial growth on a substrate having a predetermined and different lattice parameter consists of an alternate succession of layers of a first type and layers of a second type deposited on the substrate. The lattice parameter of the first type of layers is substantially matched with the lattice parameter of the substrate. In the case of the second type of layers, the lattice parameter is matched and even equal to that of the first type of layers. A component having a lattice parameter equal to that of the second type of layers is formed on the last layer of the second type. Moreover, the energy gaps of the two types of layers are different.

Abstract: Monolithic integration of Si MOSFETs and gallium arsenide MESFETs on a silicon substrate is described herein. Except for contact openings and final metallization, the Si MOSFETs are first fabricated on selected areas of a silicon wafer. CVD or sputtering is employed to cover the wafer with successive layers of SiO.sub.2 and Si.sub.3 N.sub.4 to protect the MOSFET structure during gallium arsenide epitaxy and subsequent MESFET processing. Gallium arsenide layers are then grown by MBE or MOCVD or VPE over the entire wafer. The gallium arsenide grown on the bare silicon is single crystal material while that on the nitride is polycrystalline. The polycrystalline gallium arsenide is etched away and MESFETs are fabricated in the single crystal regions by conventional processes. Next, the contact openings for the Si MOSFETs are etched through the Si.sub.3 N.sub.4 /SiO.sub.2 layers and final metallization is performed to complete the MOSFET fabrication.

Abstract: A semiconductor device comprising an epitaxially grown tin and Group IV compound semiconductor region on which at least one other semiconductor is grown lattice matched to the adjacent portion of the tin containing region. A large number of semiconductors may thus be grown.