Abstract: A removable rocker switch unit (1) has a housing (7) and an ON- and an OFF-position removably fixed to the first end of the housing (2). The rocker switch (3) has two pairs of vertically and horizontally aligned connector elements (4). The housing (7) provides two chambers, each chamber for each phase of the rocker switch (7) including a first and a second connecting elements (5, 8) in each chamber arranged to be connected by a fuse (9), a current limiter (9) or both in a series connection and/or by a varistor (9) between connecting elements (5, 8) of the two different phases.

Abstract: An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-processor node, a simultaneous buffering system is provided that allows all of the processors of the multi-processor node to operate at peak performance. A memory is shared among the nodes, with a portion of the memory resident at each of the multi-processor nodes. Each of the multi-processor nodes includes a number of elements for maintaining memory coherency, including a victim cache, a directory and a transaction tracking table. The victim cache allows for selective updates of victim data destined for memory stored at a remote multi-processing node, thereby improving the overall performance of memory.