Abstract: A method of fabricating a device is presented. The method includes forming a multilayer stack (101?, 102?, 103?) on a substrate (10?, 100?) which has a principal surface. The multilayer stack includes a supporting layer (102?) formed over the principal surface of the substrate and a photoresist layer (103?) formed on the supporting layer, patterning the multilayer stack to form at least one opening such that the photoresist layer is undercut by the supporting layer and anisotropically dry etching the substrate.

Abstract: Semiconductor devices are provided having large vias, such as under bonding pads, to increase the via open area ratio, increase the via etching rate, and avoid inter-metal dielectric cracking and damage to the integrated circuit. The via is defined as a large open area in the inter-metal dielectric layer between an isolated conductive bottom substrate layer and a conductive top layer. Methods of manufacturing semiconductor devices with a large via are also provided.

Abstract: A method of attaching a chip to the substrate with an outer layer consisting of via pillars embedded in a dielectric such as solder mask, with ends of the via pillars flush with said dielectric, the method consisting of optionally removing an organic varnish, positioning a chip having legs terminated with solder bumps in contact with exposed ends of the via pillars, and applying heat to melt the solder bumps and to wet the ends of the vias with solder.

Abstract: A method and system for integrated circuit fabrication is disclosed. In an example, the method includes determining a first process parameter of a wafer and a second process parameter of the wafer, the first process parameter and the second process parameter corresponding to different wafer characteristics; determining a variation of a device parameter of the wafer based on the first process parameter and the second process parameter; constructing a model for the device parameter as a function of the first process parameter and the second process parameter based on the determined variation of the device parameter of the wafer; and performing a fabrication process based on the model.

Abstract: A touch screen panel includes a substrate, a plurality of first electrodes formed on the substrate and extending along a first axis direction, a plurality of second electrodes formed on the substrate and extending along a second axis substantially perpendicular to the first axis; and a plurality of conducting connectors. Each conducting connector electrically couples with two neighboring second electrodes among the plurality of second electrodes in a same row without contacting the first electrodes.

Abstract: A touch screen panel includes a substrate, a plurality of first electrodes formed on the substrate and extending along a first direction, a plurality of second electrodes formed on the substrate and extending along a second direction substantially perpendicular to the first direction; and a plurality of conducting connectors. The conducting connectors are made of a metallic material. A surface of each conducting connector is processed by oxidation treatment for forming oxides, or treated by sulfidizing.

Abstract: A touch panel fabricating method is disclosed. A first conductive layer, a second conductive layer and a first photo-resist layer are sequentially formed on a substrate. Next, the first photo-resist layer is patterned by using a gray-level mask. Then, the first conductive layer and the second conductive layer are etched according to the patterned first photo-resist layer to define a plurality of first sensing electrodes. Then, an insulation layer is formed on the substrate and the first sensing electrodes. The insulation layer is patterned by using a gray-level mask. Then, a third conductive layer is formed on the patterned insulation layer. A second photo-resist layer is formed on the third conductive layer. The second photo-resist layer is patterned to expose partial third conductive layer. Then, the exposed third conductive layer is etched to define a plurality of second sensing electrodes.

Abstract: In order to provide a method of manufacturing a multilayer wiring substrate, a base member having a copper foil separably laminated thereon is prepared, and a solder resist layer is formed on the copper foil. Openings are formed in the solder resist layer, and a metal conductor portion is formed in each of the openings. By means of sputtering, a dissimilar metal layer is formed over the surface of the metal conductor portion and the entire surface of the solder resist layer. Copper electroplating is performed so as to form connection terminals and a conductor layer on the dissimilar metal layer. After a build-up step, the base material is removed, whereby the copper foil is exposed, and the exposed copper foil and the metal conductor portion are removed through etching, whereby the surfaces of the external connection terminals are exposed from the openings.

Abstract: A process for laser forming a blind via in at least one layer of a circuit substrate having a plurality of capture pads of varying geometry can include, for at least one blind via to be formed in at least one layer of a circuit substrate, evaluating a capture pad geometry value (such as area and/or volume) within a predetermined distance from a drilling location with respect to a blind via geometry value (such as area and/or volume) to be formed at the drilling location. The process can include setting at least one laser operating parameter based on the evaluation in order to obtain a desired capture pad appearance after blind via formation. The process can include imaging a capture pad area defined as an area within a predetermined distance from a blind via drilling location in at least one layer of a circuit substrate, quantifying at least one appearance value for the imaged capture pad area, and determining an acceptability of the imaged capture pad areas based on the quantified appearance value.

Abstract: A method of forming electrode structures comprising a plurality of electrode pads and a plurality of electrically conducting wires extending from the electrode pads. The method comprises coating an electrode structure with a relatively electrically insulating material, arranging each of the electrode pads in a first arrangement; arranging the wires relative to each other to provide a sufficient gap of separation between neighboring wires; securing the wires to a remotely positioned anchor member to preserve a gap of separation between neighboring wires, and applying a coating of relatively electrically insulating material to the electrode structure.

Abstract: A method of making templated circuitry employs a template system that includes a template of an insulator material on a carrier having a conductive surface. The template includes multiple levels and multiple regions, wherein a first level exposes the conductive surface of the carrier. A first metal is electrochemically deposited on the conductive surface in first regions of the first level. A circuit material is deposited to cover the first metal. The template is etched until a second level of the template exposes the conductive surface in second regions on opposite sides of the first regions. A second metal is electrochemically deposited on the conductive surface in the second regions. The template of deposited materials is transferred from the carrier to a substrate.

Abstract: A method for manufacturing a heat dissipation structure of a printed circuit board includes: forming a barrier layer on the dimple in the first copper plating layer; forming a nickel plating layer; removing the nickel plating layer and the barrier layer on the dimple; forming a second copper plating layer to make the total height of the first copper plating layer and the second copper plating layer in the second opening higher than that of the first copper plating layer in the first opening; filling the dimple in the second copper plating layer with an etching-resistant material; removing the second copper plating layer; removing the nickel plating layer and the etching-resistant material to make the second copper plating layer in the second opening being at the same height as the first copper plating layer in the first opening; and forming the heat dissipation structure by photolithography.

Abstract: A method for making a field emission double-plane light source includes following steps. A metallic based network, a pair of anodes, and a number of supporting members, are provided. Each of the anodes includes an anode conductive layer and a fluorescent layer formed on the anode conductive layer. A number of carbon nanotubes, metallic conductive particles, glass particles and getter powders are mixed to form an admixture. The admixture is coated on an upper surface and a bottom surface of the network. The admixture on the upper and bottom surfaces of the network is dried and baked. The anodes, the cathode, and the supporting members are assembled and sealed to obtain the field emission double-plane light source.

Abstract: A method realizes a multispacer structure including an array of spacers having same height. The method includes realizing, on a substrate, a sacrificial layer of a first material; b) realizing, on the sacrificial layer, a sequence of mask spacers obtained by SnPT, which are alternately obtained in at least two different materials; c) chemically etching one of the two different materials with selective removal of the mask spacers of this etched material and partial exposure of the sacrificial layer; d) chemically and/or anisotropically etching the first material with selective removal of the exposed portions of the sacrificial layer; e) chemically etching the other one of the two different materials with selective removal of the mask spacers of this etched material and obtainment of the multispacer structure.

Abstract: A structural body comprising a substrate and a structural layer formed on the substrate through an air gap in which the structural layer functions as a micro movable element is produced by a process comprising a film-deposition step of successively forming a sacrificial layer made of a silicon oxide film and the structural layer on the substrate, an air gap-forming step of removing the sacrificial layer by etching with a treating fluid to form the air gap between the substrate and the structural layer, and a cleaning step. By using a supercritical carbon dioxide fluid containing a fluorine compound, a water-soluble organic solvent and water as the treating fluid, the sacrificial layer is removed in a short period of time with a small amount of the treating fluid without any damage to the structural body.

Abstract: A multi-step etching process for a lead overlay structure such as a thin-film magnetic head structure using secondary ion mass spectroscopy (SIMS) whereby high selectivity of a lead material or other high conductivity metal layer is realized versus that of a metallic mask material and stopping layer. The first step includes patterning the mask layer using IBE or RIE. Advantageously, a photoresist layer is present over a portion of the mask layer and is left in place to be removed in a subsequent step. The second step includes etching the high conductivity metal layer using CAIBE or RIBE with an inert/reactive gas mixture and using SIMS to detect when the stopping layer is reached.

Abstract: A method for making multi-layer electronic circuit boards 64 having “blind” type apertures 28, 30 which may be selectively and electrically grounded and further having selectively formed air bridges and/or crossover circuits 45, 46.

Abstract: A metal layer, an etching resist and a photoresist are successively applied to an electrically insulating substrate. Whereupon the photoresist is patterned by photolithography in such a way that it covers a pattern of the later coarse conductor structures and the entire region of the later fine conductor structures. After the uncovered etching resist has been stripped, the photoresist is removed, whereupon the etching resist is patterned with the aid of a laser beam in such a way that it has the pattern of the fine conductor structures. The coarse conductor structures and the fine conductor structures are then formed in a common etching process.

Abstract: A fabricating method of semiconductor devices in which pads of a semiconductor chip of center-pad structure and bonding pads of a printed wired board are connected electrically. In an area of the printed wired board corresponding to the pads of the chip an extracting line for plating is formed, and circuit pattern electrically connecting the extracting line, terminal portions for external input/output and bonding pads is formed. The steps of electroplating the terminal portions and the bonding pads while supplying electricity from the extracting line, and removing the area of the printed wired board corresponding to the pads of the chip together with the extracting line to form a window portion are further comprised. A fabricating method of semiconductor devices in which to pads of a semiconductor chip of center-pad structure leads extending from circuit pattern of a printed wired board is connected.

Abstract: A multilayer circuit board having air bridge crossover structures and an additive method for producing the same, wherein the circuit includes specially designed metallic fortifying layers to mechanically and/or electrically fortify the circuit.

Abstract: A method for removing organometallic and organosilicate residues remaining after a dry etch process from semiconductor substrates. The substrate is exposed to a conditioning solution of phosphoric acid, hydrofluoric acid, and a carboxylic acid, such as acetic acid, which removes the remaining dry etch residues while minimizing removal of material from desired substrate features. The approximate proportions of the conditioning solution are typically 80 to 95 percent acetic acid, 1 to 15 percent phosphoric acid, and 0.01 to 5.0 percent hydrofluoric acid.

Abstract: A method for forming connections within a multi-layer electronic circuit board 10. In one non-limiting embodiment, the method includes selectively forming air bridges over portions of the circuit board 10 and selectively collapsing the air bridges with a metallurgical bonding tool, effective to interconnect layers of the circuit board 10.

Abstract: A multilayer circuit board having air bridge crossover structures and an additive method for producing the same, wherein the circuit includes specially designed metallic fortifying layers to mechanically and/or electrically fortify the circuit.

Abstract: A method for making a multi-layer electronic circuit board 136 having electroplated apertures 96, 98 which may be selectively and electrically isolated from an electrically grounded member 46 and further having selectively formed air bridges and/or crossover members 128 which are structurally supported by material 134.

Abstract: A process for manufacturing a chip carrier substrate, the process including the steps of providing a first layer of copper conductor on a substrate, forming a first layer of barrier metal on the first layer of copper conductor, forming a layer of aluminum on the first layer of barrier metal, forming a second barrier metal on the aluminum layer, patterning the top barrier metal in the form of studs, anodizing the aluminum unprotected by the top barrier metal, removing the aluminum oxide and patterning the first copper layer, removing all the exposed barrier metal; surrounding the studs and the copper conductor with a polymeric dielectric; polishing the polymeric dielectric to expose the studs; and forming a second layer of copper conductor on the planar polymeric dielectric.

Abstract: A method of manufacturing electronic components includes disposing a top metal layer (502) comprised of solder over a bottom metal layer (201, 202) comprised of titanium or tungsten, and selectively etching the bottom metal layer (201, 202) over the top metal layer (502) with an etchant mixture (601) comprised of an etchant, an additive to control the temperature of the etchant mixture (601), and another additive to reduce the redeposition of the top layer (502).

Abstract: A multilayer circuit board having strengthened air bridge crossover structures, and additive and subtractive methods for producing the same, wherein the circuit includes specially designed metallic fortifying layers to mechanically and/or electrically fortify the circuit. A preferred embodiment includes air bridge structures having generally T-shaped cross-sections, which provide strengthened, mechanically robust air bridges which are especially resistant to damage from flexure and displacement due to physical impact, bending, thermal excursions, and the like.

Abstract: There is disclosed herein a multilayer circuit board having air bridge crossover structures and a subtractive method for producing the same, wherein the circuit includes specially designed metallic fortifying layers which provide mechanical and/or electrical fortification to the circuit.

Abstract: A multilayer circuit board having strengthened air bridge crossover structures, and additive and subtractive methods for producing the same, wherein the circuit includes specially designed metallic fortifying layers to mechanically and/or electrically fortify the circuit. A preferred embodiment includes air bridge structures having generally T-shaped cross-sections, which provide strengthened, mechanically robust air bridges which are especially resistant to damage from flexure and displacement due to physical impact, bending, thermal excursions, and the like.

Abstract: An etched tri-metal-layer air bridge circuit board specially designed for fine-pitch applications, comprising: an electrically insulative substrate surface, a plurality of tri-metal-layer bond pads arranged in a generally straight row on the substrate surface wherein the row defines a width direction therealong, and a circuit trace arranged on the substrate surface, wherein the circuit trace runs between two adjacent ones of the plurality of tri-metal-layer bond pads. Each bond pad comprises: (1) a bottom layer attached to the substrate surface, the bottom layer being made of a first metal and having an overall width W1 as measured along the width direction; (2) a top layer disposed above and generally concentric with the bottom layer, the top layer being made of the first metal and having an overall width W2 as measured along the width direction; and (3) a middle layer made of a second metal connecting the bottom layer and the top layer.

Abstract: A method for providing a flexible lead for a microelectronic device. A lead such as nickel or a nickel alloy is provided in elongated strips on a base material such as copper, which in turn overlies a dielectric sheet. The base material is etched from beneath bond regions of the lead material strips and a cover layer of a bondable material such as gold selectively provided around the lead material strips. The lead material strips act as plating mandrels, and allow rapid deposition of the cover material. A detachment area may be provided in each lead so that the leads may be detached and displaced within a bonding window in the dielectric sheet for attachment to chip contacts.

Abstract: A thermal isolation microstructure fabricated by a process which allows the ultra thinning of support legs for the microdetector.

Abstract: An insulating layer with at least one via is provided over a metal plate. A sacrificial layer is applied over a portion of the insulating layer so that the sacrificial layer extends into the via. A metal bridge having at least one opening is provided over a portion of the sacrificial layer and a portion of the insulating layer so that the metal bridge extends over the via and the opening is situated adjacent a portion of the sacrificial layer. A reinforcing seal layer with a well is provided over the metal bridge so that the well is situated adjacent to at least a portion of the opening. The sacrificial layer is then removed.