Abstract: A method for manufacturing a film bulk acoustic resonator (FBAR) package with a thin film sealing structure includes: forming an FBAR having a bottom electrode, a piezoelectric layer, and a top electrode on a substrate; forming a plurality of inner pad electrodes electrically connected to the top electrode and the bottom electrode of the FBAR; attaching a PR (photo-resist) film to tops of the inner pad electrodes; etching the PR film to expose the inner pad electrodes to the outside; and forming a sealing layer on top of the PR film and tops of the exposed inner pad electrodes.

Abstract: An integrated circuit (IC) device includes a substrate and a circuit region over the substrate. The circuit region includes at least one active region extending along a first direction, at least one gate region extending across the at least one active region and along a second direction transverse to the first direction, and at least one first input/output (IO) pattern configured to electrically couple the circuit region to external circuitry outside the circuit region. The at least one first IO pattern extends along a third direction oblique to both the first direction and the second direction.

Abstract: An organic light-emitting display apparatus includes a plurality of first emission units, each including a first organic light-emitting device configured to emit light in at least a first direction and through a first display surface, a plurality of second emission units, each including a second organic light-emitting device configured to emit in a second direction opposite to the first direction and through a second display surface. The first emission units and the second emission units are alternately disposed. The apparatus further includes a transmissive area disposed adjacent to but not overlapping with the plurality of first emission units and the plurality of second emission units when viewed from a direction perpendicular to the first display surface, and capable of transmitting external light through the first and second display surfaces in the transmissive area.

Abstract: A semiconductor device includes a first transistor disposed over a substrate, a second disposed over the first transistor, and a conductive trace. The first transistor includes a first active area extending on a first layer. The second transistor includes a second active area extending on a second layer above the first layer. The conductive trace extends on a third layer. The first to third layers are separated from each other in a first direction, and the third layer is interposed between the first and second layers. The first active area, the second active area, and the conductive trace overlap in a layout view.

Abstract: Disclosed is a display device that is capable of being driven with low power consumption. A first thin-film transistor including a polycrystalline semiconductor layer and a second thin-film transistor including an oxide semiconductor layer are disposed in an active area, thereby reducing power consumption. At least one opening formed in a bending area is formed to have the same depth as any one of contact holes formed in the active area, thereby making it possible to form the opening and the contact holes through the same process and consequently simplifying the process of manufacturing the device. Since a high potential supply line and a low potential supply line overlap each other with a protective film formed of an inorganic insulation material interposed therebetween, short-circuiting of the high potential supply line and the low potential supply line may be prevented.

Abstract: An active matrix substrate includes a plurality of signal lines, each of which includes first and second line portions and an inner connection portion (connection portion) that connects the first and second line portions. The first and second line portions of one of two adjacent signal lines are made of first and second conductive layers, respectively, and the first and second line portions of the other of the two adjacent signal lines are made of second and first conductive layers, respectively. The position of the connection portion of each of the signal lines is determined in accordance with the layout position of that signal line in the line region.

Abstract: A varactor structure includes a substrate. A first and second gate structure are disposed on the substrate. The first and second gate structures each include a base portion and a plurality of line portions connected thereto. The line portions of each of the first and second gate structures is alternately arranged. A meander diffusion region is formed in the substrate and surrounds the line portions. A first set of contact plugs is planned with at least two columns or rows and disposed on the base portions of the first and second gate structures. A second set of contact plugs is planned with at least two columns or rows and disposed on the meander diffusion region. A first conductive layer is disposed on a top end of the first set of contact plugs. A second conductive layer is disposed on a top end of the second set of contact plugs.

Abstract: A semiconductor device includes a first gate line and a second gate line extending along a first direction, a third gate line extending along a second direction and between and directly contacting the first gate line and the second gate line, a drain region adjacent to one side of the third gate line, a fourth gate line extending along the second direction and between and directly contacting the first gate line and the second gate line, and a first metal interconnection extending along the second direction between the third gate line and the fourth gate line. Preferably, the third gate line includes a first protrusion and the fourth gate line includes a second protrusion.

Abstract: Methods/structures of forming substrate tap structures are described. Those methods/structures may include forming a plurality of conductive interconnect structures on an epitaxial layer disposed on a substrate, wherein individual ones of the plurality of conductive interconnect structures are adjacent each other, forming a portion of a seed layer on at least one of the plurality of conductive interconnect structures, and forming a conductive trace on the seed layer.

Abstract: An integrated circuit device includes a fin-type active region protruding from a top surface of a substrate and extending in a first direction parallel to the top surface of the substrate, a gate structure intersecting with the fin-type active region and extending on the substrate in a second direction perpendicular to the first direction, a source/drain region on a first side of the gate structure, a first contact structure on the source/drain region, and a contact capping layer on the first contact structure. A top surface of the first contact structure has a first width in the first direction, a bottom surface of the contact capping layer has a second width greater than the first width stated above in the first direction, and the contact capping layer includes a protruding portion extending outward from a sidewall of the first contact structure.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack and a source/drain contact structure formed over a substrate. A first gate spacer is separated the gate stack from the source/drain contact structure and extends above top surfaces of the gate stack and the source/drain contact structure. An insulating capping layer covers the top surface of the gate stack and extends on the top surface of the first gate spacer. A conductive via structure partially covers the top surface of the insulating capping layer and the top surface of the source/drain contact structure. A first insulating layer surrounds the conductive via structure and partially covers the top surface of the source/drain contact structure.

Abstract: Implementations of semiconductor packages may include: a die coupled to a substrate; a housing coupled to the substrate and at least partially enclosing the die within a cavity of the housing, and; a pin fixedly coupled to the housing and electrically coupled with the die, wherein the pin includes a reversibly elastically deformable lower portion configured to compress to prevent a lower end of the pin from lowering beyond a predetermined point relative to the substrate when the housing is lowered to be coupled to the substrate.

Abstract: A semiconductor device includes an enhancement-mode first p-channel MISFET, an enhancement-mode second p-channel MISFET, a drain conductor electrically and commonly connected to the first p-channel MISFET and the second p-channel MISFET, a first source conductor electrically connected to a source of the first p-channel MISFET, a second source conductor electrically connected to a source of the second p-channel MISFET, and a gate conductor electrically and commonly connected to a gate of the first p-channel MISFET and a gate of the second p-channel MISFET.

Abstract: Embodiments of the present application provide an integrated circuit and a layout method thereof. First, a first pitch of a first standard cell having a maximum gate length in multiple standard cells in an integrated circuit is determined. The first pitch is a distance between a central axis of a polysilicon gate in the first standard cell and central axes of virtual polysilicon gates in the first standard cell. Then, a distance between a polysilicon gate and virtual polysilicon gates in each of the standard cells is adjusted by using the first pitch and a gate length of each of the standard cells. After the adjustment, a distance between a central axis of the polysilicon gate in each of the standard cells and central axes of the virtual polysilicon gates in each of the standard cells is the same as the first pitch.

Abstract: A varactor structure includes a substrate. A first and second gate structure are disposed on the substrate. The first and second gate structures each include a base portion and a plurality of line portions connected thereto. The line portions of each of the first and second gate structures is alternately arranged. A meander diffusion region is formed in the substrate and surrounds the line portions. A first set of contact plugs is planned with at least two columns or rows and disposed on the base portions of the first and second gate structures. A second set of contact plugs is planned with at least two columns or rows and disposed on the meander diffusion region. A first conductive layer is disposed on a top end of the first set of contact plugs. A second conductive layer is disposed on a top end of the second set of contact plugs.

Abstract: Disclosed is a display device that is capable of being driven with low power consumption. A first thin-film transistor including a polycrystalline semiconductor layer and a second thin-film transistor including an oxide semiconductor layer are disposed in an active area, thereby reducing power consumption. At least one opening formed in a bending area is formed to have the same depth as any one of contact holes formed in the active area, thereby making it possible to form the opening and the contact holes through the same process and consequently simplifying the process of manufacturing the device. Since a high potential supply line and a low potential supply line overlap each other with a protective film formed of an inorganic insulation material interposed therebetween, short-circuiting of the high potential supply line and the low potential supply line may be prevented.

Abstract: A high-frequency apparatus includes a first device and a second device, and a mounting substrate on which the first and second devices are mounted. At least the second device is an acoustic wave device including a piezoelectric substrate and a functional element. The first device and the second device are adjacent to or in a vicinity of each other on the mounting substrate. A coefficient of linear expansion of a substrate of the first device is lower than a coefficient of linear expansion of the mounting substrate, and a coefficient of linear expansion of the piezoelectric substrate of the second device is higher than the coefficient of linear expansion of the mounting substrate.

Abstract: A reliable semiconductor device is provided. The semiconductor device includes at least one die. The at least one die includes an integrated circuit region, a first recess region surrounding the integrated circuit region, and a second recess region surrounding the first recess region. A first recess is disposed in the first recess region and a second recess is disposed in the second recess region.

Abstract: An active matrix substrate includes a plurality of signal lines, each of which includes first and second line portions and an inner connection portion (connection portion) that connects the first and second line portions. The first and second line portions of one of two adjacent signal lines are made of first and second conductive layers, respectively, and the first and second line portions of the other of the two adjacent signal lines are made of second and first conductive layers, respectively. The position of the connection portion of each of the signal lines is determined in accordance with the layout position of that signal line in the line region.

Abstract: A semiconductor structure includes a plurality of vias and a metal layer. The vias disposed on a semiconductor substrate. The metal layer has a plurality of metal lines and at least one transmission gate line region. The metal lines are connected to the vias. The at least one transmission gate line region is connected to at least one transmission gate corresponding to at least one transmission gate circuit. The transmission gate line region includes at least one different-net via pair. The different-net via pair has two metal lines and each of the two metal lines is connected to a via respectively. The two metal lines extend along a first axis but toward opposite directions. A distance between the two vias of the different-net via pair is within about 1.5 poly pitch.

Abstract: Stacked transistor structures and methods of forming same. In an embodiment, a stacked transistor structure has a wide central pedestal region and at least one relatively narrower channel region above and/or below the wider central pedestal region. The upper and lower channel regions are configured with a non-planar architecture, and include one or more semiconductor fins, nanowires, and/or nanoribbons. The top and bottom channel regions may be configured the same or differently, with respect to shape and/or semiconductor materials. In some cases, an outermost sidewall of one or both the top and/or bottom channel region structures, is collinear with an outermost sidewall of the wider central pedestal region. In some such cases, the outermost sidewall of the top channel region structure is collinear with the outermost sidewall of the bottom channel region structure. Top and bottom transistor structures (NMOS/PMOS) may be formed using the top and bottom channel region structures.

Abstract: Described herein are embedded dynamic random-access memory (eDRAM) memory cells and arrays, as well as corresponding methods and devices. An exemplary eDRAM memory array implements a memory cell that uses a thin-film transistor (TFT) as a selector transistor. One source/drain (S/D) electrode of the TFT is coupled to a capacitor for storing a memory state of the cell, while the other S/D electrode is coupled to a bitline. The bitline may be a shallow bitline in that a thickness of the bitline may be smaller than a thickness of one or more metal interconnects provided in the same metal layer as the bitline but used for providing electrical connectivity for components outside of the memory array. Such a bitline may be formed in a separate process than said one or more metal interconnects. In an embodiment, the memory cells may be formed in a back end of line process.

Abstract: A CIM bit cell circuit employing a capacitive storage circuit to store a binary weight data as a voltage occupies half or less of the area of a 6T SRAM CIM bit cell circuit, reducing the increase in area incurred in the addition of a CIM bit cell array circuit to an IC. The CIM bit cell circuit includes a capacitive storage circuit that stores binary weight data in a capacitor and generates a product voltage indicating a binary product resulting from a logical AND-based operation of the stored binary weight data and an activation signal. The capacitive storage circuit may include a capacitor and a read access switch or a transistor. The CIM bit cell circuit includes a write access switch to couple a write bit voltage to the capacitive storage circuit. In a CIM bit cell array circuit, the product voltages are summed in a MAC operation.

Abstract: The present disclosure provides an array substrate, a display panel, and a manufacturing method of the array substrate. The array substrate includes a substrate layer, an active layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, an interlayer insulating layer, an organic filling layer, and a third metal layer being stacked together. The meshed second metal layer is disposed in the display area, and a double-layer power voltage trace structure in the display area is formed by connecting the first via holes and power voltage signal lines of the third metal layer.

Abstract: A fuse latch of a semiconductor device is disclosed. The fuse latch of the semiconductor device includes a plurality of PMOS transistors and a plurality of NMOS transistors. The fuse latch includes PMOS transistors and NMOS transistors configured to latch fuse cell data. In the fuse latch, the plurality of PMOS transistors and the plurality of NMOS transistors are arranged in a shape of two lines in each active region in a second direction.

Abstract: A double-sided display panel and a method for manufacturing the same are provided. The double-sided display panel includes: a first substrate; a second substrate opposite to first substrate; a first display unit between the first substrate and the second substrate, the first display unit including a first luminescent layer and a first reflective layer which is closer to the second substrate than the first luminescent layer, wherein at least a part of light emitted from the first luminescent layer is reflected by the first reflective layer and emitted out through the first substrate; and a second display unit between the first substrate and second substrate, including a second luminescent layer, wherein light emitted from the second luminescent layer is emitted out through the second substrate. The first display unit includes a transparent electrode and a conductive contact layer which electrically connects the transparent electrode with the first reflective layer.

Abstract: Disclosed is a display device capable of being manufactured through a simplified process and having improved touch sensitivity. The display device includes an encapsulation unit disposed on a light-emitting element, a touch sensor disposed on the encapsulation unit, and an intermediate layer disposed between the encapsulation unit and the touch sensor. The intermediate layer includes a first intermediate layer, having a dielectric constant that is lower than a dielectric constant of an organic film disposed above or under the intermediate layer, and a second intermediate layer, having greater hardness than the first intermediate layer, whereby touch sensitivity is improved while processing is simplified.

Abstract: A method to form a 3D semiconductor device, the method including: providing a first level including first circuits, the first circuits including first transistors and first interconnection; preparing a second level including a silicon layer; forming second circuits over the second level, the second circuits including second transistors and second interconnection; transferring with bonding the second level on top of the first level; and then thinning the second level to a thickness of less than thirty microns, where the bonding includes oxide to oxide bonds, where the bonding includes metal to metal bonds, and where at least one of the metal to metal bond structures has a pitch of less than 1 micron from another of the metal to metal bond structures.

Abstract: The present disclosure proposes a thin film transistor and a related circuit. The thin film includes a gate, a drain and a source. The gate includes one or more gate units. The gate unit includes two or more strip-shaped gate branches, and a first gap is arranged between the two adjacent strip-shaped gate branches to separate them.

Abstract: A semiconductor device includes one or more fins. Each fin includes a top channel portion formed from a channel material, a middle portion, and a bottom substrate portion formed from a same material as an underlying substrate. An oxide layer is formed between the bottom substrate portion of each fin and the isolation layer, with a space between a sidewall of at least a top portion of the isolation dielectric layer and an adjacent sidewall of the one or more fins, above the oxide layer. A gate dielectric, protruding into the space and in contact with the middle portion, is formed over the one or more fins and has a portion formed from a material different from the oxide layer.

Abstract: A subfin layer is deposited on a substrate. A fin layer is deposited on the subfin layer. The subfin layer has a conduction band energy offset relative to the fin layer to prevent a leakage in the subfin layer. In one embodiment, the subfin layer comprises a group IV semiconductor material layer that has a bandgap greater than a bandgap of the fin layer.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip has a plurality of gate structures disposed over a substrate. A plurality of metal structures continuously extend from lower surfaces contacting the plurality of gate structures to upper surfaces contacting one or more interconnects within an overlying conductive interconnect layer. The plurality of metal structures are arranged at a first pitch that is larger than a second pitch of the plurality of gate structures.

Abstract: A method for manufacturing a semiconductor device includes following operations. A substrate including an active area is received. A plurality of source/drain regions of a plurality of transistor devices are formed in the active area. An isolation region is inserted between two adjacent source/drain regions of two adjacent transistor devices. The isolation region and the two adjacent source/drain regions cooperatively form two diode devices electrically connected in a back to back manner.

Abstract: A semiconductor device or structure includes a first pattern metal layer disposed between a first supply metal tract and a second supply metal tract, the first pattern metal layer comprising an internal route and a power route. A follow pin couples the first supply metal to the power route. The first supply metal tract comprises a first metal and a follow pin comprises a second metal.

Abstract: Some embodiments provide a novel compressive-sensing image capture device and a method of using data captured by the compressive-sensing image capture device. The novel compressive-sensing image capture device includes an array of sensors for detecting electromagnetic radiation. Each sensor in the sensor array has an associated mask that blocks electromagnetic radiation from portions of the sensor. In some embodiments, a diffractive mask is used to direct incoming light from a same object to different sensors in a sensing array. Some embodiments of the invention provide a dynamic mask array. In some embodiments, a novel machine trained network is provided that processes image capture data captured by the compressive-sensing image capture device to predict solutions to problems.

Abstract: An active matrix substrate includes a plurality of signal lines, each of which includes first and second line portions and an inner connection portion (connection portion) that connects the first and second line portions. The first and second line portions of one of two adjacent signal lines are made of first and second conductive layers, respectively, and the first and second line portions of the other of the two adjacent signal lines are made of second and first conductive layers, respectively. The position of the connection portion of each of the signal lines is determined in accordance with the layout position of that signal line in the line region.

Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.

Abstract: A semiconductor device includes a plurality of standard cells. The plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction and a second group of standard cells arranged in a second row extending in the row direction. The first group of standard cells and the second group of standard cells are arranged in a column direction. A cell height of the first group of standard cells in the column direction is different from a cell height of the second group of standard cells in the column direction.

Abstract: Disclosed is a display device that is capable of being driven with low power consumption. A first thin-film transistor including a polycrystalline semiconductor layer and a second thin-film transistor including an oxide semiconductor layer are disposed in an active area, thereby reducing power consumption. At least one opening formed in a bending area is formed to have the same depth as any one of contact holes formed in the active area, thereby making it possible to form the opening and the contact holes through the same process and consequently simplifying the process of manufacturing the device. Since a high potential supply line and a low potential supply line overlap each other with a protective film formed of an inorganic insulation material interposed therebetween, short-circuiting of the high potential supply line and the low potential supply line may be prevented.

Abstract: A first dielectric layer is selectively formed such that the first dielectric layer is formed over a source/drain region of a first type of transistor but not over a source/drain region of a second type of transistor. The first type of transistor and the second type of transistor have different types of conductivity. A first silicide layer is selectively formed such that the first silicide layer is formed over the source/drain region of the second type of transistor but not over the source/drain region of the first type of transistor. The first dielectric layer is removed. A second silicide layer is formed over the source/drain region of the first type of transistor.

Abstract: The present embodiment relates to an ion detector provided with a structure for suppressing degradation over time in an electron multiplication mechanism in a multi-mode ion detector. The ion detector includes a dynode unit, a first electron detection portion including a semiconductor detector having an electron multiplication function, a second electron detection portion including an electrode, and a gate part. The first and second electron detection portions are capable of ion detection at different multiplication factors. The gate part includes at least a final-stage dynode as a gate electrode, and controls switching between passage and interruption of secondary electrons which are directed toward the first electron detection portion by adjusting a set potential of the gate electrode.

Abstract: A semiconductor device includes a stacked structure disposed on a substrate. The stacked structure includes a plurality of gate electrodes. The semiconductor device further includes a first structure disposed on the substrate and passing through the stacked structure, and a second structure disposed on the substrate. The second structure is disposed outside of the stacked structure, faces the first structure, and is spaced apart from the first structure. The first structure includes a plurality of separation lines passing through at least a portion of the plurality of gate electrodes and extending outside of the stacked structure, and the second structure is formed of the same material as the first structure.

Abstract: A driving circuit, a display panel, and a display device are provided. The display panel comprises a plurality of common electrodes; a plurality of phototransistors, two or more phototransistors among the plurality of phototransistors being disposed in an area corresponding to each of the plurality of common electrodes; a plurality of photo-control lines electrically connected to a gate electrode of at least one phototransistor among the plurality of phototransistors; a plurality of photo-driving lines electrically connected to a first electrode of at least one phototransistor among the plurality of phototransistors, and a plurality of read-out lines, each of the plurality of read-out lines being electrically connected to a single common electrode among the plurality of common electrodes, and electrically connected to second electrodes of all of the phototransistors disposed in the area corresponding to the single common electrode to which each of the plurality of read-out lines are electrically connected.

Abstract: A method for manufacturing a semiconductor device includes forming a first vertical transistor on a semiconductor substrate, and forming a second vertical transistor stacked on the first vertical transistor. In the method, a silicide layer is formed on a first drain region of the first vertical transistor and on a second drain region of the second vertical transistor. The silicide layer electrically connects the first and second drain regions to each other.

Abstract: Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.

Abstract: Disclosed is a display device capable of being manufactured through a simplified process and having improved touch sensitivity. The display device includes an encapsulation unit disposed on a light-emitting element, a touch sensor disposed on the encapsulation unit, and an intermediate layer disposed between the encapsulation unit and the touch sensor. The intermediate layer includes a first intermediate layer, having a dielectric constant that is lower than a dielectric constant of an organic film disposed above or under the intermediate layer, and a second intermediate layer, having greater hardness than the first intermediate layer, whereby touch sensitivity is improved while processing is simplified.

Abstract: A standard integrated cell includes a semiconductor region with a functional domain for logic circuits including a transistor and an adjacent continuity domain that extends out to an edge of the standard integrated cell. The edge is configured to be adjacent to another continuity domain of another standard integrated cell. The standard integrated cell further includes a capacitive element. This capacitive element may be housed in the continuity domain, for example at or near the edge. Alternatively, the capacitive element may be housed at a location which extends around a substrate region of the transistor.

Abstract: An IC structure includes a first plurality of metal segments in a first metal layer, a second plurality of metal segments in a second metal layer overlying the first metal layer, and a third plurality of metal segments in a third metal layer overlying the second metal layer. The metal segments of the first and third pluralities of metal segments extend in a first direction, and the metal segments of the second plurality of metal segments extend in a second direction perpendicular to the first direction. A pitch of the third plurality of metal segments is smaller than a pitch of the second plurality of metal segments.

Abstract: A semiconductor cell structure includes four transistors, two gate-strips, four pairs of conductive segments, and a plurality of horizontal routing lines. Each of the two gate-strips intersects a first-type active zone and a second-type active zone. A first conductive segment is configured to have a first supply voltage. A second conductive segment is configured to have a second supply voltage. The first gate-strip is conductively connected to the second conductive segment. Each of the horizontal routing lines intersects one or more conductive segments over one or more corresponding intersections while conductively isolated from the one or more conductive segments at each of the one or more corresponding intersections.

Abstract: A system and method of designing an integrated circuit (IC) by considering a local layout effect are provided. The method of designing an IC may place instances of pre-placement cells so as to decrease occurrence of a local layout effect (LLE) causing structure. The method may extract a context of an instance from a peripheral layout of each of the placed instances to estimate an LLE of the instance, thereby analyzing a performance of the IC.