Abstract: A self-healing field-effect transistor (FET) device is disclosed in this application, the self-healing FET has a self-healing substrate, a self-healing dielectric layer, a gate electrode, at least one source electrode, at least one drain electrode, and at least one channel. The self-healing substrate and the self-healing dielectric layer have a disulfide-containing poly(urea-urethane) (PUU) polymer. The self-healing dielectric layer has a thickness of less than about 10 ?m. The electrodes have electrically conductive elongated nanostructures. The at least one channel has semi-conducting elongated nanostructures.

Abstract: An optical sensor includes: a photosensitive layer that absorbs incident light to generate a first carrier with a first polarity and a second carrier with a second polarity different from the first polarity; a channel layer that is electrically connected to the photosensitive layer and that conducts the first carrier that has moved from the photosensitive layer; a counter electrode facing the channel layer through the photosensitive layer; an insulating layer positioned between the photosensitive layer and the counter electrode; and a source electrode and a drain electrode each electrically connected to the channel layer.

Abstract: In a method of forming a gate-all-around field effect transistor (GAA FET), a fin structure is formed. The fin structure includes a plurality of stacked structures each comprising a dielectric layer, a CNT over the dielectric layer, a support layer over the CNT. A sacrificial gate structure is formed over the fin structure, an isolation insulating layer is formed, a source/drain opening is formed by patterning the isolation insulating layer, the support layer is removed from each of the plurality of stacked structures in the source/drain opening, and a source/drain contact layer is formed in the source/drain opening. The source/drain contact is formed such that the source/drain contact is in direct contact with only a part of the CNT and a part of the dielectric layer is disposed between the source/drain contact and the CNT.

Abstract: Described is an apparatus which comprises: a gate comprising a metal; a first layer adjacent to the gate, the first layer comprising a dielectric material; a second layer adjacent to the first layer, the second layer comprising a second material; a third layer adjacent to the second layer, the third layer comprising a third material including an amorphous metal oxide; a fourth layer adjacent to the third layer, the fourth layer comprising a fourth material, wherein the fourth and second materials are different than the third material; a source partially adjacent to the fourth layer; and a drain partially adjacent to the fourth layer.

Abstract: Disclosed herein are quantum dot devices with trenched substrates, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate having a trench disposed therein, wherein a bottom of the trench is provided by a first material, and a quantum well stack at least partially disposed in the trench. A material of the quantum well stack may be in contact with the bottom of the trench, and the material of the quantum well stack may be different from the first material.

Abstract: A method for fabricating a nanowire transistor includes the steps of first forming a nanowire channel structure on a substrate, in which the nanowire channel structure includes first semiconductor layers and second semiconductor layers alternately disposed over one another. Next, a gate structure is formed on the nanowire channel structure and then a source/drain structure is formed adjacent to the gate structure, in which the source/drain structure is made of graphene.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication. In an example, an integrated circuit structure includes a fin including silicon. A gate structure is over the fin, the gate structure having a center. A conductive source trench contact is over the fin, the conductive source trench contact having a center spaced apart from the center of the gate structure by a first distance. A conductive drain trench contact is over the fin, the conductive drain trench contact having a center spaced apart from the center of the gate structure by a second distance, the second distance greater than the first distance by a factor of three.

Abstract: A semiconductor device includes a substrate, a plurality of fins on the substrate, and an isolation region between the fins. Each of the fins includes a semiconductor material region and an impurity region disposed in the semiconductor material region. The impurity region has an upper surface below an upper surface of the isolation region.

Abstract: A semiconductor device includes a first stack of nanowires above a substrate with a first gate structure over, around, and between the first stack of nanowires and a second stack of nanowires above the substrate with a second gate structure over, around, and between the second stack of nanowires. The device also includes a first source/drain region contacting a first number of nanowires of the first nanowire stack and a second source/drain region contacting a second number of nanowires of the second nanowire stack such that the first number and second number of contacted nanowires are different.

Abstract: A field effect transistor (FET), a method of fabricating a field effect transistor, and an electronic device, the field effect transistor comprises: a source and a drain, the source being made of a first graphene film; a channel disposed between the source and the drain, and comprising a laminate of a second graphene film and a material layer having semiconductor properties, the second graphene film being formed of bilayer graphene; and a gate disposed on the laminate and electrically insulated from the laminate.

Abstract: A composite thread includes first and second segments joined to each other. The first segment comprises a functional segment that interacts with an environment of the thread. The second segment communicates information between the first segment and a point external to said composite thread.

Abstract: Novel and useful quantum structures having a continuous fully depleted well with control gates that form two quantum dot on either side of the gate. Appropriate potentials are applied to the well and control gate to control quantum tunneling between quantum dots thereby enabling quantum operations to occur. Qubits are realized by modulating applied gate potential to control tunneling through a quantum transport path between two or more sections of the well. Complex structures with a higher number of quantum dots per continuous well and a larger number of wells can be fabricated. Both planar and 3D FinFET semiconductor processes are used to build well to gate and well to well tunneling quantum structures. An injection device permits tunneling of a single quantum particle from a classic side to a quantum side of the device. Detection interface devices detect the presence or absence of a particle destructively or nondestructively.

Abstract: In a method of forming a gate-all-around field effect transistor (GAA FET), a bottom support layer is formed over a substrate and a first group of carbon nanotubes (CNTs) are disposed over the bottom support layer. A first support layer is formed over the first group of CNTs and the bottom support layer such that the first group of CNTs are embedded in the first support layer. A second group of carbon nanotubes (CNTs) are disposed over the first support layer. A second support layer is formed over the second group of CNTs and the first support layer such that the second group of CNTs are embedded in the second support layer. A fin structure is formed by patterning at least the first support layer and the second support layer.

Abstract: A semiconductor device, including a silicon on insulator (SOI) substrate is disclosed. The device may include gate structures formed on the SOI substrate and being spaced apart from each other in a horizontal direction, and a plurality of channels spaced apart from each other in a vertical direction. Each of the channels may extend through each of the gate structures in the horizontal direction. The device may include a seed layer and a source/drain region. The source/drain region may be connected to the channels, and each sidewall of the source/drain region in the horizontal direction may have a concave-convex shape. The device may include a protruding portion of the source/drain region formed between the gate structures that protrudes in the horizontal direction compared to a non-protruding portion of the source/drain region formed between the channels.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a plurality of first semiconductor layers and a plurality of second semiconductor layers on a substrate, and the first semiconductor layers and the second semiconductor layers are alternately stacked. The method also includes forming a dummy gate structure over the first semiconductor layers and the second semiconductor layers. The method further includes removing a portion of the first semiconductor layers and second semiconductor layers to form a trench, and removing the second semiconductor layers to form a recess between two adjacent first semiconductor layers. The method includes forming a dummy dielectric layer in the recess, and removing a portion of the dummy dielectric layer to form a cavity. The method also includes forming an inner spacer layer in the cavity.

Abstract: A device is disclosed that includes an insulating layer, a first electrode, a second electrode, and a bottom electrode. The insulating layer is disposed on a first surface of a substrate. The first electrode and the second electrode are disposed on a first surface of the insulating layer. The first electrode receives an input signal, and the second electrode outputs, in response to the input signal, an output signal. The bottom electrode is disposed on a second surface, opposite to the first surface, of the substrate and receives an operating voltage to modify a frequency of the output signal.

Abstract: Semiconductor nanowire devices having (111)-plane channel sidewalls and methods of fabricating semiconductor nanowire devices having (111)-plane channel sidewalls are described. For example, an integrated circuit structure includes a first semiconductor device including a plurality of vertically stacked nanowires disposed above a substrate, each of the nanowires comprising a discrete channel region having <111> lateral sidewalls along a <110> carrier transport direction. The integrated circuit structure also includes a second semiconductor device including a semiconductor fin disposed above the substrate, the semiconductor fin having a channel region with a top and side surfaces, the channel region having <111> lateral sidewalls along a <110> carrier transport direction.

Abstract: A semiconductor device includes a substrate, a channel stack, source/drain contacts, and a gate electrode. The channel stack is over the substrate and includes a 2D channel layer and a barrier layer. An energy band gap of the barrier layer is greater than an energy band gap of the 2D channel layer. The source/drain contacts are in contact with the channel stack. The gate electrode is above the substrate.

Abstract: A field-effect transistor (FET) includes a fin, an insulator region, and at least one gate. The fin has a doped first region, a doped second region, and an interior region between the first region and the second region. The interior region is undoped or more lightly doped than the first and second regions. The interior region of the fin is formed as a superlattice of layers of first and second materials alternating vertically. The insulator layer extends around the interior region. The gate is formed on at least a portion of the insulator region. The insulator layer and the gate are configured to generate an inhomogeneous electrostatic potential within the interior region, the inhomogeneous electrostatic potential cooperating with physical properties of the superlattice to cause scattering of charge carriers sufficient to change a quantum property of such charge carriers to change the ability of the charge carriers to move between the first and second materials.

Abstract: A semiconductor device includes a substrate; and a fin protruding from the substrate. The fin includes a first material and a second material. The fin includes a lower section, a middle section, and an upper section. The middle section has a smaller width at a middle portion than a width at lower and upper portions of the middle section. A concentration of the second material gradually decreases from the middle portion in upward and downward directions.

Abstract: According to one example, a method includes performing a Chemical Mechanical Polishing (CMP) process on a semiconductor workpiece that includes a nanosheet region, the nanosheet region having alternating layers of a first type of semiconductor material and a second type of semiconductor material. The method further includes stopping the CMP process when the first type of semiconductor material is covered by the second type of semiconductor material, patterning the nanosheet region to form nanosheet stacks, forming an isolation structure around the nanosheet stacks, removing a top layer of the second type of semiconductor material from the nanosheet stacks, recessing the isolation structure, and forming a gate structure over the nanosheet stacks.

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

Abstract: A microelectronic device includes a gated graphene component over a semiconductor material. The gated graphene component includes a graphitic layer having at least one layer of graphene. The graphitic layer has a channel region, a first connection and a second connection make electrical connections to the graphitic layer adjacent to the channel region. The graphitic layer is isolated from the semiconductor material. A backgate region having a first conductivity type is disposed in the semiconductor material under the channel region. A first contact field region and a second contact field region are disposed in the semiconductor material under the first connection and the second connection, respectively. At least one of the first contact field region and the second contact field region has a second, opposite, conductivity type. A method of forming the gated graphene component in the microelectronic device with a transistor is disclosed.

Abstract: A process for chemical mechanical polishing a substrate containing cobalt, zirconium oxide, poly-silicon and silicon dioxide, wherein the cobalt, zirconium, and poly-silicon removal rates are selective over silicon dioxide. The chemical mechanical polishing composition includes water, a benzyltrialkyl quaternary ammonium compound, cobalt chelating agent, corrosion inhibitor, colloidal silica abrasive, optionally a biocide and optionally a pH adjusting agent, and a pH greater than 7, and the chemical mechanical polishing compositions are free of oxidizing agents.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a base and a fin extending away from the base and including a quantum well layer. The device may further include a first gate disposed on a first side of the fin and a second gate disposed on a second side of the fin, different from the first side. Providing gates on different sides of a fin advantageously allows increasing the number of quantum dots which may be independently formed and manipulated in the fin. The quantum dots formed in such a device may be constrained in the x-direction by the one or more gates, in the y-direction by the fin, and in the z-direction by the quantum well layer, as discussed in detail herein. Methods for fabricating such devices are also disclosed.

Abstract: Semiconductor structures are provided. The semiconductor structure includes a fin structure formed over a substrate and an isolation structure formed around the fin structure. The semiconductor structure further includes a nanowire structure formed over the fin structure and a gate structure formed around the nanowire structure. In addition, a bottommost of the nanowire structure is lower than a top surface of the isolation structure.

Abstract: The current disclosure describes a new vertical tunnel field-effect transistor (TFET). The TFET includes a source layer over a substrate. A first channel layer is formed over the source layer. A drain layer is stacked over the first channel layer with a second channel layer stacked therebetween. The drain layer and the second channel layer overlap a first surface portion of the first channel layer. A gate structure is positioned over the channel layer by a second surface portion of the channel layer and contacts a sidewall of the second channel layer.

Abstract: A device includes a non-insulator structure, a first dielectric layer, and a first conductive feature. The first dielectric layer is over the non-insulator structure. The first conductive feature is in the first dielectric layer and includes carbon nano-tubes. The first catalyst layer is between the first conductive feature and the non-insulator structure. A top of the first catalyst layer is lower than a top of the first conductive feature.

Abstract: A method of forming a memory device that includes depositing a first dielectric material within a trench of composed of a second dielectric material; positioning a nanotube within the trench using chemical recognition to the first dielectric material; depositing a dielectric for cation transportation within the trench on the nanotube; and forming a second electrode on the dielectric for cation transportation, wherein the second electrode is composed of a metal.

Abstract: The present invention relates to a method for preparing an electrode comprising a metal substrate, vertically aligned carbon nanotubes and a metal oxide deposited over the entire length of said vertically aligned carbon nanotubes, said method comprising the following consecutive steps: (a) synthesizing, on a metal substrate, a mat of vertically aligned carbon nanotubes; and (b) depositing a metal oxide matrix over the entire height of said vertically aligned carbon nanotube mat via spontaneous reduction at a temperature not exceeding 40° C. The present invention also relates to said electrode and to the uses thereof.

Abstract: A method of forming a field effect transistor (FET) includes performing an oxidation on a nanosheet structure having alternating sheets of silicon and silicon germanium. An oxide etch is performed to remove portions of the sheets of silicon germanium. Other embodiments are also described herein.

Abstract: A capacitive element using VNW FETs is provided. First and second components each constituting a transistor are arranged in an X direction. From the first component, a first gate interconnect extends away from the second component, and a first top interconnect and a first bottom interconnect extend toward the second component. From the second component, a second gate interconnect extends toward the first component, and a second top interconnect and a second bottom interconnect extend away from the first component. The first top interconnect, the first bottom interconnect, and the second gate interconnect are connected.

Abstract: There are provided a nanometer semiconductor device with a high-quality epitaxial layer and a method of manufacturing the same. According to an embodiment, the semiconductor device may include: a substrate; at least one nanowire spaced apart from the substrate; at least one semiconductor layer, each formed around a periphery of respective one of the at least one nanowire to at least partially surround the corresponding nanowire, wherein the semiconductor layer(s) formed around the respective nanowire(s) are separated from each other; an isolation layer formed on the substrate, exposing the at least one semiconductor layer; and a gate stack formed on the isolation layer and intersecting the at least one semiconductor layer, wherein the gate stack includes a gate dielectric layer at least partially surrounding a periphery of respective one of the at least one semiconductor layer and a gate conductor layer.

Abstract: The present disclosure discloses a ballistic transport semiconductor device based on nano array and a manufacturing method thereof. The ballistic transport semiconductor device based on nano array comprises a conducting substrate, more than one semiconductor nano bump portion is arranged on a first surface of the conducting substrate, a top end of the semiconductor nano bump portion is electrically connected with a first electrode, a second surface of the conducting substrate is electrically connected with a second electrode, the second surface and the first surface are arranged back to back, and the height of the semiconductor nano bump portion is less than or equal to a mean free path of a carrier. The carrier is not influenced by various scattering mechanisms in a transporting procedure by virtue of the existence of ballistic transport characteristics, thereby obtaining a semiconductor device having advantages of lower on resistance, less working power consumption.

Abstract: Embodiments of the present invention provide improved methods and structures for fabrication of capacitor-less DRAM devices, sometimes referred to as ZRAM devices. A channel is formed in a fin-type field effect transistor (finFET) that is comprised of a finned channel portion and a convex channel portion. The finned channel portion may be comprised of a first semiconductor material and the convex channel portion may be comprised of a second, different semiconductor material. In embodiments, a metal gate is disposed around the elongated surface of the channel region, but is not disposed on the short surface of the channel region. A first spacer is disposed adjacent to the gate and in direct physical contact with the short surface of the channel region, and a second spacer is disposed adjacent to the first spacer.

Abstract: A semiconductor transistor device includes an emitter region that includes a plurality of metal quantum wires and is connected to an emitter terminal, a base region that includes a plurality of metal quantum wires and is connected to a base terminal, a collector region comprising a plurality of metal quantum wires and is connected to a collector terminal, an emitter barrier region between the emitter region and the base region, and a collector barrier region between the collector region and the base region.

Abstract: A device includes a substrate, a first doping portion, a second doping portion, a channel, a semiconductor film, a high-k layer, and a gate. The first doping portion and the second doping portion are over the substrate. The channel is over the substrate and between the first doping portion and the second doping portion. The semiconductor film is around the channel. The high-k layer is around the semiconductor film. The gate is over the high-k layer.

Abstract: A quantum well field-effect transistor (QWFET) includes a barrier layer, a quantum well layer, and a spacer layer. The quantum well layer is on the barrier layer. The barrier layer and the spacer layer comprise aluminum indium antimonide that is undoped. The quantum well layer comprises indium antimonide. The spacer layer is on the quantum well layer. The quantum well layer and the spacer layer are between a source contact and a drain contact. A gate contact is on a dielectric layer, which is on the spacer layer. By providing the barrier layer and the spacer layer as undoped layers, a performance of the QWFET may be improved.

Abstract: A technique relates to a semiconductor device. A stack includes two or more nanowires separated by a high-k dielectric material, the high-k dielectric material being formed on at least a center portion of the two or more nanowires in the stack. A separation space between the two or more nanowires is less than two times a thickness of the high-k dielectric material formed on a side wall of the two or more nanowires. A source or a drain formed on sides of the stack.

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to FinFET transistors. In one aspect, at least three fins are arranged to extend in parallel in a first direction and are laterally separated from each other in a second direction by shallow trench isolation structures having a first fin spacing, where at least a portion of each fin protrudes out from a substrate. At least a portion of each of a first fin and a second fin of the at least three fins vertically protrude to a level higher than an upper surface of the shallow trench isolation structures. A third fin is formed laterally between the first fin and the second fin in the second direction, where the third fin has a non-protruding region which extends vertically to a level below or equal to the upper surface of the shallow trench isolation structures.

Abstract: There are provided a nanometer semiconductor device with a high-quality epitaxial layer and a method of manufacturing the same. According to an embodiment, the semiconductor device may include: a substrate; at least one nanowire spaced apart from the substrate; at least one semiconductor layer, each formed around a periphery of respective one of the at least one nanowire to at least partially surround the corresponding nanowire, wherein the semiconductor layer(s) formed around the respective nanowire(s) are separated from each other; an isolation layer formed on the substrate, exposing the at least one semiconductor layer; and a gate stack formed on the isolation layer and intersecting the at least one semiconductor layer, wherein the gate stack includes a gate dielectric layer at least partially surrounding a periphery of respective one of the at least one semiconductor layer and a gate conductor layer.

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first semiconductor mesa formed on the semiconductor substrate within the first region; a second semiconductor mesa formed on the semiconductor substrate within the second region; and a field effect transistor (FET) formed on the semiconductor substrate. The FET includes a first doped feature of a first conductivity type formed in a top portion of the first semiconductor mesa; a second doped feature of a second conductivity type formed in a bottom portion of the first semiconductor mesa, the second semiconductor mesa, and a portion of the semiconductor substrate between the first and second semiconductor mesas; a channel in a middle portion of the first semiconductor mesa and interposed between the source and drain; and a gate formed on sidewall of the first semiconductor mesa.

Abstract: A semiconductor device includes a substrate, a channel layer, an insulating layer, source/drain contacts, a gate dielectric layer, and a gate electrode. The channel layer over the substrate and includes two dimensional (2D) material. The insulating layer is on the channel layer. The source/drain contacts are over the channel layer. The gate dielectric layer is over the insulating layer and the channel layer. The gate electrode is over the gate dielectric layer and between the source/drain contacts.

Abstract: In embodiments of the present disclosure, an ambient medium of a two-dimensional semiconductor is doped or an ambient medium of a semiconductor is locally filled with a solid material, to form a filled region, and an electronic device based on the two-dimensional semiconductor is implemented by means of a doping effect of the doped region or the filled region on a characteristic of the two-dimensional semiconductor. In the embodiments of the present disclosure, doping the two-dimensional semiconductor is not directly processing the two-dimensional semiconductor. Therefore, damage caused to the two-dimensional semiconductor in a doping process and device performance deterioration caused accordingly can be effectively reduced, and stability of device performance after doping is improved.

Abstract: Semiconductor devices and methods of forming the same include forming a stack of alternating first and second sacrificial layers. The first sacrificial layers are recessed relative to the second sacrificial layers. Replacement channel layers are grown from sidewalls of the first sacrificial layers. A first source/drain region is grown from the replacement channel layer. The recessed first sacrificial layers are etched away. A second source/drain region is grown from the replacement channel layer. The second sacrificial layers are etched away. A gate stack is formed between and around the replacement channel layers.

Abstract: A semiconductor device includes a substrate, an N-type bottom vertical gate-all-around (VGAA) transistor, a P-type bottom VGAA transistor, and a top VGAA transistor. The N-type bottom vertical gate-all-around (VGAA) transistor is over the semiconductor substrate and comprising a first nanowire made of InAs. The P-type bottom VGAA transistor is over the semiconductor substrate and comprising a second nanowire made of Ge. The top VGAA transistor is over the N-type bottom VGAA transistor, in which the top VGAA transistor includes a third nanowire in contact with the N-type bottom VGAA transistor, a fourth nanowire on and in contact with the third nanowire, and a bit line wrapping the fourth nanowire.

Abstract: The present disclosure provides a semiconductor structure, including a transistor. The transistor includes a semiconductive substrate, a gate structure, a pair of highly doped regions and a dielectric element. The semiconductive substrate has a top surface. The gate structure is over the top surface. The pair of highly doped regions is separated by the gate structure. The dielectric element is embedded in the semiconductive substrate. The dielectric element is laterally and vertically misaligned with the pair of highly doped regions.

Abstract: Field effect transistors and methods of forming the same include forming a stack of nanosheets of alternating layers of channel material and sacrificial material. A layer of sacrificial material forms a top layer of the stack. A dummy gate is formed over the stack. Stack material outside of a region covered by the dummy gate is removed. The sacrificial material is etched to form recesses in the sacrificial material layers. Spacers are formed in the recesses in the sacrificial material layers. At least one pair of spacers is formed in recesses above an uppermost layer of channel material. The dummy gates are etched away. The top layer of sacrificial material protects an uppermost layer of channel material from damage from the anisotropic etch. The sacrificial material is etched away to expose the layers of channel material. A gate stack is formed over, around, and between the layers of channel material.

Abstract: A negative capacitance field effect transistor (NCFET) and a manufacturing method thereof. The NCFET includes: a substrate structure, including a MOS region; a gate insulating dielectric structure, covering the MOS region; and a metal gate stack layer, covering the gate insulating dielectric structure. The gate insulating dielectric structure includes an interface oxide layer, a HfO2 layer, a doping material layer, and a ferroelectric material layer, which are sequentially stacked along a direction away from the substrate structure. A ferroelectric material in the ferroelectric material layer is HfxA1-xO2, A represents a doping element, and 0.1?x?0.9. A material forming the doping material layer is AyOz or A, and a ratio of y/z is equal to 1/2, 2/3, 2/5 or 1/1. Ferroelectric characteristics, material stability, and material reliability of the NCFET are improved by increasing domain polarity of the ferroelectric material.

Abstract: A biosensor comprising a substrate, a gate electrode provided on the substrate, an insulating layer provided on the gate electrode, a source electrode and a drain electrode, provided on the insulating layer, respectively, an n-type channel provided between the source electrode and the drain electrode, and a quantum dot layer provided on the n-type channel and provided so as to have electronic transition energy capable of resonating with vibration energy of a target biological material.