Abstract: Embodiments include apparatuses and methods related to a compound varactor. A first varactor in the compound varactor may include a collector layer and a first base layer that is arranged in a first plurality of parallel fingers. A second varactor in the compound varactor may include a second base layer arranged in a second plurality of parallel fingers, and the base layer may be coupled with the collector layer. In embodiments, the fingers of the base layers of the first varactor and the second varactor may be interleaved with one another. Other embodiments may be disclosed or claimed herein.

Abstract: Embodiments include apparatuses and methods related to a compound varactor. A first varactor in the compound varactor may include a collector layer and a first base layer that is arranged in a first plurality of parallel fingers. A second varactor in the compound varactor may include a second base layer arranged in a second plurality of parallel fingers, and the base layer may be coupled with the collector layer. In embodiments, the fingers of the base layers of the first varactor and the second varactor may be interleaved with one another. Other embodiments may be disclosed or claimed herein.

Abstract: A driving circuit that switches a light emitting element between an ON state and an OFF state in synchronization with an input signal is provided. The circuit includes a driving current supply unit that has a control terminal and supplies the light emitting element with a driving current whose value changes with dependency on the potential of the control terminal; a control unit that changes the potential of the control terminal in synchronization with the input signal; and a supplementary current supply unit that supplies the control terminal with a supplementary current that promotes change in the potential of the control terminal. The supplementary current supply unit has a capacitor, a voltage that is applied to the capacitor changes in synchronization with the input signal, and the supplementary current is generated by change in the voltage of the capacitor.

Abstract: A power semiconductor device includes: a first semiconductor layer; second and third semiconductor layers above and alternatively arranged along a direction parallel to an upper surface of the first semiconductor layer; and plural fourth semiconductor layers provided on some of immediately upper regions of the third semiconductor layer. An array period of the fourth semiconductor layers is larger than that of the second semiconductor layer. A thickness of part of the gate insulating film in an immediate upper region of a central portion between the fourth semiconductor layers is thicker than a thickness of part of the gate insulating film in an immediate upper region of the fourth semiconductor layers. Sheet impurity concentrations of the second and third semiconductor layers in the central portion are higher than a sheet impurity concentration of the third semiconductor layer in an immediately lower region of the fourth semiconductor layers.

Abstract: Disclosed herein is a metal e-fuse device that employs an intermetallic compound programming mechanism and various methods of making such an e-fuse device. In one example, a device disclosed herein includes a first metal line, a second metal line and a fuse element that is positioned between and conductively coupled to each of the first and second metal lines, wherein the fuse element is adapted to be blown by passing a programming current therethrough, and wherein the fuse element is comprised of a material that is different from a material of construction of at least one of the first and second metal lines.

Abstract: Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The first and third doped regions are of the same type sandwiching the second doped region of the second type. A first input terminal is coupled to the first and third doped regions and a second terminal is coupled to the second doped region. At the interfaces of the doped regions are first and second depletion regions whose width can be varied by varying the voltage across the terminals from zero to full reverse bias.

Abstract: An integrated circuit package system including: providing an integrated circuit die, forming a first layer over the integrated circuit die, forming a bridge on and in the first layer, forming a second layer on the first layer, and forming bump pads on and in the second layer, the bump pads connected to ends of the bridge.

Abstract: Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The second and third doped regions are of the same type sandwiching the first doped region of the second type. A first varactor terminal is coupled to the second and third doped regions and a second varactor terminal is coupled to the first doped region. At the interfaces of the doped regions are first and second depletion regions, the widths of which can be varied by varying the voltage across the terminals from zero to full reverse bias. At zero bias condition, junction capacitance (Cmax) is enhanced due to summation of two junction capacitances in parallel. At reverse bias condition, with the merging of the two junction depletion widths, the capacitor areas are drastically reduced, thereby reducing Cmin significantly.

Abstract: Methods and heterostructure barrier varactor (HBV) diodes optimized for application with frequency multipliers at providing outputs at submillimeter wave frequencies and above. The HBV diodes include a silicon-containing substrate, an electrode over the silicon-containing substrate, and one or more heterojunction quantum wells of alternating layers of Si and SiGe of one or more electrodes of the diode. Each SiGe quantum well preferably has a floating SiGe layer between adjacent SiGe gradients followed by adjacent Si layers, such that, a single homogeneous structure is provided characterized by having no distinct separations. The plurality of Si/SiGe heterojunction quantum wells may be symmetric or asymmetric.

Abstract: A wire embedded in a semiconductor substrate is covered with an insulating film, and a bias voltage is applied to the semiconductor substrate or to the wire to form a depletion layer extending from an edge of the insulating film. Alternatively, a semiconductor layer having a different conductivity type from the semiconductor substrate is formed within the semiconductor substrate to surround the insulating film.

Abstract: Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The second and third doped regions are of the same type sandwiching the first doped region of the second type. A first varactor terminal is coupled to the second and third doped regions and a second varactor terminal is coupled to the first doped region. At the interfaces of the doped regions are first and second depletion regions, the widths of which can be varied by varying the voltage across the terminals from zero to full reverse bias. At zero bias condition, junction capacitance (Cmax) is enhanced due to summation of two junction capacitances in parallel. At reverse bias condition, with the merging of the two junction depletion widths, the capacitor areas are drastically reduced, thereby reducing Cmin significantly.

Abstract: Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The first and third doped regions are of the same type sandwiching the second doped region of the second type. A first input terminal is coupled to the first and third doped regions and a second terminal is coupled to the second doped region. At the interfaces of the doped regions are first and second depletion regions whose width can be varied by varying the voltage across the terminals from zero to full reverse bias.

Abstract: A varactor is configured with first and second conducting layers, spaced apart from one another such that a given voltage can be applied across the first and second conducting layers. Further, an insulator arrangement includes at least one insulator layer disposed between the first and second conducting layers, configured to cooperate with the first and second conducting layers to produce a charge pool which changes responsive to changes in the given voltage such that a device capacitance value between the first and second conducting layers changes responsive to the given voltage. The insulator arrangement can include one layer, two distinct layers or more than two distinct layers. One or more of the layers can be an amorphous material. A zero-bias voltage version of the varactor is also described.

Abstract: It is an object to obtain a semiconductor device including a capacitance having a great Q-value. In an SOI substrate comprising a support substrate (165), a buried oxide film (166) and an SOI layer (171), an isolating oxide film 167 (167a to 167c) is selectively formed in an upper layer portion of the SOI layer (171) with a part of the SOI layer (171) remaining as a P? well region (169). Consequently, an isolation (partial isolation) structure is obtained. An N+ diffusion region (168) is formed in the SOI layer (171) between the isolating oxide films (167a) and (167b) and a P+ diffusion region (170) is formed in the SOI layer (171) between the isolating oxide films (167b) and (167c). Consequently, there is obtained a junction type variable capacitance (C23) having a PN junction surface of the P? well region (169) provided under the isolating oxide film (167b) and the N+ diffusion region (168).

Abstract: A varactor is provided. The varactor includes a second type substrate, two gate structures, a first type doped region and a second type doped region. The two gate structures are disposed over the substrate, and each of the gate structures includes an inter-gate dielectric layer and a gate conductive layer. The first type doped region is disposed in the substrate between the two gate structures. The second type doped region is disposed in the substrate at a side of the two gate structures apart from the first type doped region. The first type doped region is electrically connected to a first electrode, and second type doped region is electrically connected to a second electrode, and the two gate structures are electrically connected to the first electrode or the second electrode.

Abstract: A PN-junction varactor includes a first ion well of first conductivity type formed on a semiconductor substrate of second conductivity type. A first dummy gate is formed over the first ion well. A first gate dielectric layer is formed between the first dummy gate and the first ion well. A second dummy gate is formed over the first ion well at one side of the first dummy gate. A second gate dielectric layer is formed between the second dummy gate and the first ion well. A first heavily doped region of the second conductivity type is located in the first ion well between the first dummy gate and the second dummy gate. The first heavily doped region of the second conductivity type serving as an anode of the PN-junction varactor.

Abstract: A varactor diode having a first electrode comprising a well region of a first conductivity type in a substrate, a second electrode comprising a first plurality of diffusion regions of a second conductivity type abutting isolation regions disposed in said well region, and a second plurality of diffusion regions of said first conductivity type extending laterally from portions of said first plurality of diffusion regions not adjacent said isolation regions and having a dopant concentration greater than that of said first plurality of diffusion regions. The varactor has a tunability of at least approximately 3.5 in a range of applied voltage between approximately 0V to 3V, an approximately linear change in capacitive value in a range of applied voltage between approximately 0V to 2V, and a Q of at least approximately 100 at a circuit operating frequency of approximately 2 GHz.

Abstract: An integrated, tunable capacitor has terminal regions that extend significantly deeper into the semiconductor body than the customary source/drain terminal regions in the conventional CMOS varactors. For this purpose, by way of example, well-type regions or collector deep implantation regions may be provided, with which the depleted regions occurring in the event of large tuning voltages extend significantly further into the semiconductor body. The varactor with a large tuning range can be produced without additional outlay in mass production methods and can be used, for example, in phase-locked loops.

Abstract: A semiconductor device includes a plurality of barrier layers and a plurality of quantum well layers which are alternately interleaved with each other and disposed on a substrate of semiconductor material so as to form a multiple-heterojunction varactor diode. The barrier layers and quantum well layers are doped with impurities. The varactor diode includes an ohmic contact which is electrically connected to a heavily doped embedded region and a Schottky contact which is electrically connected to a depletion region of the diode. The ohmic contact and the Schottky contact enable an external voltage source to be applied to the contacts so as to provide a bias voltage to the varactor diode. A variable capacitance is produced as a result of the depletion region varying with a variation in the bias voltage. The varactor diode also provides a constant series resistance.

Abstract: An integrated, tunable capacitance is specified in which the quality factor is improved by virtue of the fact that, instead of source/drain regions, provision is made of highly doped well terminal regions having a deep depth, for example formed as collector deep implantation regions. This reduces the series resistance of the tunable capacitance. The integrated, tunable capacitance can be used for example in integrated voltage-controlled oscillator circuits in which a high quality factor is demanded.

Abstract: A varactor diode having a first electrode comprising a well region of a first conductivity type in a substrate, a second electrode comprising a first plurality of diffusion regions of a second conductivity type abutting isolation regions disposed in said well region, and a second plurality of diffusion regions of said first conductivity type extending laterally from portions of said first plurality of diffusion regions not adjacent said isolation regions and having a dopant concentration greater than that of said first plurality of diffusion regions. The varactor has a tunability of at least approximately 3.5 in a range of applied voltage between approximately 0V to 3V, an approximately linear change in capacitive value in a range of applied voltage between approximately 0V to 2V, and a Q of at least approximately 100 at a circuit operating frequency of approximately 2 GHz.

Abstract: A variable capacitor includes an N+ layer including a variable capacitance region, a P+ layer epitaxially grown on the N+ layer and formed from a SiGe film and a Si film, and a P-type electrode. An NPN-HBT (Hetero-junction Bipolar Transistor) includes a collector diffusion layer formed simultaneously with the N+ layer of the variable capacitor, a collector layer, and a Si/SiGe layer epitaxially grown simultaneously with the P+ layer of the variable capacitor. Since a depletion layer formed in a PN junction of the variable capacitor can extend entirely across the N+ layer, reduction in variation range of the capacitance can be suppressed.

Abstract: A varactor circuit having an increased tuning range comprises a first varactor in series with a second varactor between first and second terminals. A resistor is connected between the first and second terminals. A tap of the resistor is connected to a junction of the first and second varactors. This circuit effectively doubles tuning range compared to a single varactor.

Abstract: A memory device includes memory cells having two tunnel junctions in series. In order to program a selected memory cell, a first tunnel junction in the selected memory cell is blown. Blowing the first tunnel junction creates a short across the first tunnel junction, and changes the resistance of the selected memory cell from a first state to a second state. The change in resistance is detectable by a read process. The second tunnel junction has different anti-fuse characteristic than the first tunnel junction, and is not shorted by the write process. The second tunnel junction can therefore provide an isolation function to the memory cell after the first tunnel junction is blown.

Abstract: A voltage-variable capacitor is constructed from a metal-oxide-semiconductor transistor. The transistor source has at least two contacts that are biased to different voltages. The source acts as a resistor with current flowing from an upper source contact to a lower source contact. The gate-to-source voltage varies as a function of the position along the source-gate edge. A critical voltage is where the gate-to-source voltage is equal to the transistor threshold. A portion of the source has source voltages above the critical voltage and no conducting channel forms under the gate. Another portion of the source has source voltages below the critical voltage, and thus a conducting channel forms under the gate for this portion of the capacitor. By varying either the gate voltage or the source voltages, the area of the gate that has a channel under it is varied, varying the capacitance. Separate source islands eliminate source current.

Abstract: A varactor includes a semiconductor substrate of a first conductivity type, a high-concentration buried collector region of a second conductivity type formed in an upper portion of the semiconductor substrate, a collector region of the second conductivity type formed on a first surface of the high-concentration buried collector region, a high-concentration collector contact region of the second conductivity type formed on a second surface of the high-concentration buried collector region, a high-concentration silicon-germanium base region of the first conductivity type formed on the collector region, a metal silicide layer formed on the silicon-germanium base region, a first electrode layer formed to contact the metal silicide layer, and a second electrode layer formed to be electrically connected to the collector contact region.

Abstract: A termination structure for a superjunction device on which the net charge between P pylons in an N− termination region is intentionally unbalanced and is negative. The P pylons in the termination area are further non-uniformly located relative to those in the active area. A field ring which is an extension of the source electrode terminates at a radial mid point of the termination region.

Abstract: A varactor has a gate region, first and second biasing regions of N+ type embedded in a well, and first and second extraction regions of P+ type, forming a pair of PN junctions with the well. The PN junctions are inversely biased and extract charge accumulating in the well, below the gate region, when the gate region is biased to a lower voltage than a predetermined threshold value.

Abstract: A variable capacity device having an nin, pip, nn−p, np−p, or nip junction whose middle layer is constituted by a quantum-wave interference layer with plural periods of a first layer W and a second layer B as a unit. The second layer B has a wider band gap than the first layer W. Each thickness of the first layer W and the second layer B is determined by multiplying by an odd number one fourth of a wavelength of a quantum-wave of carriers in each of the first layer W and the second layer B existing around the lowest energy level of the second layer B. A &dgr; layer, for changing energy band suddenly, is formed at interfaces between the first layer W and the second layer B and has a thickness substantially thinner than the first layer W and the second layer B. Plurality of quantum-wave interference units are formed sandwiching carrier accumulation layers in series. Then a voltage-variation rate of capacity of the variable capacity device is improved.

Abstract: A MOS-type capacitor includes a semiconductor substrate of a first conductive type serving as a first electrode, a conductor layer formed on the semiconductor substrate via a capacitive insulation film and serving as a second electrode, and an impurity region of a second conductive type formed in the vicinity of the surface of the semiconductor substrate at a location in proximity to a region facing the conductor layer. The MOS-type capacitor is used as a variable capacitor in a VCO (voltage-controlled oscillator) having a widened frequency range.

Abstract: An electrical device having a voltage dependent capacitance is provided comprising a first region of a semiconductor material, and a second region and a third region of a semiconductor material formed in the first region, the second and third regions being separated by a separation region, and an electrically insulating layer formed on the first region at least at a region corresponding to the separation region, and a substantially conductive element formed on the insulating layer at least at a region corresponding to the separation region such that the insulating layer electrically insulates the substantially conductive element from the first, second and third regions, and a first electrode connected to the substantially conductive element, and a second electrode and third electrode are connected to the second and third regions. A method of manufacturing the device is also disclosed.

Abstract: The semiconductor device comprises a low-conductivity or insulating layer (5) on one surface of which is formed a conducting section (6) while the other face is provided with a hole- or electron-type semiconductor layer (1) with an ohmic contact. A semiconductor or metal layer (2) is provided on the surface of the semiconductor layer and with (1) forms a p-n junction or Schottky barrier with another ohmic contact. The choice of the alloy cross section and thickness of the layer (1) is restricted by the condition that said layer or part of it must be fully depleted by the basic charge carriers until breakdown of the p-n junction and/or the Schottky barrier when the latter is subjected to an external bias determined by the inequality shown in the application. The p-n junction and/or Schottky barrier can be formed with a non-homogeneous dopant section along a selected X direction on the surface of the layer (1).

Abstract: A voltage variable capacitor (10) fabricated on a semiconductor substrate (11) includes a gate structure (62) and a well (22) under the gate structure (62). A heavily doped buried layer (15) and a heavily doped contact region (31) in the semiconductor substrate (11) form a low resistance conduction path from the well (22) to a surface (17) of the semiconductor substrate (11). A multi-finger layout is used to construct the voltage variable capacitor (10). In operation, when a voltage applied across the voltage variable capacitor (10) changes, the width of depletion region in the well (22) changes, and the capacitance of the voltage variable capacitor (10) varies accordingly.

Abstract: A semiconductor device having the base and collector surrounded by a continuous tungsten filled slot as ground plane. The portion of the tungsten filled slot over the buried layer extends beyond the surface of the buried layer and the portion of the tungsten filled slot not over the buried layer extends beyond the interface between the epitaxial layer and the substrate.

Abstract: A varactor comprising a substrate of semiconductor material on which is grown both an electrostatic barrier having a first layer of material doped with donor impurities and a second layer of material doped with acceptor impurities and a depletable layer. In other embodiments of the present invention varactors are provided that include a plurality of barrier and depletable layer pairs grown in a serial arrangement.

Abstract: An area-variable varactor diode is disclosed, in which the capacitance can be arbitrarily varied under an applied bias voltage. The area-variable varactor diode is characterized in that, in order to ensure freedom to designing the epi-layer, to obtain the desired capacitance characteristics, and to facilitate the integration with other elements, a steeply varied depletion layer area is provided through a variation of the surface layout area, and thus, varied capacitance characteristics are obtained. In steeply varying the area of the depletion layer, an etching of the active layer, a selective epi-layer growth, and an ion implantation are carried out or a combination of them is carried out. The capacitance characteristics are varied in accordance with the pattern of the mask, and therefore, a restriction is not imposed on the epi-layer, with the result that an integration with other elements becomes easy.

Abstract: A semiconductor body has a first region of one conductivity type coupled to a first electrode. A second region of the opposite conductivity type is coupled to a second electrode and is provided within the first region to form a first pn junction with the first region. At least one further region of the opposite conductivity type is formed within the first region and spaced from the second region so as to form a further pn junction with the first region with each of the first and further pn junctions making a contribution to the capacitance of the diode. This capacitance varies during operation of the diode with a reverse-biasing voltage applied between the first and second electrodes.

Abstract: A variable-capacitance device has an n-type diffusion layer which has an impurity concentration profile such that a region where the impurity concentration remains substantially constant and a region where the impurity concentration changes abruptly are alternately repeated, and the impurity concentration increases as the deepness from the surface increases. The impurity concentration profile can be achieved by implanting n-type impurity atoms a plurality of times with different energies in an ion implantation process or varying the concentration of n-type impurity atoms such as of phosphorus added upon epitaxial layer growth. The variable-capacitance device, and a semiconductor integrated circuit device composed of a plurality of such variable-capacitance devices can be fabricated on a semiconductor substrate, and are highly stable.

Abstract: A notched insulation gate static induction transistor integrated circuit ording to the present invention comprises an enhancement mode CMOS logic circuit including a notched insulation gate static induction transistor in which a threshold voltage is determined to prevent current from flowing in a standby mode, and a depletion enhancement mode CMOS logic circuit including a notched insulation gate static induction transistor in which a threshold voltage is determined to cause current to slightly flow in the standby mode. The enhancement mode CMOS logic circuit and the depletion enhancement mode CMOS logic circuit are formed on a major surface of a substrate, and the depletion enhancement mode CMOS logic circuit is used in a circuit in which an average power consumption in a switching operation is higher than that in the standby mode.

Abstract: A plurality of variable-capacitance diode elements are formed in the top of a semiconductor substrate. The rear surface of the substrate is connected to a first lead frame that acts as a common electrode for one electrode from each of the variable-capacitance diode elements. Each of the other electrodes of the variable-capacitance diode elements is connected by a wire to a second lead frame. In this manner, a single variable-capacitance diode device is formed between the first and second lead frames by a plurality of variable-capacitance diode elements.