Abstract: In a gallium arsenide crystal body, an etching pit density of the gallium arsenide crystal body is more than or equal to 10 cm?2 and less than or equal to 10000 cm?2, and an oxygen concentration of the gallium arsenide crystal body is less than 7.0×1015 atoms·cm?3. In a gallium arsenide crystal substrate, an etching pit density of the gallium arsenide crystal substrate is more than or equal to 10 cm?2 and less than or equal to 10000 cm?2, and an oxygen concentration of the gallium arsenide crystal substrate is less than 7.0×1015 atoms·cm?3.

Abstract: Various examples are provided for radio frequency (RF) switching. In one example, a RF switch includes a dual-drive Mach-Zehnder modulator (DDMZM) that can generate a single-sideband (SSB) signal by modulating an input RF signal onto an optical carrier; a tunable phase modulator incorporated loop mirror filter (PM-LMF) that can optically notch filter the SSB signal in response to a control signal; and a photodetector (PD) that can generate a RF output signal based upon the SSB signal. In another example, a method includes modulating an input RF signal onto an optical carrier to generate a SSB signal; notch filtering the SSB signal by a tunable PM-LMF in response to a control signal; and generating a RF output signal based upon the SSB signal.

Abstract: A method for forming a resistive switching device. The method includes providing a substrate having a surface region and forming a first dielectric material overlying the surface region of the substrate. A first wiring structure overlies the first dielectric material. The method forms a first electrode material overlying the first wiring structure and a resistive switching material comprising overlying the first electrode material. An active metal material is formed overlying the resistive switching material. The active metal material is configured to form an active metal region in the resistive switching material upon application of a thermal energy characterized by a temperature no less than about 100 Degree Celsius. In a specific embodiment, the method forms a blocking material interposing the active metal material and the resistive switching material to inhibit formation of the active metal region in the resistive switching material during the subsequent processing steps.

Abstract: A phase change memory cell and a method for fabricating the phase change memory cell. The phase change memory cell includes a bottom electrode and a first non-conductive layer. The first non-conductive layer defines a first well, a first electrically conductive liner lines the first well, and the first well is filled with a phase change material in the phase change memory cell.

Abstract: The present invention relates to resistive memory devices incorporating therein vertical selection transistors and methods for making the same. A memory device comprises a semiconductor substrate having a first type conductivity and a plurality of parallel trenches therein; a plurality of parallel common source lines having a second type conductivity opposite to the first type conductivity formed in the trench bottoms; a plurality of parallel gate electrodes formed on the trench sidewalls with a gate dielectric layer interposed therebetween, the gate electrodes being lower in height than the trench sidewalls; and a plurality of drain regions having the second type conductivity formed in top regions of the trench sidewalls, at least two of the drain regions being formed in each of the trench sidewalls and sharing a respective common channel formed in the each of the trench sidewalls and a respective one of the source lines.

Abstract: Resistive memory having confined filament formation is described herein. One or more method embodiments include forming an opening in a stack having a silicon material and an oxide material on the silicon material, and forming an oxide material in the opening adjacent the silicon material, wherein the oxide material formed in the opening confines filament formation in the resistive memory cell to an area enclosed by the oxide material formed in the opening.

Abstract: Some embodiments include methods of forming memory cells. An opening is formed over a first conductive structure to expose an upper surface of the first conductive structure. The opening has a bottom level with a bottom width. The opening has a second level over the bottom level, with the second level having a second width which is greater than the bottom width. The bottom level of the opening is filled with a first portion of a multi-portion programmable material, and the second level is lined with the first portion. The lined second level is filled with a second portion of the multi-portion programmable material. A second conductive structure is formed over the second portion. Some embodiments include memory cells.

Abstract: Disclosed herein is a compact RRAM (Resistance Random Access Memory) device structure and various methods of making such an RRAM device. In one example, a device disclosed herein includes a gate electrode, a conductive sidewall spacer and at least one variable resistance material layer positioned between the gate electrode and the conductive sidewall spacer.

Abstract: The present disclosure provides systems and methods for configuring and constructing a single photo detector or array of photo detectors with all fabrications circuitry on a single side of the device. Both the anode and the cathode contacts of the diode are placed on a single side, while a layer of laser treated semiconductor is placed on the opposite side for enhanced cost-effectiveness, photon detection, and fill factor.

Abstract: A detector of periodic packets of X photons, each packet having a duration shorter than 0.1 nanosecond, comprising a sensor comprising a semiconductor element of type III-V biased in a negative differential resistance region, said sensor being arranged in a resonant cavity tuned to a multiple of the packet repetition frequency.

Abstract: Monolithic electronic device including a common nitride epitaxial layer are provided. A first type of nitride device is provided on the common nitride epitaxial layer including a first at least one implanted n-type region on the common nitride epitaxial layer. The first at least one implanted n-type region has a first doping concentration greater than a doping concentration of the common nitride epitaxial layer. A second type of nitride device, different from the first, including a second at least one implanted n-type region is provided on the common nitride epitaxial layer. The second at least one implanted n-type region is different from the first at least one implanted n-type region and has a second doping concentration that is greater than the doping concentration of the common nitride epitaxial layer. First and second pluralities of contacts respectively define first and second electronic devices on the common nitride epitaxial layer.

Abstract: A Gunn diode includes an active layer having a top and a bottom, a first contact layer disposed adjacent to the top of the active layer, a second contact layer disposed adjacent to the bottom of the active layer, wherein the first and second contact layers are more heavily doped than the active layer, and at least one outer contact layer disposed at an outer region of at least one of the first and second contact layers, the at least one outer contact layer being more heavily doped than the first and second contact layers, wherein the first and second contact layers, the active layer, and the at least one outer contact layer include a base material that is the same.

Abstract: A semiconductor device which displays an oscillating voltage due to the creation of charge domains which includes a plurality of semiconductor layers and at least two electrodes spaced from one another in the direction of the layers, an upper of which has a composition and/or dimensions predetermined so that a charge therein balances a depletion from a surface charge of the upper layer on application of a potential difference across said electrodes. The electrodes may be in contact solely with the upper layer. A method of manufacturing the device is also provided.

Abstract: A multilevel phase change memory may be formed of a chalcogenide material formed between a pair of spaced electrodes. The cross-sectional area of the chalcogenide material may decrease as the material extends from one electrode to another. As a result, the current density decreases from one electrode to the other. This means that a higher current is necessary to convert the material that has the largest cross-sectional area. As a result, different current levels may be utilized to convert different amounts of the chalcogenide material to the amorphous or reset state. A distinguishable resistance may be associated with each of those different amounts of amorphous material, providing the opportunity to engineer a number of different current selectable programmable states.

Abstract: An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage component contacts on a semiconductor component. Each interconnect contact includes a compliant conductive layer formed as a conductive spring element. In addition, the complaint conductive layer includes a tip for engaging the component contact and a spring segment portion for resiliently supporting the tip. A method for fabricating the interconnect includes the steps of shaping the substrate, forming a conductive layer on a shaped portion of the substrate and removing at least some of the shaped portion. The shaped portion can comprise a raised step or dome, or a shaped recess in the substrate. The conductive layer can comprise a metal, a conductive polymer or a polymer tape can include a penetrating structure or penetrating particles.

Abstract: The invention relates to a layered construction for a Gunn diode. The layered construction comprises a series of stacked layers consisting of a first highly doped nd GaAs layer (3), a graded AlGaAs layer (5), which is placed upon the first highly doped layer (3), whereby the aluminum concentration of this layer, starting from the boundary surface to the first nd GaAs layer (3), decreases toward the opposite boundary surface of the AlGaAs layer (5), and of a second highly doped n+ layer (7). An undoped intermediate layer (4, 6) serving as a diffusion or segregation stop layer is placed on at least one boundary surface of the AlGaAs layer (5) to one of the highly doped layers (3, 7) and prevents an unwanted doping of the graded layer.

Abstract: The present invention provides a photoresist stripper including about 5 wt % to about 20 wt % alcohol amine, about 40 wt % to about 70 wt % glycol ether, about 20 wt % to about 40 wt % N-methyl pyrrolidone, and about 0.2 wt % to about 6 wt % chelating agent.

Abstract: Disclosed herein is a method for fabricating an organic thin film transistor that includes a gate electrode, a gate insulating film, source/drain electrodes and an organic semiconductor layer formed in this order on a substrate wherein the surface of the gate insulating film on which source/drain electrodes are formed is impregnated with an inorganic or organic acid, followed by annealing. According to the method, the surface of a gate insulating film damaged by a photoresist process can be effectively recovered. In addition, organic thin film transistors having high charge carrier mobility and high on/off current ratio can be fabricated.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a substrate (110), as well as a nickel silicide region (170) located over the substrate (110), the nickel silicide region (170) having an amount of indium located therein.

Abstract: A semiconductor chip includes a base substrate, a bulk device region having a bulk growth layer on a part of the base substrate, an SOI device region having a buried insulator on the base substrate and a silicon layer on the buried insulator, and a boundary layer located at the boundary between the bulk device region and the SOI device region. The bulk device region has a first device-fabrication surface in which a bulk device is positioned on the bulk growth layer. The SOI device region has a second device-fabrication surface in which an SOI device is positioned on the silicon layer. The first and second device-fabrication surfaces are positioned at a substantially uniform level.

Abstract: A mask fabrication and repair technique including multiple exposures is provided. In this multiple exposure technique, the first exposure can define the critical dimensions (CDs) of the shapes for the mask. A subsequent exposure can eliminate isolated defects and significantly reduce the size of defects proximate to the desired shapes on the mask. Because similar processes (i.e. forming, exposing, and developing a photoresist layer) are used for creating and repairing the mask, certain repair-related defects, such as phase and transmission defects, can be minimized. Wafer repair can also be performed using the same multiple exposure technique.

Abstract: Multi-terminal field effect devices comprising a chalcogenide material. The devices include a first terminal, a second terminal and a field effect terminal. Application of a gate signal to the field effect terminal modulates the current passing through the chalcogenide material between the first and second terminals and/or modifies the holding voltage or current of the chalcogenide material between the first and second terminals. The devices may be used as interconnection devices in circuits and networks to regulate current flow between circuit or network elements.

Abstract: An asymmetrical virtual ground single transistor floating gate memory cell has a floating gate that overlies a channel region in a p-well, the channel region lying between a heavily doped n+ drain region and a lightly doped n? source region. A heavily doped p+ region known as a “halo” is disposed in the channel adjacent the heavily doped n+ drain. The floating gate is spaced away from the channel region by a generally thin tunnel oxide. A lightly doped source with a graded source/channel junction reduces source side CHE generation. In one variation, a thicker oxide between the source and the floating gate reduces CHE injection from the source side. A heavily doped drain with a halo implant in the channel adjacent the drain enhances drain side CHE generation.

Abstract: A semiconductor optical device includes, on a semiconductor substrate, a mesa-stripe-like multilayer structure constituted by at least an n-cladding layer, an active region formed from an active layer or a photoabsorption layer, and a p-cladding layer, and a buried layer in which two sides of the multilayer structured are buried using a semi-insulating semiconductor crystal. The buried layer includes a diffusion enhancement layer which is adjacent to the mesa-stripe-like multilayer structure and enhances diffusion of a p-impurity, and a diffusion suppression layer which is adjacent to the diffusion enhancement layer and suppresses diffusion of a p-impurity. A method of manufacturing a semiconductor optical device is also disclosed.

Abstract: A method of producing a particle beam mask and mask structures to allow for the use of dummy fill shapes. This invention overcomes distortion in by adding a dummy shape in unexposed regions and applying a blocking layer to cover the dummy shape. The blocking layer is comprised of an aperture or additional mask mounted close to the mask or can be added to the mask itself.

Abstract: An apparatus comprising control circuitry formed on a substrate, and a plurality of active media coupled to the control circuitry and formed in a plurality of planes over the substrate. A method comprising forming a pair of junction regions on a substrate separated by a channel length; and forming a channel material overlying and coupled to the pair of junction regions having a dimension at least equal to the channel length. An apparatus comprising a contact formed in a first plane over a device structure; and a device coupled to the contact and formed in a second plane a greater distance from the substrate than the first plane.

Abstract: Indium phosphor (InP) Gunn diode that realizes improvements in thermal characteristics, yield factor of good products and easy assembly to planar circuits is provided. In a Gunn diode of the present invention, contact layers are interposing an active layer. An anode electrode and a cathode electrode are formed on the uppermost contact layer. A high resistance region around the cathode electrode is formed at least in an uppermost contact layer by ion implantation using the cathode and anode electrode as a mask. A region under the cathode electrode functions as a Gunn diode and a region under the anode electrode function as a conductive path from the anode electrode to the active layer. These two regions are defined by the high resistance region.

Abstract: The present invention generally relates to improved binary half tone (“BHT”) photomasks and microscopic three-dimensional structures (e.g., MEMS, micro-optics, photonics, micro-structures and other three-dimensional, microscopic devices) made from such BHT photomasks. More particularly, the present invention provides a method for designing a BHT photomask layout, transferring the layout to a BHT photomask and fabricating three-dimensional microscopic structures using the BHT photomask designed by the method of the present invention. In this regard, the method of designing a BHT photomask layout comprises the steps of generating at least two pixels, dividing each of the pixels into sub-pixels having a variable length in a first axis and fixed length in a second axis, and arraying the pixels to form a pattern for transmitting light through the pixels so as to form a continuous tone, aerial light image.

Abstract: A method for forming small repeating structures, such as contact holes, is disclosed. The method comprises using a phase shift mask to perform a first exposure of a photoresist layer formed atop of a substrate. The phase shift mask includes etched regions and unetched regions. Next, the position of the phase shift mask is adjusted relative to the photoresist layer. A second exposure through the adjusted phase shift mask is performed on the photoresist layer. The photoresist is developed and is used as a mask for etching the substrate. After etch, the photoresist is stripped and cleaned. The resulted small sub-wavelength pattern is formed from the disclosed technique.

Abstract: An electronic device includes a FET that is capable of operating in a negative differential resistance mode as well as in a conventional FET mode. The selection of the mode can be accomplished by providing a control signal to a body terminal of the FET as needed for a particular application. By providing two different operating modes a multi-function logic gate is effectuated that can perform two or more different logical functions on an input signal. Furthermore the device can be used as an element of a new logic family and synthesized into suitable configurations so that more sophisticated and complex functions are achieved with increased density, lower power, etc. over conventional semiconductor FETs.

Abstract: A photolithographic mask used for defining a layer in an integrated circuit, or other work piece, where the layer comprises a pattern including a plurality of features to be implemented with phase shifting in phase shift regions is laid out including for patterns comprising high density, small dimension features, and for “full shift” patterns. The method includes identifying cutting areas for phase shift regions based on characteristics of the pattern. Next, the process cuts the phase shift regions in selected ones of the cutting areas to define phase shift windows, and assigns phase values to the phase shift windows. The phase shift values assigned comprise &phgr; and &thgr;, so that destructive interference is caused in transitions between adjacent phase shift windows having respective phase shift values of &phgr; and &thgr;. In the preferred embodiment, &phgr; is equal to approximately &thgr;+180 degrees.

Abstract: A Gunn diode which is formed by sequentially laminating a first semiconductor layer, an active layer and a second semiconductor layer onto a semiconductor substrate. The Gunn diode comprises first and second electrodes arranged on the second semiconductor layer for impressing voltage on the active layer, and a concave portion which is cut from around the first electrode in a direction of the second semiconductor layer and the active layer and which subdivides the second semiconductor layer and the active layer to which the first electrode is connected as a region which functions as a Gunn diode. Since etching for defining a region that is to function as a Gunn diode is performed by self-alignment dry etching utilizing electrode layers formed above this region as masks, variations in characteristics are restricted.

Abstract: A Gunn diode which is formed by sequentially laminating a first semiconductor layer, an active layer and a second semiconductor layer onto a semiconductor substrate. The Gunn diode comprises first and second electrodes arranged on the second semiconductor layer for impressing voltage on the active layer, and a concave layer portion which is cut from around the first electrode in a direction of the second semiconductor layer and the active layer and which subdivides the second semiconductor layer and the active layer to which the first electrode is connected as a region which functions as a Gunn diode. Since etching for defining a region that is to function as a Gunn diode is performed by self-alignment dry etching utilizing electrode layers formed above this region as masks, variations in characteristics are restricted.

Abstract: A Gunn diode which is formed by sequentially laminating a first semiconductor layer, an active layer and a second semiconductor layer onto a semiconductor substrate. The Gunn diode comprises first and second electrodes arranged on the second semiconductor layer for impressing voltage on the active layer, and a concave portion which is cut from around the first electrode in a direction of the second semiconductor layer and the active layer and which subdivides the second semiconductor layer and the active layer to which the first electrode is connected as a region which functions as a Gunn diode. Since etching for defining a region that is to function as a Gunn diode is performed by self-alignment dry etching utilizing electrode layers formed above this region as masks, variations in characteristics are restricted.

Abstract: A Gunn diode includes a layered structure including at least a cathode layer, an anode layer, and an active region interposed between the cathode and anode layers, wherein at least a portion of the active region is an AlGaAs layer.

Abstract: A method of manufacturing single-crystal silicon carbide/single-crystal silicon heterojunctions with negative differential resistance, by which one or more single-crystal silicon carbide/single-crystal silicon layer(s) with different types of dopants is/are formed on a silicon substrate, thereby forming new-type multiple negative differential resistance based on (a) single-crystal silicon carbide/single-crystal silicon heterojunction(s). The heterojunction(s) structure from top to bottom can be (1) Al/P--SiC/GCL/N--Si/Al; (2) Al/P--Si/GCL/P--SiC/GCL/N--Si/Al; and (3) Al/P--SiC/GCL/N--Si/GCL/P--SiC/GCL/N--Si/Al, wherein the GCL (Graded Reactant-gas Composition Ratio Layer) is a buffer layer formed between single-crystal silicon carbide layer and single-crystal silicon layer by gradually changing the composition of reaction gases. The structure and process of devices with negative differential resistance according to the invention are simpler than those of the prior art using Group III-V semiconductors.

Abstract: A low cost highly integrated method of fabricating a heat sink on the backside of a power semiconductor device maintains device performance, improves thermal transfer, and enables reliable planar connections without having to dice the wafer or package the discrete device-heat sink assembly. An etch stop layer is formed between the wafer and the frontside power devices to protect them during backside processing and to reduce the contact resistance between the device and its heat sink. The heat sinks are formed by thinning, patterning and then plating the wafer in such a manner that the devices can be released without dicing. The heat sinks are preferably oversized so that a vacuum tool can grasp the heat sink from above without damaging the device and then compression bond the heat sink onto a planar microstrip circuit assembly, which is designed and packaged to facilitate easy replacement of failed devices.

Abstract: A semiconductor body (2) has an active region (6) of n conductivity type formed of a material having a relatively low mass, high mobility conduction band main minimum and at least one relatively high mass, low mobility conduction band satellite minimum and an injector region (9) defining a potential barrier (P) to the flow of electrons into the active region (6) of a height such that, in operation of the device, electrons with sufficient energy to surmount the barrier (P) provided by the injector region (9) are emitted into the active region (6) with an energy comparable to that of the at least one relatively high mass, low mobility conduction band satellite minimum. An electron containing well region (10a, 10b) of a material different from that of the active region (6) and of the injector region (9) is provided between the injector region (9) and the active region (6) for inhibiting the spread of a depletion region into the active region (6) during operation of the device.

Abstract: The present invention (or multi-terminal lateral hot-electron transistor, ET) is based on a high electron mobility (hot-electron) transistor with a split-gate arrangement similar to those used in quantum wave guide devices. In the present invention, the depletion below the split gate is used to form, and control, potential barriers between the source and drain contacts. The devices, according to the present invention, exhibit pronounced SNDC which is controlled by the gate bias.

Abstract: A semiconductor structure comprises a first material layer of a homopolar material having a conduction band that includes an L valley and a .GAMMA. valley such that the L valley has an energy level lower than the .GAMMA. valley when in a bulk crystal state, and a second material layer of a polar compound formed with an epitaxial relationship with respect to the first material layer; wherein the first material layer has a thickness such that there is formed first and second quantum levels respectively in correspondence to the .GAMMA. valley and the L valley such that: the second quantum level has an energy level higher than the first quantum level.

Abstract: This invention is a three layer Si.sub.x Ge.sub.1-x structure formed on a silicon substrate in which a thin, lightly doped Si.sub.x Ge.sub.1-x layer is formed between two heavily doped Si.sub.x Ge.sub.1-x layers. The incorporation of at least 10% germanium in the silicon provides for intervalley scattering of carriers in the conduction band of the Si.sub.x Ge.sub.1-x layers. This intervalley scattering leads to the negative differential conductance necessary for transferred electron device (TED) operation. Additionally, the lightly doped Si.sub.x Ge.sub.1-x layer is made very thin, on the order of 2,000 to 7,000 Angstroms, and the current flow through the this layer is vertical so that a high electric field can be placed across the lightly doped layer without applying a high voltage across the lightly doped layer. The lightly doped layer can be made thin even though it is interposed between two heavily doped layers because the growth of the in-situ doped Si.sub.x Ge.sub.

Abstract: A Gunn diode in which the conversion efficiency can be improved without lowering the reliability, by reducing the dead zone while maintaining n.sup.+ nn.sup.+ structure. In this Gunn diode, the donor impurity concentration in the n-type active layer is graded along a direction perpendicular to a contact plane between the n-type active layer and the n.sup.+ -type layers, and an average concentration gradient of the donor impurity concentration in the n-type active layer simultaneously satisfies the following two inequalities: G>(A.sub.1 N/L)exp(-NL/S.sub.1) and G<(A.sub.2 N/L)exp(-NL/S.sub.2), where L is a thickness of the n-type active layer, N is an average concentration of the donor impurity, S.sub.1 =0.87.times.10.sup.12 cm.sup.-2 is a constant, S.sub.2 =1.32.times.10.sup.12 cm.sup.-2 is a constant, A.sub.1 =2.0 is a constant, and A.sub.2 =9.0 is a constant.

Abstract: A transferred electron effect device (1) has adjacent its cathode contact region (3) an injection zone (60) defining a potential barrier (P) for causing electrons to be emitted, under the influence of an electric field applied between the cathode and anode contact regions (3 and 4), into the active region (5) of the device with an energy comparable to that of a relatively high mass, low mobility satellite minimum (L) of the active region (5). The anode contact region (4), active region (5), injection zone (60) and cathode contact region (3) are grown sequentially, for example using molecular beam epitaxy, on a substrate which is then selectively removed to expose the anode contact region. A heat sink (70) is provided in thermal contact with the anode contact region (4). Providing the heat sink (70) in thermal contact with the anode contact region (4) rather than the cathode contact region (3) enables a significant increase in rf output power.