Abstract: A display device includes a metal layer, a boots layer, a passivation layer, and a conductive layer. The boots layer is located below the metal layer. The boots layer is partially overlapped with the metal layer. The passivation layer covers the metal layer and the boots layer. The conductive layer covers the passivation layer and the metal layer. The conductive layer is overlapped with the boots layer along a direction of the orthogonal projection.

Abstract: A transistor includes a body of semiconductor material, where the body has laterally opposed body sidewalls and a top surface. A gate structure contacts the top surface of the body. A source region contacts a first one of the laterally opposed body sidewalls and a drain region contacts a second one of the laterally opposed body sidewalls. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).

Abstract: Provided are a thin-film transistor substrate that has enhanced electrical characteristics, such as off-current characteristics of a thin-film transistor, without increasing the number of mask processes, a display apparatus, and a method of manufacturing the thin-film transistor substrate. The thin-film transistor substrate includes: a semiconductor layer including a first conductive region, a second conductive region, and a first semiconductor region; a lower electrode disposed on the semiconductor layer and at least partially overlapping the first semiconductor region; and an upper electrode disposed on the lower electrode and at least partially overlapping the first semiconductor region, a first boundary between the first semiconductor region and the first conductive region coincides with an edge of the upper electrode, and a second boundary between the first semiconductor region and the second conductive region coincides with an edge of the lower electrode or an edge of the upper electrode.

Abstract: A method of manufacturing a polycrystalline silicon layer for a display device includes the steps of forming an amorphous silicon layer on a substrate, cleaning the amorphous silicon layer with hydrofluoric acid, rinsing the amorphous silicon layer with hydrogenated deionized water, and irradiating the amorphous silicon layer with a laser beam to form a polycrystalline silicon layer.

Abstract: A die including a first contact with a first shape (e.g., ring-shaped) and a second contact with a second shape (e.g., cylindrical shaped) different from the first shape. The first contact has an opening that extends through a central region of a surface of the first contact. A first solder portion is coupled to the surface of the first contact and the first solder portion has the first shape. A second solder portion is coupled to a surface of the second contact and the second solder portion has the second shape. The first solder portion and the second solder portion both have respective points furthest away from a substrate of the die. These respective points of the first solder portion and the second solder portion are co-planar with each other such that a standoff height of the die remains consistent when coupled to a PCB or an electronic component.

Abstract: Provided are a display apparatus and a method of manufacturing the same. The display apparatus includes a substrate, a first conductive layer disposed on the substrate, and a first insulating pattern disposed on the first conductive layer. The first insulating pattern includes a fluorine compound and a nitrogen compound. The nitrogen compound is represented by Formula 1: NR1R2R3OH??<Formula 1> wherein in Formula 1, R1 to R3 are each independently selected from hydrogen, a substituted or unsubstituted C1-C20 alkyl group, a substituted or unsubstituted C6-C30 aryl group, and a substituted or unsubstituted C7-C30 aralkyl group.

Abstract: A system and method for efficiently creating layout for memory bit cells are described. In various implementations, cells of a library use Cross field effect transistors (FETs) that include vertically stacked gate all around (GAA) transistors with conducting channels oriented in an orthogonal direction between them. The channels of the vertically stacked transistors use opposite doping polarities. A first category of cells includes devices where each of the two devices in a particular vertical stack receive a same input signal. The second category of cells includes devices where the two devices in a particular vertical stack receive different input signals. The cells of the second category have a larger height dimension than the cells of the first category.

Abstract: An analyzer and a detection system are provided. The analyzer includes a chip placement structure and at least one detector unit. The chip placement structure is configured to place a detection chip, and the detection chip is provided with at least one detection area. The at least one detector unit is configured to detect one or more detection areas of the detection chip in a case where the detection chip is placed on the chip placement structure.

Abstract: A system and method for efficiently creating layout for memory bit cells are described. In various implementations, cells of a library use Cross field effect transistors (FETs) that include vertically stacked gate all around (GAA) transistors with conducting channels oriented in an orthogonal direction between them. The channels of the vertically stacked transistors use opposite doping polarities. One or more of these cells use a dual polarity local interconnect power connection to receive a voltage reference level from a backside bus. For example, a power supply reference voltage level is received by a p-type device from a backside bus where the connection traverses both a p-type local interconnect layer and an n-type local interconnect layer.

Abstract: An occupant protection device which can protect an occupant without delay is provided. An image taken by an imaging device is analyzed to judge whether there is an object approaching the subject car. In the case where a collision between the object and the subject car is judged to be inevitable, an airbag device is activated before the collision, whereby the occupant can be protected without delay. By using selenium for a light-receiving element of the imaging device, an accurate image can be obtained even under low illuminance. Imaging in a global shutter system leads to an accurate image with little distortion. This enables more accurate image analysis.

Abstract: A display device includes a first active pattern, a first conductive pattern including a gate electrode overlapping the first active pattern, a first gate line overlapping the first active pattern and extending in a first direction, and a second gate line extending in the first direction, a second conductive pattern disposed on the first conductive pattern and including a third gate line extending in the first direction and a fourth gate line extending in the first direction, a second active pattern disposed on the second conductive pattern and including a material different from a material of the first active pattern, and a third conductive pattern disposed on the second active pattern and including a first upper electrode overlapping the third gate line and connected to the third gate line, and a second upper electrode overlapping the fourth gate line and connected to the fourth gate line.

Abstract: An embodiment of a display device includes a display panel having a flexible characteristic and a rear passivation layer disposed on a rear surface of the display panel and including an opening, wherein a pixel is formed in an area of the display panel corresponding to the opening. The display panel includes: a flexible substrate including a polyimide layer and a barrier layer disposed on the polyimide layer; a driving transistor and a fifth transistor disposed on the substrate and including a polycrystalline semiconductor layer; a light emitting diode receiving an output current of the driving transistor; and a bottom metal layer disposed between the polyimide layer and the polycrystalline semiconductor layer in a cross-sectional view and disposed around a channel of the driving transistor in a plan view.

Abstract: Embodiments of methods and structures for forming a 3D integrated wiring structure are disclosed. The method can include forming an insulating layer on a front side of a first substrate; forming a semiconductor layer on a front side of the insulating layer; patterning the semiconductor layer to expose at least a portion of a surface of the insulating layer; forming a plurality of semiconductor structures over the front side of the first substrate, wherein the semiconductor structures include a plurality of conductive contacts and a first conductive layer; joining a second substrate with the semiconductor structures; performing a thinning process on a backside of the first substrate to expose the insulating layer and one end of the plurality of conductive contacts; and forming a conductive wiring layer on the exposed insulating layer.

Abstract: A display device includes a substrate including a pixel region and a peripheral region. A plurality of pixels is disposed in the pixel region of the substrate. Each of the plurality of pixels includes a light emitting element. Data lines and scan lines are connected to each of the plurality of pixels. A power line is configured to supply power to the plurality of pixels. The power line includes a plurality of first conductive lines and a plurality of second conductive lines intersecting the plurality of first conductive lines. The plurality of second conductive lines is arranged in a region between adjacent light emitting elements of the plurality of pixels. At least some of the plurality of second conductive lines extend in a direction oblique to a direction of extension of the data lines or the scan lines.

Abstract: The current disclosure describes a tunnel FET device including a P-I-N heterojunction structure. A high-K dielectric layer and a metal gate wrap around the intrinsic channel layer with an interlayer positioned between high-K dielectric layer and the intrinsic channel layer of the P-I-N heterojunction. The interlayer prevents charge carriers from reaching the interface with high-K dielectric layer under the trap-assisted tunneling effect and reduces OFF state leakage.

Abstract: A depletion-mode FeFET (“FeDFET”) is programmable to a first programmed state, under a first set of voltage biasing conditions, and to a second programmed state, under a second set of voltage biasing conditions. In both the first and second programmed states, the storage transistor has a threshold voltage that is not greater than 0 volts. A memory circuit may be organized as memory cells, with each memory cell including select transistors, transistor switches and FeDFETs in a static random-access memory (SRAM) cell configuration.

Abstract: Described herein are apparatuses, systems, and methods associated with metal-assisted transistors. A single crystal semiconductor material may be seeded from a metal. The single crystal semiconductor material may form a channel region, a source, region, and/or a drain region of the transistor. The metal may form the source contact or drain contact, and the source region, channel region, and drain region may be stacked vertically on the source contact or drain contact. Alternatively, a metal-assisted semiconductor growth process may be used to form a single crystal semiconductor material on a dielectric material adjacent to the metal. The portion of the semiconductor material on the dielectric material may be used to form the transistor. Other embodiments may be described and claimed.

Abstract: A transistor includes a gate electrode, an active layer facing the gate electrode, and a source electrode and a drain electrode connected to the active layer. The active layer includes a lower active layer including an oxide-based semiconductor material, and an upper active layer including the oxide-based semiconductor material and an oxygen-gettering material.

Abstract: An organic light emitting display device may include a substrate having a display area and a non-display area at least partially surrounds the display area, a pixel structure disposed in the display area on the substrate, a via insulating layer disposed in the non-display area on the substrate and having a contact hole, a lower pad disposed on the via insulating layer and a connecting structure. Here, the connecting structure may include a flexible substrate disposed on the lower pad, an upper pad disposed between the flexible substrate and the lower pad, and an upper dummy pad spaced apart from the upper pad in a first direction on a bottom surface of the flexible substrate.

Abstract: A display apparatus includes a substrate, an insulating layer, an alignment film, and a sealant. The insulating layer is disposed on the substrate and with a plurality of grooves. The alignment film is disposed on the insulating layer. The sealant is disposed on the alignment film. Wherein, the sealant overlaps at least a portion of the plurality of grooves. In a predetermined unit region, the side length of the predetermined unit region is a maximum width X of the sealant, and a total side length of the portions of the plurality of grooves located in the predetermined unit region is greater than 8 times of the maximum width X.

Abstract: A semiconductor device with high on-state current and high reliability is provided. The semiconductor device includes first to fifth insulators, first to third oxides, and first to fourth conductors; the fifth insulator includes an opening in which the second oxide is exposed; the third oxide is placed in contact with a bottom portion of the opening and a side portion of the opening; the second insulator is placed in contact with the third oxide; the third conductor is provided in contact with the second insulator; the third insulator is placed in contact with a top surface of the third conductor and the second insulator; and the fourth conductor is in contact with the third insulator and the top surface of the third conductor and placed in the opening.

Abstract: A display device and a method of manufacturing a display device are provided. A display device includes a lower conductive pattern disposed on a substrate, a lower insulating layer disposed on the lower conductive pattern, the lower insulating layer including a first lower insulating pattern including an overlapping region overlapping the lower conductive pattern, and a protruding region. The display device includes a semiconductor pattern disposed on the first lower insulating pattern and having a side surface, the side surface being aligned with a side surface of the first lower insulating pattern or disposed inward from the side surface of the first lower insulating pattern, a gate insulating layer disposed on the semiconductor pattern, a gate electrode disposed on the gate insulating layer, and an empty space disposed between the substrate and the protruding region of the first lower insulating pattern.

Abstract: The present disclosure provides a thin film transistor and a fabrication method thereof, an array substrate and a fabrication method thereof, and a display panel. The method for fabricating a thin film transistor includes: forming an active layer including a first region, a second region and a third region on a substrate; forming a gate insulating layer on a side of the active layer away from the substrate; forming a gate electrode on a side of the gate insulating layer away from the active layer; and ion-implanting the active layer from a side of the gate electrode away from the active layer, so that the first region is formed into a heavily doped region, the second region is formed into a lightly doped region, and the third region is formed into an active region.

Abstract: Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.

Abstract: Provided is a compound of Chemical Formula 1: wherein: L11 is a single bond or a substituted or unsubstituted C6-60 arylene; L12 and L13 are each independently a single bond or a substituted or unsubstituted C6-60 arylene; R11 is a substituted or unsubstituted C6-60 aryl; R12 and R13 are each independently any one substituent selected from the group consisting of the following: wherein, each R? is independently a substituted or unsubstituted C6-60 aryl, and R14 and R15 are hydrogen, or are linked to each other, and an organic light emitting device including the same.

Abstract: A transistor with stable electrical characteristics. A semiconductor device includes a first insulator over a substrate, a second insulator over the first insulator, an oxide semiconductor in contact with at least part of a top surface of the second insulator, a third insulator in contact with at least part of a top surface of the oxide semiconductor, a first conductor and a second conductor electrically connected to the oxide semiconductor, a fourth insulator over the third insulator, a third conductor which is over the fourth insulator and at least part of which is between the first conductor and the second conductor, and a fifth insulator over the third conductor. The first insulator contains a halogen element.

Abstract: A display device includes a driving transistor and an organic EL element. The driving transistor includes an oxide semiconductor layer; a first gate electrode that includes a region overlapping the oxide semiconductor layer; a first insulating layer between the first gate electrode and the oxide semiconductor layer; a second gate electrode that includes a region overlapping the oxide semiconductor layer and the first gate electrode; a second insulating layer between the second gate electrode and the oxide semiconductor layer; and a first and a second transparent conductive layer that are provided between the oxide semiconductor layer and the first insulating layer and each include a region contacting the oxide semiconductor layer. The organic EL element includes a first electrode; a second electrode; a light emitting layer between the first electrode and the second electrode; and an electron transfer layer between the light emitting layer and the first electrode.

Abstract: A display device may include a light emitting element, a buffer layer, a gate insulation layer, and a switching element. A refractive index of the gate insulation layer may be equal to a refractive index of the buffer layer. The switching element may be electrically connected to the light emitting element and may include an active layer and a gate electrode. The active layer may be positioned between the buffer layer and the gate insulation layer and may directly contact at least one of the buffer layer and the gate insulation layer. The gate insulation layer may be positioned between the active layer and the gate electrode and may directly contact at least one of the active layer and the gate electrode.

Abstract: The present disclosure provides a touch module, a display panel and a display apparatus. The display panel includes a substrate, a driving circuit structure layer, a light-emitting layer including a plurality of light-emitting regions and non-light-emitting regions, an encapsulation layer arranged on a surface of the light-emitting layers away from the substrate, an insulating dielectric layer with a plurality of hollow patterns penetrating the insulating dielectric layer, including a touch region, a peripheral signal trace region, and a frame region, touch electrode pattern, arranged on a surface of the insulating dielectric layer, located in the touch region and including a plurality of first touch electrodes and a plurality of second touch electrodes, and a plurality of touch signal lines distributed at intervals, electrically connected to the touch electrode patterns.

Abstract: According to one embodiment, a display device includes a first substrate, a second substrate and a liquid crystal layer. The first substrate includes a first insulating substrate, a scanning line, a signal line, a switching, and a pixel electrode. The liquid crystal layer includes a polymer in a shape of a streak and a liquid crystal molecule. The scanning line includes a conductive layer located between the first insulating substrate and the liquid crystal layer, and a first reflective layer located between the first insulating substrate and the conductive layer and having a reflectance higher than a reflectance of the conductive layer.

Abstract: A liquid crystal display is provided. The liquid crystal display includes a first substrate. The liquid crystal display also includes a plurality of first thin film transistors disposed on the first substrate. The liquid crystal display further includes a second substrate disposed opposite to the first substrate. In addition, the liquid crystal display includes a plurality of second thin film transistors disposed on the second substrate. The liquid crystal display also includes a plurality of sensing units disposed on the second substrate, and at least one of the plurality of sensing units electrically connected to at least one of the plurality of second thin film transistors. The liquid crystal display further includes a liquid crystal layer disposed between the first substrate and the second substrate.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. A lower portion of a stack is formed, with the stack ultimately comprising vertically-alternating first tiers and second tiers above the conductor tier. The stack comprises laterally-spaced memory-block regions. Material of the first tiers is of different composition from material of the second tiers. A lowest of the first tiers comprises conductive first sacrificial material. Conductive second material is directly electrically coupled to the conductive first sacrificial material. The conductive first sacrificial material and the conductive second material have different reduction potentials that are at least 0.5V away from one another. A lowest of the second tiers is insulative and below the lowest first tier. The vertically-alternating first tiers and second tiers of an upper portion of the stack are formed above the lower portion.

Abstract: A novel material and a transistor including the novel material are provided. One embodiment of the present invention is a composite oxide including at least two regions. One of the regions includes In, Zn and an element M1 (the element M1 is one or more of Al, Ga, Si, B, Y, Ti, Fe, Ni, Ge, Zr, Mo, La, Ce, Nd, Hf, Ta, W, Mg, V, Be, and Cu) and the other of the regions includes In, Zn, and an element M2 (the element M2 is one or more of Al, Ga, Si, B, Y, Ti, Fe, Ni, Ge, Zr, Mo, La, Ce, Nd, Hf, Ta, W, Mg, V, Be, and Cu). In an analysis of the composite oxide by energy dispersive X-ray spectroscopy, the detected concentration of the element M1 in a first region is less than the detected concentration of the element M2 in a second region, and a surrounding portion of the first region is unclear in an observed mapping image of the energy dispersive X-ray spectroscopy.

Abstract: Disclosed are a photodetector using a photoelectric conversion effect wherein current changes according to light; and a method of manufacturing the photodetector. More particularly, a photodetector manufactured using a transition metal dichalcogen compound having high sensitivity to wavelengths of light in the visible light region by forming a sensor layer utilizing a transition metal dichalcogen compound such that the thickness of the sensor layer can be adjusted is provided.

Abstract: Disclosed is a method of manufacturing a gallium oxide thin film for a power semiconductor using a dopant activation technology that maximizes dopant activation effect and rearrangement effect of lattice in a grown epitaxial at the same time by performing in-situ annealing in a growth condition of a nitrogen atmosphere at the same time as the growth of a doped layer is finished.

Abstract: A display substrate and a display device are provided. The display substrate includes sub-pixels which are arranged in a sub-pixel array in a first direction and a second direction. At least one sub-pixel includes a first transistor, a second transistor, a third transistor, and a storage capacitor. An active layer of the third transistor includes a body region and a first via hole region successively arranged in the first direction and electrically connected with each other; a first electrode of the third transistor is electrically connected to the first via hole region through a first via hole which is shifted in the second direction with respect to the body region, allowing the active layer incudes a first active layer side connecting the body region and the first via hole region; an extension direction of the first active layer side intersects with both the first direction and the second direction.

Abstract: A semiconductor device includes a first substrate, circuit devices disposed on the first substrate, a first interconnection structure electrically connected to the circuit devices, a second substrate disposed on an upper portion of the first interconnection structure, gate electrodes spaced apart from each other and stacked on the second substrate in a direction perpendicular to an upper surface of the second substrate, and channel structures penetrating the gate electrodes, extending perpendicularly to the second substrate, and including a channel layer. The semiconductor device also includes a ground interconnection structure connecting the first substrate and the second substrate, and including an upper via integrated with the second substrate and extending from a lower surface of the second substrate towards the first substrate.

Abstract: A field-effect transistor including a semiconductor layer formed of an n-type metal oxide semiconductor, wherein the n-type metal oxide semiconductor includes indium oxide, wherein the indium oxide is n-type doped through introduction of one or more kinds of cations as dopants, and wherein the n-type metal oxide semiconductor has a peak detected at an angle corresponding to a (222) plane of indium oxide having a bixbite structure in an X-ray diffraction method using a two-dimensional detector.

Abstract: An electro-optical device includes one or more control lines that include a scanning line, a data line and a pixel circuit. The pixel circuit has a drive transistor, a write-in transistor with a gate which is electrically connected to the scanning line, a light-emitting element that emits light at a brightness that depends on the size of a current that is supplied through the drive transistor, and a control line which overlaps the gate of the drive transistor when viewed from a direction that is perpendicular to a surface of a substrate on which the pixel circuit is formed is included in the one or more control lines.

Abstract: A semiconductor device includes a semiconductor layer containing metal atoms, a charge storage layer provided on a surface of the semiconductor layer via a first insulating film, and an electrode layer provided on a surface of the charge storage layer via a second insulating film. The thickness of the first insulating film is 5 nm or more and 10 nm or less. The concentration of the metal atoms in the semiconductor layer is 5.0×1017 [EA/cm3] or higher and 1.3×1020 [EA/cm3] or lower.

Abstract: A display panel and a display device are provided. The display panel includes: a substrate, the substrate includes a plurality of pixel areas; a functional device layer, the functional device layer is disposed on the substrate; a plurality of via holes, the via holes are positioned on the functional device layer, and each of the via holes corresponds to one said first area; an organic layer, the organic layer is disposed on the functional device layer, and a portion of the organic layer extends into the via holes; a plurality of light emitting units; wherein, the via holes are positioned along an edge of a second area.

Abstract: A semiconductor structure including nanosheet stacks on a substrate, each nanosheet stack including alternating layers of sacrificial semiconductor material and semiconductor channel material and a crystallized gate dielectric layer surrounding the semiconductor channel layers of a first subset of the nanosheet stacks, a dipole layer on top of the crystallized gate dielectric and surrounding the layers of semiconductor channel material of the first subset of the nanosheet stacks and a gate dielectric modified by a diffused dipole material surrounding the semiconductor channel layers of a second subset of the nanosheet stacks.

Abstract: The disclosure relates to a thin film transistor. The thin film transistor may include a substrate, an active layer on the substrate, a gate on the active layer, and a source and a drain. The active layer may include a first conducting region, a second conducting region, and a channel region between the first conducting region and the second conducting region. An orthographic projection of the source and an orthographic projection of the drain on the substrate may cover at least an orthographic projection of a first conducting region and an orthographic projection of a second conducting region on the substrate.

Abstract: An array substrate and a manufacturing method thereof, wherein the array substrate includes a substrate; an active layer disposed on the substrate; a gate insulating layer disposed on the active layer; a gate disposed on the gate insulating layer; and a protection region dispose between the active layer and the gate, wherein the protection region is disposed on two sides of the gate and disposed on a same layer as the gate insulating layer.

Abstract: The present disclosure provides a TFT array substrate and a manufacturing method thereof. For the manufacturing method, a source electrode and a drain electrode are formed at first, and then edges of the source electrode and the drain electrode are used as masks to pattern a semiconductor layer to form an amorphous silicon island, which makes edges of the amorphous silicon island flush with the edges of the source electrode and the drain electrode, and completely removes the exposed semiconductor layer outside a metal layer, thereby decreasing photoelectric sensitivity of a TFT device, decreasing a size of the TFT device, and being beneficial for saving layouts and simplifying processes.

Abstract: The present disclosure generally relate to thin films incorporating high aspect ratio feature definitions and methods for forming the same. As gate height increases, 3D NAND gate stacks are subject to higher aspect ratio etching. Due to the current limitations of etching techniques, the vertical etch profile typically tapers as the depth into the gate stack increases. The inventors have devised a unique deposition scheme that compensates for etch performance degradation in deep trenches by a novel plasma-enhanced chemical vapor deposition (PECVD) film deposition method. The inventors have found that by grading various properties (e.g., refractive index, stress of the film, dopant concentration in the film) of the as-deposited films (e.g., silicon nitride) a more uniform etch profile can be achieved by compensating for variations in both dry and wet etch rates.

Abstract: A method of fabricating air gap spacers is provided. The method includes forming gate structures to extend upwardly from a substrate with source or drain (S/D) regions disposed between the gate structures and with contact trenches defined above the S/D regions and between the gate structures. The method further includes disposing contacts in the contact trenches. The method also includes configuring the contacts to define open-ended air gap spacer trenches with the gate structures. In addition, the method includes forming a cap over the open-ended air gap spacer trenches to define the open-ended air gap spacer trenches as air gap spacers. The gate structures have an initial structure prior to and following the disposing and the configuring of the contacts and prior to and following the forming of the cap.

Abstract: A semiconductor device includes several first cell rows extending in a first direction, each of the first cell rows having a first row height; several second cell rows extending in the first direction, each of the second cell rows having a second row height smaller than the first row height, wherein the first cell rows and the second cell rows are interlaced; a first cell arranged in a first row of the first cell rows; and at least one second cell arranged in at least one row of the second cell rows, wherein the at least one second cell abuts the first cell in a second direction different from the first direction, wherein the at least one second cell and at least one circuit component included in the first cell have the same operation configuration.

Abstract: Semiconductor devices and methods of forming a semiconductor device that includes a polysilicon layer that may improve device reliability and/or a functioning of the device. An example device may include a wide band-gap semiconductor layer structure including a drift region that has a first conductivity type; a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a bottom surface, a first sidewall, a second sidewall, and an upper opening; and a plurality of polysilicon layers, each polysilicon layer on the second sidewall of a respective gate trench.

Abstract: A method of manufacturing a low temperature polysilicon thin film, including: forming a buffer layer on a substrate; forming a silicon layer on the buffer layer; providing a mask; patterning the silicon layer through the mask, wherein the patterned silicon layer includes a plurality of recrystallization growth spaces; and annealing the silicon layer to form a polysilicon layer, and a partial silicon material of the polysilicon layer is formed on the recrystallization growth space.