Abstract: A qubit value change monitor is disclosed. An initial qubit value of a qubit in superposition is determined based on a first plurality of readings of the qubit. Subsequent to determining the initial qubit value, a current first qubit value is determined based on a second plurality of readings of the qubit. It is determined that the initial first qubit value differs from the current first qubit value. Responsive to determining that the initial first qubit value differs from the current first qubit value, a changed qubit action is initiated.

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a die having a first side and a second side disposed opposite to the first side. The IC package may further include an encapsulation material encapsulating at least a portion of the die and having a first surface that is adjacent to the first side of the die and a second surface disposed opposite to the first surface. In embodiments, the second surface may be shaped such that one or more cross-section areas of the IC package are thinner than one or more other cross-section areas of the IC package. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure describe novel qubit device packages, as well as related computing devices and methods. In one embodiment, an exemplary qubit device package includes a qubit die and a package substrate, where the qubit die is coupled to the package substrate using one or more preforms. In particular, a single preform may advantageously be used to replace a plurality of individual contacts, e.g. a plurality of individual solder bumps, electrically coupling the qubit die to the package substrate. Such packages may reduce design complexity and undesired coupling, and enable inclusion of larger numbers of qubits in a single qubit die.

Abstract: Provided is a structure including a first conductor plane (101); a second conductor plane (102); a first transmission line (104) that is formed in a layer different from the first conductor plane (101) and the second conductor plane (102); a second transmission line (105) that is disposed so as to face the second conductor plane (102) in a layer opposite to the first transmission line (104) with respect to the second conductor plane (102); a first conductor via (103) that connects one end of the first transmission line (104) with the first conductor plane (101); a second conductor via (106) that connects another end of the first transmission line (104) with one end of the second transmission line (105); and a slit (107) that is formed on the second conductor plane (102).

Abstract: A trench portion (trench) is formed at each of four corner portions of a chip bonding region having a quadrangular planar shape smaller than an outer-shape size of a die pad included in a semiconductor device. Each trench is formed along a direction of intersecting with a diagonal line which connects between the corner portions where the trench portions are arranged, and both ends of each trench portion are extended to an outside of the chip bonding region. The semiconductor chip is mounted on the chip bonding region so as to interpose a die-bond material. In this manner, peel-off of the die-bond material in a reflow step upon mounting of the semiconductor device on a mounting substrate can be suppressed. Also, even if the peel-off occurs, expansion of the peel-off can be suppressed.

Abstract: Microfeature dies with redistribution structures that reduce or eliminate line interference are disclosed. The microfeature dies can include a substrate having a bond site and integrated circuitry electrically connected to the bond site. The microfeature dies can also include and a redistribution structure coupled to the substrate. The redistribution structure can include an external contact site configured to receive an electric coupler, a conductive line that is electrically connected to the external contact site and the bond site, and a conductive shield that at least partially surrounds the conductive line.

Abstract: An integrated circuit connection comprises a substrate, first and second transmission lines, a die, and a conductive ribbon. The first transmission line has a first end and is arranged on the substrate. The die is spaced from the first end. The die has a first surface, which is arranged on the substrate, and a second surface, which is opposite to the first surface and which has the second transmission line arranged thereon. The second transmission line has a second end. The conductive ribbon electrically couples the first and the second ends.

Abstract: Superconductive interconnection structures providing continuous, uninterrupted superconducting signal paths between a superconducting chip and a superconducting chip carrier are described. The superconductive interconnection structures employ superconducting solder bumps and pillars of Under Bump Metal (“UBM”). The superconductive interconnection structures are employed in a two-stage solder bumping process in which the superconducting chip is first bonded to a testing module for screening and then bonded to a chip packaging module for operation. Either the testing module or the chip packaging module, or both, may include a multi-chip module for carrying multiple superconducting chips simultaneously.

Abstract: A superconducting integrated circuit may include a magnetic flux transformer having an inner inductive coupling element and an outer inductive coupling element that surrounds the inner inductive coupling element along at least a portion of a length thereof. The magnetic flux transformer may have a coaxial-like geometry such that a mutual inductance between the first inductive coupling element and the second inductive coupling element is sub-linearly proportional to a distance that separates the first inner inductive coupling element from the first outer inductive coupling element. At least one of the first inductive coupling element and the second inductive coupling element may be coupled to a superconducting programmable device, such as a superconducting qubit.

Abstract: A connection element is arranged on a connection area of a semiconductor component. The connection element includes at least one bonding wire portion fixed on the connection area. The connection area is covered by an electrically conductive material, the fixed bonding wire portion being surrounded or embedded by the electrically conductive material.

Abstract: A integrated circuit and methods for fabricating the circuit are provided. The circuit integrates at least one circuit element formed from a material that is superconducting at temperatures less than one hundred milliKelvin and at least one resistor connected to the circuit element. The resistor is formed from an alloy of transition metals that is resistive at temperatures less than one hundred milliKelvin.

Abstract: A protected electrical device having at least one electrical sub-assembly (1) to be protected comprises on at least one (11) of upper and lower surfaces (11, 12), at least a screening layer (2) against the electromagnetic (EM) and radiofrequency (RF) fields emitted by the electrical sub-assembly (1). The screening layer (2) comprises at least a first layer made of soft magnetic material with a high relative permeability (µr) larger than 500. The screening layer (2) is placed on substantially the whole surface of said at least one (11) of the upper and lower surfaces (11, 12), except on predetermined regions (1a) of limited area, the electrical connections (8, 9) with external devices being located on at least some of the predetermined regions of limited area.

Abstract: Disclosed are methods, systems, and structures for implementing interconnect modeling by using a test structure which include a variation of physical wire structures between local interconnects and distant interconnects. According to one approach, the impact of variations of the physical properties for neighborhood wires are considered for the electrical modeling of interconnects. This variation between the local and distant wire characteristics allows more accurate and robust interconnect modeling to be created.

Abstract: A semiconductor device includes: a semiconductor element; a die pad with the semiconductor element mounted thereon; a plurality of electrode terminals each having a connecting portion electrically connected with the semiconductor element; and a sealing resin for sealing the semiconductor element, the die pad and the electrode terminals so that a surface of each electrode terminal on an opposite side from a surface having the connecting portion is exposed as an external terminal surface. A recess having a planar shape of a circle is formed on the surface of each electrode terminal with the connecting portion, and the recess is arranged between an end portion of the electrode terminal exposed from an outer edge side face of the sealing resin and the connecting portion. While a function of the configuration for suppressing the peeling between the electrode terminal and the sealing resin can be maintained by mitigating an external force applied to the electrode terminal, the semiconductor device can be downsized.

Abstract: An alpha particle blocking structure and method of making the structure. The structure includes: a semiconductor substrate; a set of interlevel dielectric layers stacked from a lowermost interlevel dielectric layer closest to the substrate to a uppermost interlevel dielectric layer furthest from the substrate, each interlevel dielectric layer of the set of interlevel dielectric layers including electrically conductive wires, top surfaces of the wires substantially coplanar with top surfaces of corresponding interlevel dielectric layers; an electrically conductive tot final pad contacting a wire pad of the uppermost interlevel dielectric layer; an electrically conductive plating base layer contacting a top surface of the terminal pad; and a copper block on the plating base layer.

Abstract: A method of forming the integrated circuit. The method includes, in an integrated circuit package, forming each bond to or from an integrated circuit pad that is intended to be an antenna connection to be elongated compared to other bonds, and arranged in an approximately perpendicular direction to the plane of the integrated circuit; encapsulating the top of the integrated circuit package with a dielectric material at a height greater than a desired antenna length; and milling the dielectric encapsulation down to a pre-selected and calibrated height, such that the elongated bond wire to/from the integrated circuit pad that is intended to be an antenna connection is severed, such that the approximately vertical bond wire to/from the integrated circuit pad that is intended to be an antenna connection forms a quarter wave monopole.

Abstract: An apparatus includes a first substrate having a set of semiconductor devices formed within it. The apparatus also includes a second substrate. A third substrate has a data conductor coupled between first and second connections to the second substrate. The data conductor is coupled to the set of semiconductor devices at respective connection points.

Abstract: The present invention provides a semiconductor device, including: a semiconductor substrate having a circuit formed thereon; a mounting substrate cemented to a rear face of the semiconductor substrate; a plurality of pads arranged in a linearly juxtaposed relationship with each other in a direction perpendicular to a peripheral edge side of the semiconductor substrate which is nearest to the pads on a main face of the semiconductor substrate and electrically connected to the circuit in a corresponding relationship to a signal, a power supply voltage and a reference signal; a plurality of wires individually cemented at one end thereof to the pads; and a plurality of wire cemented elements formed on the mounting substrate and cemented to the other end of the wires.

Abstract: A flexible printed circuit board includes: a signal wiring pattern including: a transmission line for connecting an end of an optical device with an end of a signal generation circuit; and another transmission line for connecting another end of the optical device with another end of the signal generation circuit; a thin film resistor layer formed in a region including a region facing the signal wiring pattern so as to constitute a first microstrip line together with each of the transmission lines; a ground conductor formed in a region except a part of a region facing the thin film resistor layer within a region including a region facing the signal wiring pattern so as to constitute a second microstrip line together with each of the transmission lines; and an insulating layer formed between each two of the signal wiring pattern, the thin film resistor layer, and the ground conductor.

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Abstract: An object of the present invention is to provide a transmitter-receiver RF-IC having a built-in regulator, which can reduce a minimum value of an input voltage of the regulator without increasing its area, the input voltage being supplied from a battery, the transmitter-receiver RF-IC being capable of normal operation with the input voltage, whereby the operating time of a mobile terminal can be improved as compared with the prior art. According to the present invention, in order to achieve the above object, an output end of a regulator built into a RF-IC is first led to the outside of the RF-IC. Then, the output end is led to an area in proximity to the circuit block by use of wiring on a mobile terminal substrate whose resistance is low, or by use of wiring on a module whose resistance is low, thereby shortening the wiring length inside the RF-IC.

Abstract: An apparatus includes a first substrate having a set of semiconductor devices formed within it. The apparatus also includes a second substrate. A third substrate has a data conductor coupled between first and second connections to the second substrate. The data conductor is coupled to the set of semiconductor devices at respective connection points.

Abstract: A superconducting system that includes an interface circuit capable of making the best use of a high-speed superconducting circuit and a high-speed semiconductor circuit. A multi-chip module in which an Nb superconducting circuit having Josephson junctions formed by the use of Nb and an oxide high-temperature superconducting latch interface circuit having Josephson junctions formed by the use of an oxide high-temperature superconductor are connected is located in a low temperature environment kept at 4.2 K. The oxide high-temperature superconducting latch interface circuit is connected to a high-speed semiconductor amplifier and a signal outputted from the Nb superconducting circuit is transmitted to the high-speed semiconductor amplifier.

Abstract: An example of a circuit structure may include a first dielectric layer having first and second surfaces, and a channel extending at least partially between the first and second surfaces and along a length of the first dielectric layer. First and second conductive layers may be disposed on respective portions of the first and second surfaces. A first conductor, having an end, may be disposed on a surface of the first dielectric layer, including at least a first portion extending around at least a portion of the conductor end. The second conductive layer may line the channel extending around a portion of the conductor end. Some examples may include a stripline having a second conductor connected to the first conductor. Some examples may include a cover having a wall positioned on the first dielectric over the second conductor.

Abstract: Provided are a multi-ground shielding semiconductor package including analog and digital circuit blocks and capable of preventing a coupling problem between the analog and digital circuit blocks caused by high frequency noise. A method of fabricating the multi-ground shielding semiconductor package, and a method of preventing noise in the multi-ground shielding semiconductor package are also provided. The multi-ground shielding semiconductor package includes at least one semiconductor chip; and a circuit board on which the semiconductor chip is mounted and on which a plurality of circuit blocks are formed, wherein a conductive ground shielding is formed between the circuit blocks and separately from grounds of the circuit blocks to prevent noise between the circuit blocks.

Abstract: A substrate for mounting a device is disclosed. The substrate includes at least one transition for providing an RF connection to a lead of the device, the lead extending from a device input to an otherwise free end. The transition comprises two spaced apart electrically coupled members, the first member occupying at least the same area on a top surface of the substrate as the device lead to which it is to connect, and the second member lying in register with the first member. The transition comprises an input, which is located at the end of the second member which is nearest the free end of the device lead and an output which is located at the opposite end of the first member and which is in register with the device input. The electrical characteristics of the transition are such that the electrical length from the input of the transition to the output of the transition is approximately equal to one half of a wavelength over a given operating frequency band of the device.

Abstract: A connection arrangement for a micro lead frame plastic (MLP) package is provided that includes a paddle configured to be connected to a circuit board and a first ground pad and a second ground pad each connected to the paddle. The first and second ground pads together with the paddle are configured to provide continuity of ground between the circuit board and a chip mounted to the paddle.

Abstract: A Radio Frequency (RF) device includes a semi conductive die and a package in which the semi conductive die mounts. The semi conductive die includes a first portion of an RF circuit and a plurality of die pads formed thereon. The package includes a heat slug upon which the semi conductive die resides, a plurality of package pins, a plurality of bond wires, a downbond rail, and a plurality of downbonds. Each of the bond wires couples between a corresponding die pad and a corresponding package pin. The downbond rail couples to the heat slug. At least one downbond couples between a die pad corresponding to the first portion of the RF circuit and a respective location on the downbond rail, serves as an inductor for a second portion of the RF circuit, may include a plurality of downbonds coupled in parallel, and has a length and/or a diameter selected to provide a desired inductance.

Abstract: A ferroelectric memory device of the present invention includes a memory cell array in which memory cells are arranged in a matrix having first signal electrodes, second signal electrodes arranged in a direction intersecting the first signal electrodes, and a ferroelectric layer disposed at least in intersection regions between the first signal electrodes and the second signal electrodes, and a peripheral circuit section for selectively writing information into or reading information from the memory cell. The memory cell array and the peripheral circuit section are formed in different layers. The peripheral circuit section is formed in a region outside the memory cell array.

Abstract: The purpose of the present invention is to provide a small-sized switch attaining high isolation of not less than 80 dB, maintaining low insertion loss also in high frequencies not less than 60 GHz. A semiconductor switch according to the present invention utilizes FETs a gate electrode, a source electrode, and a drain electrode of each of which are formed on a semiconductor. The source electrode and the drain electrode are connected with the earth as well as are disposed in parallel to each other, and the gate electrode is formed between the source electrode and the drain electrode, and both the ends of the gate electrode are connected to the first input-output terminal 1 and the second input-output terminal.

Abstract: A large area dummy pattern DL is formed in a layer underneath a target T2 region formed in a scribe region SR of a wafer. A small area dummy pattern in a lower layer and a small area dummy pattern Ds2 in an upper layer are disposed in a region where the inter-pattern space of a pattern (active regions L1, L2, L3, gate electrode 17), which functions as an element of a product region PR and scribe region SR, is wide. The small area dummy pattern Ds2 in the upper layer is offset by ½ pitch relative to the small area dummy pattern Ds in the lower layer.

Abstract: Semiconductor devices and methods of forming the semiconductor devices using an HTS (High Temperature Superconductor) layer in combination with a typical diffusion layer between the dielectric material and the copper (or other metal) conductive wiring. The HTS layer includes a superconductor material comprised of barium copper oxide and a rare earth element. The rare earth element yttrium is particularly suitable. For semiconductor devices having other semiconductor circuits or elements above the wiring, a capping layer of HTS material is deposited over the wiring before a cover layer of dielectric is deposited.

Abstract: A semiconductor light emitting device including a p-type electrode structure and having a low contact resistance and high reflectance is provided. The semiconductor light emitting device includes a transparent substrate, an electron injection layer having first and second regions on the transparent substrate, an active region formed on the first region, a hole injection layer on the active layer, a first electrode structure on the second region, and a second electrode structure on the hole injection layer, and includes a first layer including nitrogen and a second layer including Pd. The low contact resistance and high reflectance can be obtained by forming a trivalent compound layer composed of Pd—Ga—N at an interface between the hole injection layer, which is composed of p-GaN, and the metal layer of the p-type electrode.

Abstract: A superconducting system that includes an interface circuit capable of making the best use of a high-speed superconducting circuit and a high-speed semiconductor circuit. A multi-chip module in which an Nb superconducting circuit having josephson junctions formed by the use of Nb and an oxide high-temperature superconducting latch interface circuit having josephson junctions formed by the use of an oxide high-temperature superconductor are connected is located in a low temperature environment kept at 4.2 K. The oxide high-temperature superconducting latch interface circuit is connected to a high-speed semiconductor amplifier and a signal outputted from the Nb superconducting circuit is transmitted to the high-speed semiconductor amplifier.

Abstract: A semiconductor device (121) is provided which comprises a substrate and a die (123) having a first surface which is attached to the substrate by way of a die attach material. At least a portion (127) of the perimeter of the die is resistant to wetting by the die attach material, either through treatment with a dewetting agent or by selective removal of the backside metallization. It is found that this construction allows the surface area of the die to be increased without increasing the incidence of cracking and chipping along the sawn edges of the die.

Abstract: An integrated circuit is packaged using a package substrate that has a bottom side with a regular array of connection points and a top side with the integrated circuit on it. The package substrate also has vias that are present to provide electrical connection between the top and bottom sides. The vias have a via capture pad that is used to directly receive a wire bond. Thus, the wires from the integrated circuit to the top side directly contact the vias at their capture pads. In such a connection there is then no need for a trace from location where the wire is bonded on the top side to the via. This saves cost. Further this makes the package substrate useful for more than one type of integrated circuit.

Abstract: A Radio Frequency (RF) device includes a semi conductive die and a package in which the semi conductive die mounts. The semi conductive die includes a first portion of an RF circuit and a plurality of die pads formed thereon. The package includes a heat slug upon which the semi conductive die resides, a plurality of package pins, a plurality of bond wires, a downbond rail, and a plurality of downbonds. Each of the bond wires couples between a corresponding die pad and a corresponding package pin. The downbond rail couples to the heat slug. At least one downbond couples between a die pad corresponding to the first portion of the RF circuit and a respective location on the downbond rail, serves as an inductor for a second portion of the RF circuit, may include a plurality of downbonds coupled in parallel, and has a length and/or a diameter selected to provide a desired inductance.

Abstract: A solid-state quantum computing qubit includes a multi-terminal junction coupled to a superconducting loop where the superconducting loop introduces a phase shift to the superconducting order parameter. The ground state of the supercurrent in the superconducting loop and multi-terminal junction is doubly degenerate, with two supercurrent ground states having distinct magnetic moments. These quantum states of the supercurrents in the superconducting loop create qubits for quantum computing. The quantum states can be initialized by applying transport currents to the external leads. Arbitrary single qubit operations may be performed by varying the transport current and/or an externally applied magnetic field. Read-out may be performed using direct measurement of the magnetic moment of the qubit state, or alternatively, radio-frequency single electron transistor electrometers can be used as read-out devices when determining a result of the quantum computing.

Abstract: An interconnect is described including a semiconductor substrate having opposing surfaces, including first and second insulated conductors for transmitting signals. A third conductor substantially surrounds and is electrically insulated from the first and second insulated conductors. Capacitance between the first insulated conductor and the third conductor is substantially equivalent to capacitance between the second insulated conductor and the third conductor. The first insulated conductor and the second insulated conductor are disposed between the opposing surfaces of the semiconductor substrate.

Abstract: A solid-state quantum computing qubit includes a multi-terminal junction coupled to a superconducting loop where the superconducting loop introduces a phase shift to the superconducting order parameter. The ground state of the supercurrent in the superconducting loop and multi-terminal junction is doubly degenerate, with two supercurrent ground states having distinct magnetic moments. These quantum states of the supercurrents in the superconducting loop create qubits for quantum computing. The quantum states can be initialized by applying transport currents to the external leads. Arbitrary single qubit operations may be performed by varying the transport current and/or an externally applied magnetic field. Read-out may be performed using direct measurement of the magnetic moment of the qubit state, or alternatively, radio-frequency single electron transistor electrometers can be used as read-out devices when determining a result of the quantum computing.

Abstract: The present invention generally involves an extra-substrate control system comprising a first substrate, attached to which is at least one superconducting structure, and a second substrate, connected to which is at least one element of circuitry, wherein the superconducting structure and the circuitry interact, so that a change in a state of the superconducting structure can be detected by the circuitry. The present invention also provides a quantum computing apparatus comprising a first substrate, attached to which is one or more layers of material, at least one of which is a superconducting material, a second substrate, deposited on which is a flux shield and on the flux shield is at least one element of circuitry, wherein the superconducting material and the second substrate are separated by a mean distance that is small enough to permit coupling between the element of circuitry and the superconducting material.

Abstract: An integrated circuit package houses and connects to a die to form an integrated circuit with internal matching. The package comprises a lead frame comprising at least one transmission line, a die paddle, and at least one input lead and at least one output lead. Bond wires connect select locations along the at least one transmission line to ground through impedance matching circuit components located within the integrated circuit to provide an impedance matching network associated with at least one of the output leads. The package may also substantially encapsulate the lead frame, while exposing the die paddle and the input/output leads.

Abstract: An interconnect is described including a semiconductor substrate having opposing surfaces, including first and second insulated conductors for transmitting signals. A third conductor substantially surrounds and is electrically insulated from the first and second insulated conductors. Capacitance between the first insulated conductor and the third conductor is substantially equivalent to capacitance between the second insulated conductor and the third conductor. The first insulated conductor and the second insulated conductor are disposed between the opposing surfaces of the semiconductor substrate.

Abstract: A superconducting quantum-bit device based on Josephson junction has a charge as a first principal degree of freedom assigned to writing and a phase as a second principal degree of freedom assigned to reading. The device comprises a Cooper-pair box comprising first and second Josephson junctions defining a charge island of the Cooper-pair box closing up onto a superconducting loop. A read circuit comprises a read Josephson junction JL inserted into the superconducting loop and having a Josephson energy Ej at least 50 times greater than the Josephson energy of each of the first and second Josephson junctions.

Abstract: A method for increasing the critical temperature, Tc, of a high critical temperature superconducting (HTS) film (104) grown on a substrate (102) and a superconducting structure (100) made using the method. The HTS film has an a-b plane parallel to the surface of the substrate and a c-direction normal to the surface of the substrate. Generally, the method includes providing the substrate, growing the HTS film on the substrate and, after the HTS film has been grown, inducing into the HTS film a residual compressive strain the a-b plane and a residual tensile strain into the c-direction.

Abstract: An integrated circuit package houses and connects to a die to form an integrated circuit with internal matching. The package comprises a lead frame comprising at least one transmission line, a die paddle, and at least one input lead and at least one output lead. Bond wires connect select locations along the at least one transmission line to ground through impedance matching circuit components located within the integrated circuit to provide an impedance matching network associated with at least one of the output leads. A plastic mold compound substantially encases the lead frame, while exposing the die paddle and the input/output leads. Incorporating the transmission line into the lead-frame avoids having to place the matching network outside of the integrated circuit package. That is, etching the lead frame to provide the transmission line, and placing components (e.g., capacitors, inductors, etc.

Abstract: An electrical circuit and method substantially to mitigate the effects of a current increase due to a fault within the circuit. In particular, where the electrical circuit (80) includes a laser diode it is desirable to create a fault tolerant circuit to avoid a sudden increase in light intensity output by the laser diode. A track (44b) associated with the laser diode is identified and insulated by means of a layout of the circuit. Specifically, where the circuit is an integrated circuit, metal layers (42, 44, 46) and vias (50) are utilised to form an insulating shield (76) around the track (44b) associated with the laser diode.

Abstract: A combination edge- and broadside-coupled transmission line element formed in an integrated circuit chip, using semiconductor processes, in a stack of metal layers separated by dielectric layers. Each of the metal layers includes a number of transmission lines. Interconnects between the transmission lines are formed at predetermined locations, each interconnect electrically connecting together a group of the transmission lines to form a conductor. The efficiency of the coupling between the lines in the different conductor is increased by positioning the lines such that both edge and broadside-coupling is realized. For example, at least one of the transmission lines in one of the conductors is positioned either above or below a transmission line in the other conductor to achieve broadside-coupling and laterally adjacent to another transmission line in the other conductor to achieve edge-coupling.

Abstract: A method includes providing a superconducting material having pinning sites that can pin magnetic vortices within the superconducting material. The method also includes pinning one or more magnetic vortices at one or more of the pinning sites. An information storage apparatus includes a superconducting material, doped particles within the superconducting material that can pin dipole magnetic vortices, a magnetic tip that generates pinned magnetic vortices and a magnetic detector that detects pinned magnetic vortices.