Abstract: A food transportation system and associated modular humidity control system are provided. An example system includes a body configured for attachment with a food storage housing. The body defines a closed circuit air flow path for circulating air through the food storage housing. The system also includes a humidity control element secured within the closed circuit air flow path that condenses moisture from the moisture-laden air passing through the closed circuit air flow path. The system further includes a condensation collector configured to receive fluid condensed from the moisture-laden air by the humidity control element.

Abstract: The display device includes: a flexible display panel including a display portion in which scanning lines and signal lines cross each other; a supporting portion for supporting an end portion of the flexible display panel; a signal line driver circuit for outputting a signal to the signal line, which is provided for the supporting portion; and a scanning line driver circuit for outputting a signal to the scanning line, which is provided for a flexible surface of the display panel in a direction which is perpendicular or substantially perpendicular to the supporting portion.

Abstract: A MEMS chip package is provided with a removable cover to allow non-destructive testing. The MEMS package has a container (with walls and a bottom) and a cover. The cover has a glass pane, and is secured to the MEMS package with an elastomeric gasket mounted between the walls of the MEMS package and the cover. A number of attachment mechanisms secure the cover to the MEMS package.

Abstract: An image sensor package and a manufacturing method thereof are provided. The image sensor package includes a redistribution circuit structure; an image sensing chip disposed on the redistribution circuit structure and having a sensing surface, on which a sensing area and a first conductive pillar arranged in the periphery of the sensing area are disposed; a lid covering the sensing area; an encapsulant disposed on the redistribution circuit structure and encapsulating at least part of the image sensing chip and the cover; and a top tier semiconductor chip disposed above the image sensing chip and having an active surface on which a first conductor is disposed. The first conductor overlaps the image sensing chip in a direction perpendicular to the sensing surface. The first conductive pillar and the first conductor are aligned and bonded to each other to electrically connect the image sensing chip and the top tier semiconductor chip.

Abstract: A semiconductor device substrate assembly may include a first substrate, comprising: a first insulator plate; and a first patterned metal layer, disposed on the first insulator plate, wherein the first insulator plate comprises a first material and a first thickness. The assembly may include a second substrate, comprising: a second insulator plate; and a second patterned metal layer, disposed on the second insulator plate, wherein the second insulator plate comprises the first material and the first thickness. The assembly may also include a third substrate, disposed between the first substrate and the second substrate, comprising: a third insulator plate; and a third patterned metal layer, disposed on the third insulator plate, wherein the third insulator plate comprises a second material and a second thickness, wherein at least one of the second material and the second thickness differs from the first material and the first thickness, respectively.

Abstract: A circuit, comprising a diode, a conductive upper support disposed on top of the diode and electrically coupled to the diode, a conductive lower support disposed underneath the diode and electrically coupled to the diode, a mechanical support disposed adjacent to the diode, the conductive upper support and the conductive lower support, an insulator disposed underneath the mechanical support, an upper terminal coupled to the mechanical support and electrically coupled to the conductive upper support and a lower terminal coupled to the insulator and electrically coupled to the conductive lower support.

Abstract: An interposer includes: a base substrate; an interconnection structure on a top surface of the base substrate and including a metal interconnection pattern; an upper passivation layer on the interconnection structure and having compressive stress; a lower passivation layer under a bottom surface of base substrate, the lower passivation layer having compressive stress that is less than the compressive stress of the upper passivation layer; a lower conductive layer under the lower passivation layer; and a through electrode penetrating the base substrate and the lower passivation layer. The through electrode electrically connects the lower conductive layer to the metal interconnection pattern of the interconnection structure.

Abstract: A spacer structure, which connects an insulating substrate and a semiconductor chip of a double-sided-cooled power module, includes: a conductive material layer which is composed of a composite material; an underlying plating layer disposed on the conductive material layer; and a copper plating layer disposed on the underlying plating layer, in which the copper plating layer is in contact with a joining material that joins the spacer to the semiconductor chip and the insulating substrate.

Abstract: A method of manufacturing display device is disclosed. a substrate includes a basal layer and metal contacts on the top surface. An insulation layer is disposed on the top surface and includes a first mounting surface and a bottom surface. Multiple grooves are formed on the insulation layer and each extends from the first mounting surface to the bottom surface. The grooves respectively correspond to the metal contacts and expose respective metal contacts. An electromagnetic force is provided with a direction from the basal layer toward the insulation layer. A droplet containing multiple micro components is provided on the first mounting surface. A configuration of an electrode of the micro component corresponds to a configuration of one of the grooves. The electrode is attracted to the corresponding groove by the electromagnetic force so as to electrically contact the metal contact.

Abstract: Silicone-containing light fixture optics. A method for manufacturing an optical component may include mixing two precursors of silicone, opening a first gate of an optic forming device, moving the silicone mixture from the extrusion machine into the optic forming device, cooling the silicone mixture as it enters the optic forming device, filling a mold within the optic forming device with the silicone mixture, closing the first gate, and heating the silicone mixture in the mold to at least partially cure the silicone. Alternatively, a method for manufacturing an optical component may include depositing a layer of heat cured silicone optical material to an optical structure, arranging one or more at least partially cured silicone optics on the layer of heat cured silicone optical material, and heating the heat cured silicone optical material to permanently adhere the one or more at least partially cured silicone optics to the optical structure.

Abstract: A lower electrode, an upper electrode provided above the lower electrode, a semiconductor chip provided between the lower electrode and the upper electrode, a pressure pad provided between the lower electrode and the upper electrode to be overlapped with the semiconductor chip, and a spiral conductor provided between the lower electrode and the upper electrode to be overlapped with the semiconductor chip and the pressure pad are provided. The spiral conductor has an upper spiral conductor, and a lower spiral conductor which is in contact with a lower end of the upper spiral conductor and faces the upper spiral conductor, and by forming grooves in the upper spiral conductor and the lower spiral conductor, a direction of a current flowing through the upper spiral conductor coincides with a direction of a current flowing through the lower spiral conductor in plan view.

Abstract: Methods of forming and structures of packages are discussed herein. In an embodiment, a method includes forming a back side redistribution structure, and after forming the back side redistribution structure, adhering a first integrated circuit die to the back side redistribution structure. The method further includes encapsulating the first integrated circuit die on the back side redistribution structure with an encapsulant, forming a front side redistribution structure on the encapsulant, and electrically coupling a second integrated circuit die to the first integrated circuit die. The second integrated circuit die is electrically coupled to the first integrated circuit die through first external electrical connectors mechanically attached to the front side redistribution structure.

Abstract: A semiconductor package includes: a memory sub-package including a first connecting layer and a plurality of memory chips disposed on the first connecting layer; a logic sub-package including a second connecting layer, a controller chip disposed on the second connecting layer, and a buffer chip connected to the controller chip and the plurality of memory chips; and a plurality of inter-package connecting members each of which connects the memory sub-package and the logic sub-package, wherein the buffer chip is connected to the plurality of memory chips via a plurality of first data transfer lines each having a first data transfer rate, the buffer chip is connected to the controller chip via a plurality of second data transfer lines each having a second data transfer rate, and the first data transfer rate is less than the second data transfer rate.

Abstract: Packages including substrate-less integrated components and methods of fabrication are described are described. In an embodiment, a packaging method includes attaching a ground structure to a carrier and a plurality of components face down to the carrier and laterally adjacent to the ground structure. The plurality of components are encapsulated within a molding compound, and the carrier is removed exposing a plurality of component terminals and a plurality of ground structure terminals. A plurality of packages are singulated.

Abstract: A semiconductor chip including a die substrate, a plurality of first bonding structures, a plurality of conductive elements, at least one integrated device, a plurality of conductive posts and a protection layer is provided. The first bonding structures are disposed on the die substrate. The conductive elements are disposed on the die substrate adjacent to the first bonding structures. The integrated device is disposed on the die substrate over the first bonding structures, wherein the integrated device includes a plurality of second bonding structures and a plurality of conductive pillars, and the second bonding structures are hybrid bonded to the first bonding structures. The conductive posts are disposed on the conductive elements and surrounding the integrated device. The protection layer is encapsulating the integrated device and the conductive posts.

Abstract: A semiconductor device is disclosed including semiconductor die formed with a row of functional die bond pads and an adjacent row of dummy die bond pads. The functional die bond pads may be electrically connected to the integrated circuits formed within the semiconductor die. The dummy die bond pads may be formed in the scribe area of a semiconductor wafer from which the semiconductor die are formed, and are provided for wire bonding the semiconductor die within the semiconductor device.

Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a first recess portion and a first stopper layer disposed on a bottom surface of the first recess portion; a semiconductor chip disposed in the first recess portion and having connection pads, an active surface on which the connection pads are disposed, and an inactive surface opposing the active surface and disposed on the first stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the first recess portion; and a connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connecting the wiring layers of the frame and the connection pads of the semiconductor chip to each other.

Abstract: It is an object to provide a pressure-contact power semiconductor device and a power semiconductor core module which are capable of properly reducing their sizes. Each power semiconductor core module includes the following: a plurality of power semiconductor chips including a plurality of self-turn-off semiconductor elements and a plurality of diodes adjacent to each other in plan view; and a plurality of first springs disposed between an upper metal plate and a conductive cover plate. The plurality of self-turn-off semiconductor elements of each power semiconductor core module are arranged along any one of an L-shaped line, a cross-shaped line, and a T-shaped line in plan view.

Abstract: A power semiconductor device module includes a metal baseplate and a plastic housing that together form a tray. Power electronics are disposed in the tray. A plastic cap covers the tray. Electrical press-fit terminals are disposed along the periphery of the tray. Each electrical terminal has a press-fit pin portion that sticks up through a hole in the cap. In addition, the module includes four mechanical corner press-fit anchors disposed outside the tray. One end of each anchor is embedded into the housing. The other end is an upwardly extending press-fit pin portion. The module is manufactured and sold with the press-fit pin portions of the electrical terminals and the mechanical corner anchors unattached to any printed circuit board (PCB). The mechanical anchors help to secure the module to a printed circuit board. Due to the anchors, screws or bolts are not needed to hold the module to the PCB.

Abstract: An optoelectronic semiconductor device is disclosed. The optoelectronic semiconductor device includes a matrix substrate including a matrix circuit and a substrate, and a plurality of microsized optoelectronic semiconductor elements disposed separately and disposed on the matrix circuit. Each of the microsized optoelectronic semiconductor elements includes a first electrode and a second electrode, the matrix circuit includes a plurality of third electrodes and a plurality of fourth electrodes. The first electrodes are coupled with and electrically connected with the third electrodes respectively, or the second electrodes are coupled with and electrically connected with the fourth electrodes respectively. Reflectivities of at least some of junctions between the first electrode and the third electrode, or reflectivities of at least some of junctions between the second electrode and the fourth electrode are less than 20%.

Abstract: A semiconductor device includes a substrate, a semiconductor chip, and an array of contact elements electrically coupling the substrate to the semiconductor chip. The semiconductor device includes an underfill material between the substrate and the semiconductor chip and between the contact elements. A patterned structure is arranged on the substrate and extends from under the semiconductor chip through a keep-out zone around an edge of the semiconductor chip. The patterned structure provides a reservoir for the underfill material.

Abstract: A manufacturing method of a package structure is provided. The method includes the following steps. A package panel is provided. The package panel includes a first encapsulation, a plurality of first integrated circuit components and a plurality of redistribution circuit patterns electrically connected to the first integrated circuit components, the first integrated circuit components are encapsulated by the first encapsulation, and the redistribution circuit patterns are distributed on the first encapsulation and the first integrated circuit components. The first encapsulation of the package panel is cut to form a plurality of singulated package strips. One of the singulated package strips is attached onto an attachment region of a substrate. The substrate includes at least one tooling hole distributed outside of the attachment region. The package process is performed over the singulated package strip with the substrate affixed through the tooling hole to form the package structure.

Abstract: An optoelectronic semiconductor device and a manufacturing method are disclosed. The manufacturing method includes steps of: a step of providing a microsized optoelectronic semiconductor element, a step of providing a matrix substrate, a step of electrode alignment and lamination, a step of electrode coupling, a step of illumination and lift-off and a step of removal. The step of electrode coupling is to provide a first light to concentratedly illuminate at least some of the junctions between the first electrodes and the third electrodes or concentratedly illuminate at least some of the junctions between the second electrodes and the fourth electrodes. The step of illumination and lift-off is to provide a second light to concentratedly illuminate at least some of the interfaces between the microsized optoelectronic semiconductor elements and the epitaxial substrate to peel off the microsized optoelectronic semiconductor elements from the epitaxial substrate.

Abstract: A semiconductor device comprises two electrodes with opposite faces; a semiconductor wafer sandwiched between the two electrodes; an outer insulating ring attached to the two electrodes and surrounding the semiconductor wafer; a middle insulating ring inside the outer insulating ring and surrounding the semiconductor wafer, whereby the middle insulating ring is made of a plastics material; and an inner insulating ring inside the middle insulating ring, whereby the inner insulating ring is made of ceramics and/or glass material. Either the middle insulating ring or the inner insulating ring has a tongue and the other thereof has a groove such that the tongue fits into the groove for their rotational alignment. The middle insulating ring and the inner insulating ring have a radial opening for receiving a gate connection of the semiconductor device.

Abstract: Methods of forming and structures of packages are discussed herein. In an embodiment, a method includes forming a back side redistribution structure, and after forming the back side redistribution structure, adhering a first integrated circuit die to the back side redistribution structure. The method further includes encapsulating the first integrated circuit die on the back side redistribution structure with an encapsulant, forming a front side redistribution structure on the encapsulant, and electrically coupling a second integrated circuit die to the first integrated circuit die. The second integrated circuit die is electrically coupled to the first integrated circuit die through first external electrical connectors mechanically attached to the front side redistribution structure.

Abstract: Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed. In one embodiment, a system comprises a semiconductor component including an interposer substrate, a microelectronic die over the interposer substrate, and a connection structure composed of a volume of solder material between the interposer substrate and the microelectronic die. The connection structure can include at least one of (a) a single, unitary structure covering approximately all of the back side of the microelectronic die, and (b) a structure electrically isolated from internal active features of the microelectronic die. In some embodiments, the connection structure can be positioned to provide generally consistent stress distribution within the system.

Abstract: Systems and methods for setting, assembling, and/or monitoring deflection (and thus load) in a load beam of a clamping system for a press pack high power semiconductor. The clamping system includes an assembly of a heat sink, a clamp component, and a semiconductor package. The clamp component includes two or more bolts securely connecting a load beam to the heat sink, with the semiconductor package sandwiched between the load beam and the heat sink. A detector and a calibration gage can be assembled onto the clamping system to detect and/or measure the depth of curvature of the load beam.

Abstract: A power semiconductor device module includes a metal baseplate and a plastic housing that together form a tray. Power electronics are disposed in the tray. A plastic cap covers the tray. Electrical press-fit terminals are disposed along the periphery of the tray. Each electrical terminal has a press-fit pin portion that sticks up through a hole in the cap. In addition, the module includes four mechanical corner press-fit anchors disposed outside the tray. One end of each anchor is embedded into the housing. The other end is an upwardly extending press-fit pin portion. The module is manufactured and sold with the press-fit pin portions of the electrical terminals and the mechanical corner anchors unattached to any printed circuit board (PCB). The mechanical anchors help to secure the module to a printed circuit board. Due to the anchors, screws or bolts are not needed to hold the module to the PCB.

Abstract: A semiconductor device includes an annular-shaped first frame comprised of a ceramic and forming an inner cavity in which semiconductor elements are disposed. A first electrode is on one side and a second electrode is on another. A second frame in the inner cavity holds the semiconductor elements and is comprised of a resin. A first metallic member is on one side, has an annular shape, and connects the first frame and first electrode. A second metallic member is on the other side, has an annular shape, and connects the first frame and the second electrode. A first elastic body has a first portion between the first metallic member and the second frame and a second portion abutting an inner sidewall of the first frame or overlapping the first frame. A second elastic body has a first portion between the second metallic member and the second frame.

Abstract: A semiconductor device includes a device die having a top surface, a bottom surface, and sidewalls between the top and bottom surfaces. A first protective layer covers at least the top surface and the sidewalls of the die. A thickness of the first protective layer on the sidewalls near the top surface is greater than a thickness of the first protective layer on the sidewalls die near the bottom surface.

Abstract: A semiconductor arrangement includes top and bottom contact plates, a plurality of chip assemblies, a dielectric embedding compound, and a control electrode interconnection structure. Each chip assembly has a semiconductor chip having a semiconductor body. The semiconductor body has a top side and an opposing underside. The top side is spaced apart from the underside in a vertical direction. Each semiconductor chip has a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, a control electrode arranged at the top side, and an electrically conductive top compensation die, arranged on the side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode by means of a top connecting layer. An electric current between the top main electrode and the bottom main electrode can be controlled by means of the control electrode.

Abstract: An embodiment is a method including forming a first package. The forming the first package includes forming a through via adjacent a first die, at least laterally encapsulating the first die and the through via with an encapsulant, and forming a first redistribution structure over the first die, the through via, and the encapsulant. The forming the first redistribution structure including forming a first via on the through via, and forming a first metallization pattern on the first via, at least one sidewall of the first metallization pattern directly overlying the through via.

Abstract: A semiconductor device manufacturing method improves the yield of manufacturing semiconductor devices. There are provided an insulating film for covering multiple bonding pads, a first protective film over the insulating film, and a second protective film over the first protective film. In semiconductor chips, multiple electrode layers are coupled electrically to each of the bonding pads via first openings formed in the insulating film and second openings formed in the first protective film. Multiple bump electrodes are coupled electrically to each of the electrode layers via third openings formed in the second protective film. In pseudo chips, the second openings are formed in the first protective film and the third openings are formed in the second protective film. The insulating film is exposed at the bottom of the second openings coinciding with the third openings. A protective tape is applied to a principal plane to cover the bump electrodes.

Abstract: A spacer system for a semiconductor switching device which is formed as a spacer ring and a plurality of insulating elements and supporting elements are arranged in an alternating manner around a circumference of the spacer ring. The insulating element includes a recess receiving a cathode gate connector element. The supporting element includes a projection receiving a spring system for clamping while assembling the switching device. The switching device includes a substrate, a cathode pole piece, an anode pole piece, strain buffer plates and a gate ring. Further connector elements, are electrically connecting the cathode pole piece and the gate ring of the semiconductor switching device to an external circuit unit. The space between the connector elements is minimized in order to reduce the gate circuit impedance, thus enabling an increased maximum turn-off current and further allowing for the use of larger semiconductor switching devices for high power applications.

Abstract: Provided is a semiconductor integrated circuit including: a plurality of first input/output cells arranged on a semiconductor integrated circuit substrate; a plurality of second input/output cells arranged on the semiconductor integrated circuit substrate along the plurality of first input/output cells; and a potential supply portion formed on a semiconductor package substrate, a portion of the potential supply portion protruding in a surface of the semiconductor package substrate, and configured to supply a predetermined potential to a target cell which is one of the plurality of first input/output cells and a cell neighboring the target cell among the plurality of second input/output cells through a region including the protruding portion.

Abstract: A semiconductor assembly includes a frame having at least one opening, an identical number of electrically conductive first contact plates, and an identical number of chip arrays. Each chip array has a number of semiconductor chips that are cohesively connected to one another by an embedding compound. In addition, each of the semiconductor chips has a first load terminal and a second load terminal arranged at mutually opposite sides of the relevant semiconductor chip. One of the chip arrays is inserted into each of the openings. Each of the first contact plates is arranged above one of the chip arrays in such a way that, for each of the semiconductor chips, the first load terminal is situated at a side of said semiconductor chip facing the first contact plate and the second load terminal is situated a of said semiconductor chip facing away from the first contact plate.

Abstract: A method of packaging integrated circuits includes providing a molded substrate that has a plurality of first semiconductor dies and a plurality of second semiconductor dies laterally spaced apart from one another and covered by a molding compound. The molding compound is thinned to expose at least some of the second semiconductor dies. The exposed second semiconductor dies are removed to form cavities in the molded substrate. A plurality of third semiconductor dies are inserted in the cavities formed in the molded substrate, and electrical connections are formed to the first semiconductor dies and to the third semiconductor dies.

Abstract: A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.

Abstract: A method for fabricating a packaging substrate includes: providing a carrier having a first metal layer and a second metal layer formed on the first metal layer; forming a first circuit layer on the second metal layer and forming a separating portion on an edge of the second metal layer such that the separating portion is spaced from the first circuit layer; forming a dielectric layer on the second metal layer and the first circuit layer such that the first circuit layer and the separating portion are embedded in the dielectric layer and portions of the dielectric layer are formed between the first circuit layer and the separating portion; forming a second circuit layer on the dielectric layer; and applying forces on the separating portion so as to remove the first metal layer and the carrier, thereby maintaining the integrity of the first circuit layer.

Abstract: A power semiconductor module and a power semiconductor module assembly, which includes a plurality of power semiconductor modules, are disclosed. The power semiconductor module includes an electrically conducting base plate, an electrically conducting top plate, arranged in parallel to the base plate and spaced apart from the base plate, at least one power semiconductor device, which is arranged on the base plate in a space formed between the base plate and the top plate, and at least one presspin, which is arranged in the space formed between the base plate and the top plate to provide contact between the semiconductor device and the top plate. A metallic protection plate can be provided at an inner face of the top plate facing towards the base plate, wherein the material of the protection plate has a melting temperature higher than the melting temperature of the top plate.

Abstract: A semiconductor device that improves the heat cycle resistance and power cycle resistance of a power module. An electrode member in which copper posts are formed in a plurality of perforations cut in a support made of a ceramic material is soldered onto a side of an IGBT where an emitter electrode is formed. By soldering the copper posts onto the electrode, heat generated in the IGBT is transferred to the electrode member and is radiated. In addition, even if a material of which the IGBT is made and copper differ in thermal expansivity, stress on a soldered interface is reduced and distortion is reduced. This suppresses the appearance of a crack. As a result, the heat cycle resistance and power cycle resistance of a power module can be improved.

Abstract: A semiconductor device includes a semiconductor element in a frame body. The semiconductor element includes a first electrode electrically connected to an electrode block provided on a first side of the semiconductor element. A connection element, which in some embodiments may be a portion of the electrode block, connects the electrode block to the frame body. The semiconductor element is sealed within an enclosure formed at least in part by the frame body, the connection element, and the electrode block. The connection element includes a fragile portion which has a resistance to increases in pressure or temperature that is less than other portions of the connection element. That is, in general, the fragile portion will fail before other portions of the connection element when pressure or temperature increases, which may occur when, for example, the semiconductor element breaks down.

Abstract: A package system includes a first substrate and a second substrate. The second substrate is electrically coupled with the first substrate. The second substrate includes at least one first opening. At least one electrical bonding material is disposed between the first substrate and the second substrate. A first portion of the at least one electrical bonding material is at least partially filled in the at least one first opening.

Abstract: A semiconductor device includes a substrate having a conductor; a semiconductor chip disposed on the substrate and electrically connected to the conductor; a tubular electrode having one end electrically connected to the conductor; and a sealing resin sealing the substrate, the semiconductor chip and the electrode. The electrode is configured to be extendable and contractible in the stacking direction in which the substrate and the semiconductor chip are stacked in the state before sealing of the sealing resin. The edge of the other end of the electrode is exposed from the sealing resin. The electrode has a hollow space opened at the edge of the other end. Therefore, a semiconductor device reduced in size and a method of manufacturing this semiconductor device can be provided.

Abstract: A multi layer interconnecting substrate has at least two spaced apart metal layers with a conductive pad on each one of the metal layers. Two different types of insulating layers are placed between the metal layers. The placement is such that one of the two different types of insulating layers is placed between the conductive pads and the other type of insulating layer is placed between the two spaced apart metal layers.

Abstract: Packaged semiconductor product (2) including a first semiconductor device (4A) and a packaging structure with a protective envelope (6) and a first and second external electrode (8,10). The first semiconductor device (4A) has a first substrate (11A) and is provided with a first passivation layer (12A) and a first electronic structure. The first substrate has a first main surface (14). The first substrate (11A) is embedded in the protective envelope (6) and the first main surface (14) faces a first opening (23) of the protective envelope (6). The first electronic structure has a first and a second contact region (20, 22) for electrically contacting the first electronic structure. The first passivation layer (12A) substantially covers the first main surface (14) and the first electronic structure. The protective envelope (6) extends between the first passivation layer (12A) and the first external electrode (8) towards the first contact region (20).

Abstract: A semiconductor device includes a plurality of functional element chips, an electric connection member joined to two of the functional element chips, a first wire and a resin configured to cover the functional element chips, the electric connection member and the first wire. One of the two functional element chips may be a first semiconductor chip having first and second major surface electrodes facing toward the same direction and a first rear surface electrode facing in a direction opposite to a direction in which the first major surface electrode faces. The electric connection member may be joined to the first major surface electrode. The first wire may be joined to the second major surface electrode. The first wire may include a portion overlapping with the electric connection member in a thickness direction of the first semiconductor chip.

Abstract: A package-on-package proximity sensor module including a infrared transmitter package and a infrared receiver package is presented. The proximity sensor module may include a fully-assembled infrared transmitter package and a fully-assembled infrared receiver package disposed on a quad flat pack no-lead (QFN) lead frame molded with an IR cut compound housing. A bottom surface of the QFN lead frame may be etched and covered with the IR cut compound to provide a locking feature between the QFN lead frame and the IR cut compound housing.

Abstract: An organic light emitting diode (OLED) display device, including a first substrate and a second substrate facing each other, a sealant arranged between the first and second substrates to adhere the first and second substrates together, a plurality of interconnections arranged on one of the first and second substrates and a plurality of cladding parts covering at least a portion of each of the plurality of interconnections at a location that corresponds to the sealant, each of the cladding parts including a material having a higher melting point than that of the interconnections. By including the cladding parts, a short circuit between the interconnections caused by heat applied to the sealant can be prevented, and safety and reliability of the OLED display device can be improved.

Abstract: A packaged power semiconductor device is provided with voltage isolation between a metal backside and terminals of the device. The packaged power semiconductor device is arranged in an encapsulant defining a hole for receiving a structure for physically coupling the device to an object. A direct-bonded copper (“DBC”) substrate is used to provide electrical isolation and improved thermal transfer from the device to a heatsink. At least one power semiconductor die is mounted to a first metal layer of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. In one embodiment, the packaged power semiconductor device conforms to a TO-247 outline and is capable of receiving a screw for physically coupling the device to a heatsink.