Abstract: The invention concerns a method of testing a semiconductor-on-insulator type structure comprising a support substrate, a dielectric layer having a thickness of less than 50 nm and a semiconductor layer, the structure comprising a bonding interface between the dielectric layer and the support substrate or the semiconductor layer or inside the dielectric layer, characterized in that it comprises measuring the charge to breakdown (QBD) of the dielectric layer and in that information is deduced from the measurement relating to the hydrogen concentration in the layer and/or at the bonding interface. The invention also concerns a method of fabricating a batch of semiconductor-on-insulator type structures including carrying out the test on a sample structure from the batch.

Abstract: A surface mountable multi-chip device is provided which includes first and second lead frames portions and at least two chips. The lead frame portions each include a header region and a lead region. Beneficially, the header regions of the first and second lead frame portions lie in a common plane, with at least one semiconductor chip being placed on each of the header regions. A conductive member link is placed on top of the two chips to electrically and mechanically interconnect the chips.

Abstract: A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.

Abstract: A semiconductor device package is disclosed which includes inter-digitated input and output bond wires configured to increase the negative mutual inductive coupling between the wires, thus reducing the overall parasitic inductance of the device. In one embodiment, the microelectronic component includes a semiconductor device coupled to a substrate, such as a lead frame, a first set of bond wires connected to the semiconductor device for providing current flow into the semiconductor device, and a second set of bond wires that are in a current loop with the first set of bond wires and are connected to the semiconductor device for providing current flow out of the semiconductor device, wherein the first and second set of bond wires are configured in an inter-digitated pattern to increase the magnitude of mutual inductive coupling between the first and second set of bond wires.

Abstract: A surface mountable multi-chip device is provided which includes first and second lead frames portions and at least two chips. The lead frame portions each include a header region and a lead region. Beneficially, the header regions of the first and second lead frame portions lie in a common plane, with at least one semiconductor chip being placed on each of the header regions. A conductive member link is placed on top of the two chips to electrically and mechanically interconnect the chips.

Abstract: A packaged integrated circuit device with a multi-level leadframe has a plurality of integral capacitors formed by placing a thin dielectric layer between a lower leadframe and an upper leadframe, one of the leadframes being subdivided into a plurality of portions, each subdivided portion with an accessible tab for wire attachment. The planar capacitors are bonded to the bottom surface of the semiconductor chip and act as a die support paddle. Each capacitor may be configured to provide the desired voltage decoupling and noise suppression for a particular portion of the integrated circuit to which it is connected. Capacitors useful for other purposes may be likewise provided in the package.

Abstract: The present invention is a novel field effect transistor having a channel region formed from a narrow bandgap semiconductor film formed on an insulating substrate. A gate dielectric layer is formed on the narrow bandgap semiconductor film. A gate electrode is then formed on the gate dielectric. A pair of source/drain regions formed from a wide bandgap semiconductor film or a metal is formed on opposite sides of the gate electrode and adjacent to the low bandgap semiconductor film.

Abstract: The present invention is a novel field effect transistor having a channel region formed from a narrow bandgap semiconductor film formed on an insulating substrate. A gate dielectric layer is formed on the narrow bandgap semiconductor film. A gate electrode is then formed on the gate dielectric. A pair of source/drain regions formed from a wide bandgap semiconductor film or a metal is formed on opposite sides of the gate electrode and adjacent to the low bandgap semiconductor film.

Abstract: In a manufacturing process of an SOI structure semiconductor device in which an MOS capacitor is located on an SOI substrate, the capacitor insulating film of the MOS capacitor is prevented from degrading due to a bimetal effect, which is caused by a thermal treatment and characteristic to the SOI substrate. A trench is formed to surround the MOS capacitor in the SOI substrate, thick oxide films are formed on sidewalls defining the trench, and the trench is filled with polysilicon to complete a trench isolation layer. Because the thick oxide films have a coefficient of thermal expansion that is different from that of a silicon semiconductor layer of the SOI substrate, the thick oxide films are able to prevent the capacitor insulating film from degrading in film quality due to the thermal treatment in the manufacturing process. As a result, an SOI semiconductor device in which an MOS capacitor on an SOI substrate offers performance comparable to an MOS capacitor on a silicon substrate can be formed.

Abstract: In one embodiment of the invention, an integral capacitor includes a power plane, a ground plane, and a dielectric layer. The power plane has a power surface and a power periphery. The power plane couples power to signals of an integrated circuit operating at a fundamental frequency. The first ground plane have a first ground surface and a first ground periphery. The first ground plane couples ground to the signals. The first ground plane is separated from the power plane by a first distance. The first ground surface is larger than the power surface and the first ground periphery extends at least a second distance from the power periphery. The second distance is at least larger than N times the first distance. The dielectric layer is formed between the power plane and the first ground plane.

Abstract: A packaged integrated circuit device with a multi-level leadframe has a plurality of integral capacitors formed by placing a thin dielectric layer between a lower leadframe and an upper leadframe, one of the leadframes being subdivided into a plurality of portions, each subdivided portion with an accessible tab for wire attachment. The planar capacitors are bonded to the bottom surface of the chip and act as a die support paddle. Each capacitor may be configured to provide the desired voltage decoupling and noise suppression for a particular portion of the integrated circuit to which it is connected. Capacitors useful for other purposes may be likewise provided in the package.

Abstract: Resistance elements having plural sheet resistances or resistance elements having different conduction types are formed on a semiconductor integrated circuit device in fewer steps. An oxide film is formed on a silicon semiconductor substrate. A poly-silicon film is formed on the silicon oxide film. A resist film is used to make poly-silicon pattern pieces 6a having an appropriate length in parallel. The widths of the pattern pieces are different. When boron is ion-implanted in two directions inclined to the substrate (at angles of 45° to the substrate surface from the upper left and the upper right), ion implanted areas are formed in both side faces of the pattern pieces. The resultant is annealed and then the impurity is diffused to be activated. This causes the formation of resistance elements having the different concentrations of the impurity, corresponding to the widths of the pattern pieces.

Abstract: A capacitor assembly having one or more capacitors embedded in the core layer of a package having integrated circuits (ICs) mounted thereon. Each embedded capacitor has plural pairs of first and second electrodes and the package core layer has plural sets of first and second vias dispersed over the pairs of electrodes and being connected thereto. A metal layer is provided on the core layer and includes a first portion having at least one metal strip and a second portion, electrically isolated from each strip. Each metal strip is positioned such that it is extended to overlie both the first electrode of a distinct pair of electrodes and the second electrode of an adjacent, succeeding pair of electrodes and effects a mutual electrical connection between them through first and second vias associated therewith, respectively.

Abstract: A packaged integrated circuit device with a multi-level leadframe has a plurality of integral capacitors formed by placing a thin dielectric layer between a lower leadframe and an upper leadframe, one of the leadframes being subdivided into a plurality of portions, each subdivided portion with an accessible tab for wire attachment. The planar capacitors are bonded to the bottom surface of the chip and act as a die support paddle. Each capacitor may be configured to provide the desired voltage decoupling and noise suppression for a particular portion of the integrated circuit to which it is connected. Capacitors useful for other purposes may be likewise provided in the package.

Abstract: A packaged integrated circuit device with a multi-level lead frame has a plurality of integral capacitors formed by placing a thin dielectric layer between a lower lead frame and an upper lead frame, one of the lead frames being subdivided into a plurality of portions, each subdivided portion with an accessible tab for wire attachment. The planar capacitors are bonded to the bottom surface of the chip and act as a die support paddle. Each capacitor may be configured to provide the desired voltage decoupling and noise suppression for a particular portion of the integrated circuit to which it is connected. Capacitors useful for other purposes may be likewise provided in the package.

Abstract: A MOSFET device is formed on a P- doped semiconductor substrate with an N- well formed therein, with a pair of isolation regions formed in the N- well with a gate oxide layer formed above the N- well. An FET device is formed with source and drain regions within the N-well, and a gate electrode formed above the gate oxide layer aligned with the source and drain regions. The gate electrode comprises a stack of layers. A polysilicon layer is formed on the gate oxide layer. A tungsten nitride dopant barrier layer is formed upon the polysilicon layer having a thickness of from about 5 nm to about 20 nm, and a tungsten silicide layer is formed upon the tungsten nitride layer.

Abstract: A packaged integrated circuit device with a multi-level lead frame has a plurality of integral capacitors formed by placing a thin dielectric layer between a lower lead frame and an upper lead frame, one of the lead frames being subdivided into a plurality of portions, each subdivided portion with an accessible tab for wire attachment. The planar capacitors are bonded to the bottom surface of the chip and act as a die support paddle. Each capacitor may be configured to provide the desired voltage decoupling and noise suppression for a particular portion of the integrated circuit to which it is connected. Capacitors useful for other purposes may be likewise provided in the package.

Abstract: A high speed diode with a low forward-bias turn-on voltage is formed by a heterojunction between a layer of doped semiconductor material that has a narrow bandgap energy of not more than about 0.4 eV, and a layer of oppositely doped semiconductor material that has a substantially wider bandgap energy. The device operates with a lower turn-on voltage than has previously been attainable, despite lattice mismatches between the two materials that can produce strain and substantial lattice dislocations in the low bandgap material. The two materials are selected so that the valence and conduction band edge discontinuities at the heterojunction enable a forward carrier flow but block a reverse carrier flow across the junction under forward-bias conditions. Preferred material systems are InAs for the narrow bandgap material, InGaAs for the wider bandgap material and InP for the substrate, or AlSb for the wider bandgap material and GaSb for the substrate.

Abstract: A memory board includes a board, a RAM (random access memory), a back-up battery for supplying a back-up power to the RAM, and a switch to switch a power source from a main power to the back-up battery when the voltage of the main power drops below a predetermined value. The back-up battery is located at the same position where either the switch or the RAM is located and mounted to cover the switch or the RAM.

Abstract: A Schottky barrier diode includes a semiconductor substrate, an ohmic electrode formed on a first region of the semiconductor substrate, and a Schottky metal electrode formed on a second region spaced apart from the first region on the semiconductor substrate. The Schottky electrode includes at least one ohmic portion forming an ohmic contact with the semiconductor substrate, whereby rectifying characteristics of the Schottky barrier diode are improved.

Abstract: A semiconductor device includes a diode having a Schottky barrier and a MOS transistor integrally formed in one and the same semiconductor substrate in which the diode and MOS transistor have their main electrode in common use. The diode has a first diode portion having a pn junction in a current-passing direction and a second diode portion having a combination of the Schottky barrier and another pn junction in the current passing direction.

Abstract: A semiconductor rectifier having a high breakdown voltage and a high speed operation is provided, which includes a semiconductor substrate having an N.sup.+ -type semiconductor layer and an N-type semiconductor layer, a P.sup.+ -type semiconductor layer formed in the N-type semiconductor layer to provide a PN junction therebetween, the P.sup.+ -type semiconductor layer defining exposed regions of the N-type semiconductor layer, and a metal layer provided on an entire surface of the semiconductor substrate having the P.sup.+ -type semiconductor layer to provide contact surfaces of Schottky barrier between the metal layer and each of the exposed regions of the N-type semiconductor layer. In the structure, a configuration of the PN junction is provided to satisfy conditions given by 0.degree.<.theta..ltoreq.135.degree. and 3Wbi.ltoreq.W.ltoreq.2W.sub.B where .theta.