Abstract: According to an aspect of the present invention, there is provided a semiconductor IC that includes a plurality of standard cells arranged in a first direction on a semiconductor substrate, and a first diffusion layer connected to a first power source and a second diffusion layer connected to a second power source in the each standard cell, wherein the first diffusion layers as well as the second diffusion layers of neighboring standard cells are integrally formed.

Abstract: A single evaluation portion is formed by disposing a plurality of MIS transistors used for evaluation having substantially the same structure as that of an actually used MIS transistor. In the evaluation portion, the respective source regions, drain regions, and gate electrodes of the MIS transistors used for evaluation are electrically connected in common to a source pad, a drain pad, and a gate pad, respectively. If the effective gate width of the single evaluation portion exceeds a given value, variations in characteristics evaluated by the evaluation portion approach variations in the characteristics of the entire semiconductor device. The accuracy of evaluating the characteristics of the semiconductor device can thus be improved by using the evaluation portion.

Abstract: A current reference, which may be fabricated independently, on a die, as part of an integrated circuit, or a system, or in various other forms, is disclosed. The current reference may include a voltage source having a substantially temperature stable output voltage, a first semiconductor device biased by the substantially temperature stable output voltage to provide a first output current, and a second semiconductor device providing a second output current, wherein a reference current is provided approximately equal to the difference between the first and second output currents.

Abstract: A new test structure to locate bridging defects in a conductive layer of an integrated circuit device is achieved. The test structure comprises a line comprising a conductive layer overlying a substrate. The line is coupled to ground. A plurality of rectangles comprises the conductive layer. The rectangles are not connected to the line or to other rectangles. Near edges of the rectangles and of the line are parallel. The rectangles are floating. The test structure is used with a passive voltage contrast test in a scanning electron microscope. A test structure and method to measure critical dimensions is disclosed.

Abstract: A technique is disclosed which facilitates the layout of op amp cells, for example, two-stage op amp cells or three-stage op amp cells, to provide larger operational amplifiers. In accordance with one aspect, the op amp cells can be suitably coupled in parallel to provide a larger operational amplifier. This paralleling aspect can be facilitated by connecting the respective negative and positive inputs of a predetermined number of input gm stages together, connecting the outputs of a predetermined number of output gm stages together, and connecting a predetermined number of intermediate internal nodes between the input gm stages and the output gm stages together, without the occurrence of saturation of the internal nodes. In addition, the input and output characteristics of operational amplifier can be suitably improved.

Abstract: The present invention aims at improving the lifetime of the wiring connecting to the hole nearest to the bonding pad and thereby improving the reliability of the semiconductor device. The invention relates to such semiconductor device and method of manufacturing the semiconductor device. The semiconductor device includes a plurality of first metal layers connected to a bonding pad, and plurality of aluminum wirings respectively connected to the first metal layers. The plurality of aluminum wirings are connected to a single second metal layer and have a length equal to or short than Blech Length.

Abstract: A bipolar silicon transistor includes at least one emitter zone with n.sup.+ arsenic doping and with a phosphorus doping. The ratio between arsenic dopant concentration and phosphorus dopant concentration is between 10:1 and 500:1 in the at least one emitter zone. The at least one emitter zone may also have a penetration depth of less than 0.5 .mu.m. A method for producing a bipolar silicon transistor includes implanting a n.sup.+ -doped emitter zone with arsenic, implanting the n.sup.+ -doped emitter zone with phosphorus, setting a ratio in the n.sup.+ -doped emitter zone between the arsenic dopant concentration and phosphorus dopant concentration to between 10:1 and 500:1, and annealing crystal defects.

Abstract: The present invention reduces parasitic capacitance in a capacitive element distribution system by running unit electrode lead lines and common electrode lead lines in different directions so that the conductor lines may be sufficiently separated to suppress parasitic capacitance.

Abstract: A semiconductor device implemented using a transistor (Q1) including at least one emitter (E1) and a transistor (Q2) which is larger than the transistor (Q1) including n emitters (E21 to E2n) each having the same area as the emitter (E1) of the transistor (Q1). The emitter (E1) of the transistor (Q1) is disposed between the emitters (E21 to E2n) of the transistor (Q2). When there is deflection of a substrate due to a stress to cause distortion in shape of the emitters, the emitter (E1) has much less distortion in shape than the emitters located on the end portions of the row region in the longitudinal direction. Since the transistor (Q2) has a number of emitters, the distortion in shape of the emitters (E21 to E2n) of the transistor (Q2), if any, has little effect on the whole.

Abstract: SRAM cells are manufactured with balanced, high-resistance load resistances by having substantially all of dielectric layer directly over the polysilicon load resistor covered by a metal layer. The metal layer protects the polysilicon during subsequent processing which can adversely alter its characteristics.

Abstract: The invention concerns approaches to interconnecting individual field-effect transistors (FETs) in integrated circuits (ICs), in order to provide a larger, composite transistor. In one approach, the individual FETs are positioned symmetrically about centroids, which are themselves distributed symmetrically over the IC. The invention allows individual digital transistors to be connected into a larger, composite, analog transistor.

Abstract: AMOS transistor with enhanced electrical characteristics and a method for manufacturing the same. In the channel region, a first impurity region is provided for adjusting a threshold voltage, a second impurity region is provided which serves as a diffusion barrier, and a third impurity region is provided for preventing a punchthrough. These regions are formed sequentially at subsequently shallower depths in the substrate. The disclosed transistor minimizes short-channel effects and punchthrough without reducing the current driving capability of the device.

Abstract: A particular layout (38) of transistors along a continuous conductor line (54), such as the transistors in a CMOS inverter, has been found which reduces breaks or voids in the conductor line due to electromigration of the conductor atoms from predominantly unidirectional current flows. The conductor line may be a metal line. By alternating the two types of transistors, p- and n-type (40, 41, 46 & 47), along the length of the metal line, almost the entire length of the line can be changed to one with bidirectional current flow which significantly reduces the mean-time-to-failure for electromigration-related damage. The layout arrangement will find greater advantage for large transistors, long metal lines, relatively large unidirectional current flows and devices that run at high frequency, such as clock drivers.

Abstract: The invention concerns approaches to interconnecting individual field-effect transistors (FETs) in integrated circuits (ICs), in order to provide a larger, composite transistor. In one approach, the individual FETs are positioned symmetrically about centroids, which are themselves distributed symmetrically over the IC. The invention allows individual digital transistors to be connected into a larger, composite, analog transistor.

Abstract: A semiconductor-insulator-semiconductor (SIS) structure diode device for providing fast optoelectronic switching with stimulated emission. The device includes a substrate which has a buffer layer disposed on top thereof. An n-type cladding layer is disposed on top of the buffer layer. An undoped i-region is disposed on top of the buffer layer. The i-region includes at least one quantum well disposed between two waveguide layers. A lightly doped p-type cladding layer is disposed on top of the i-region. A contact layer is further disposed on top of the p-type cladding layer. First and second contact terminals are included for providing a two-terminal device. The diode advantageously provides good lasing performance, significant negative differential resistance and strong light sensitivity. In an alternate embodiment, a third terminal is connected to the undoped i-region to thereby form a three terminal device.

Abstract: An integrated circuit constructed using exposure and etching steps in an FET fabrication process incorporates electrical lead structures coupled to distributed IC components to compensate for process variation. The electrical lead structure (10,14,16,24,34is composed of an etchable conductive layer constructed in a configuration with graduated coupling widths (B,C,D,E . . . ) forming a graduated range of respective etchable dimensions arranged in an electrically coupled sequence. A primary lead (IA) is coupled at a first end to the widest coupling width (B). A plurality of secondary leads (0B,0C,0D,0E . . . ) distributed along the electrically coupled sequence of graduated coupling widths are coupled respectively to the distributed electrical component elements (P1B,P1C,P1D,P1E . . . ) (N1B,N1C,N1D,N1E . . . ) (RB,RC,RD,RE . . . ) of a distributed electrical component such as a PMOS transistor (P1) NMOS transistor (N1) or resistor (R). The graduated coupling widths (B,C,D,E . . .

Abstract: Improved, edge compensated capacitors and a method for making the same are presented. The present invention arranges individual cells of capacitors and uses passive dummy cells so as to achieve a ratio between the length of the exposed perimeters of the cells of the two capacitors that is equal to the desired capacitance ratio between the two capacitors. By doing so, the edge shrinkage effects on both cells are taken into account, and accurate capacitor ratios are maintained. In one embodiment of the invention the number of intersections between exposed edges of the cells of the two capacitors are also adjusted to conform to the capacitor ratio to achieve additional edge shrinkage compensation.

Abstract: A field-effect transistor device comprising a p-type silicon substrate, a pair of n-channel MOS transistors, and a wiring means connecting the MOS transistors. The first MOS transistor has a gate electrode provided above the substrate and extending in one direction, and two regions formed in the substrate, located on two opposing sides of the gate electrode, and serving as a source and a drain. The second MIS transistor has a gate electrode provided above the substrate and extending in said one direction, and two regions formed in the substrate, located on two opposing sides of this gate electrode, and serving as a source and a drain. The wiring means includes bit lines BL and BL which permit the source-drain paths of the first and second MIS transistors to be oriented in the same direction.