Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a core substrate with a first conductive structure having a first thickness on the core substrate, and a second conductive structure having a second thickness on the core substrate, where the first thickness is different than the second thickness.

Abstract: An integrated circuit package is provided with a thin-film battery electrically connected to and encapsulated with an integrated circuit die. The battery can be fabricated on a dedicated substrate, on the die pad, or on the integrated circuit die itself.

Abstract: A semiconductor device includes: a spiral-shaped inductor formed to include a metal wire; and a horseshoe-shaped inductor formed to include the metal wire. The horseshoe-shaped inductor is arranged such that an opening of the horseshoe-shaped inductor is disposed opposite to the spiral-shaped inductor. Accordingly, unnecessary wave (spurious) output from a transmitting unit can be reduced as small as possible.

Abstract: An embodiment is a device comprising a substrate, a metal pad over the substrate, and a passivation layer comprising a portion over the metal pad. The device further comprises a metal pillar over and electrically coupled to the metal pad, and a passive device comprising a first portion at a same level as the metal pillar, wherein the first portion of the passive device is formed of a same material as the metal pillar.

Abstract: An objective is to provide a component-incorporated wiring substrate capable of solving a problem caused by an increase in length of wiring lines that connect a component and a capacitor. A component-incorporated wiring substrate 10 includes a core substrate 11, a first capacitor 301, a wiring laminate portion 31, and a second capacitor 101. An accommodation hole portion 90 of the core substrate 11 accommodates the first capacitor 101 therein, and a component-mounting region 20 is set on a surface 39 of the wiring laminate portion 31. The second capacitor 101 has electrode layers 102, 103 and a dielectric layer 104. The second capacitor 101 is embedded in the wiring laminate portion 31 in such a state that first main surfaces 105, 107 and second main surfaces 106, 108 are in parallel with the surface 39 of the wiring laminate portion 31, and is disposed between the first capacitor 301 and the component-mounting region 20.

Abstract: A semiconductor package includes a substrate, at least one chip including a first side and a backside opposite of the first side, the first side electrically coupled to the substrate, a conductive layer coupled to the backside of the at least one chip, and at least one electronic component coupled to the conductive layer and in electrical communication with the substrate.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate having a component side; mounting a device over the component side; forming a shield connector on the component side adjacent the device; forming a package interconnect on the component side outside a region having the shield connector and the device; applying an encapsulant around the package interconnect, the shield connector, and the device; and mounting a shield structure on the encapsulant, the shield connector, and the device, with the package interconnect partially exposed.

Abstract: A nonvolatile memory apparatus includes a first electrode, a second electrode, a variable resistance layer, a resistance value of the variable resistance layer reversibly varying between a plurality of resistance states based on an electric signal applied between the electrodes. The variable resistance layer includes at least a tantalum oxide, and is configured to satisfy 0<x<2.5 when the tantalum oxide is represented by TaOx; and wherein when a resistance value between the electrodes is in the low-resistance state is RL, a resistance value between the electrodes is in the high-resistance state is RH, and a resistance value of a portion other than the variable resistance layer in a current path connecting a first terminal to a second terminal via the first electrode, the variable resistance layer and the second electrode, is R0, R0 satisfies RL<R0.

Abstract: Capacitors are formed in metallization layers of semiconductor device in regions where functional conductive features are not formed, more efficiently using real estate of integrated circuits. The capacitors may be stacked and connected in parallel to provide increased capacitance, or arranged in arrays. The plates of the capacitors are substantially the same dimensions as conductive features, such as conductive lines or vias, or are substantially the same dimensions as fill structures of the semiconductor device.

Abstract: In order to reduce a thermal stress applied by a metal cap to a semiconductor chip: a semiconductor chip (2) is bonded to a flat portion (11) of a metal cap (1); side wall portions of the metal cap (1) serve as external connection terminals (13); and a slit (7) is formed in the metal cap (1) so as to cross the semiconductor chip (2), so a bonding region between the semiconductor chip (2) and the metal cap (1) is divided into small bonding regions to reduce thermal stresses applied to the respective bonding regions. Therefore, peeling can be prevented in respective bonding regions, whereby a small-size semiconductor device in which the semiconductor chip is bonded to the metal cap with improved bonding reliability is obtained.

Abstract: A semiconductor chip and a semiconductor device mounting the semiconductor chip capable of increasing a capacitance of a capacitor without reducing the number of signal bumps or power bumps of a package and the number of C4 solder balls of the semiconductor chip, and achieving a stable power supply with suppressing fluctuations of power at a resonance frequency without a limitation in a position to mount a capacitor for lowering noise of a signal transceiving interface block. In the semiconductor device, a via hole is provided to the semiconductor chip, a power-supply electrode connected to the via hole is provided to a back surface of the semiconductor chip, and a capacitor is mounted to the electrode on the back surface. And, a high-resistance material is used for a material of a power-supply via hole inside the semiconductor chip, thereby increasing the resistance and lowering the Q factor.

Abstract: A semiconductor module structure and a method of forming the semiconductor module structure are disclosed. The structure incorporates a die mounted on a substrate and covered by a lid. A thermal compound is disposed within a thermal gap between the die and the lid. A barrier around the periphery of the die extends between the lid and the substrate, contains the thermal compound, and flexes in response to expansion and contraction of both the substrate and the lid during cycling of the semiconductor module. More particularly, either the barrier is formed of a flexible material or has a flexible connection to the substrate and/or to the lid. The barrier effectively contains the thermal compound between the die and the lid and, thereby, provides acceptable and controlled coverage of the thermal compound over the die for heat removal.

Abstract: A kind of microphone package structure includes at least of a substrate, a sound processing unit, an upper cap and other devices. There would be at least one trench set on the substrate, and a separation gap between the trench and the bonding pad of the substrate is maintained. After connective paste is smeared on the surface of the substrate, the trench would be assembled with other devices. This kind of package structure could prevent a short circuit being caused by the overflowing of the connective paste.

Abstract: An integrated circuit includes a first integrated circuit die having a first circuit and a first inductive interface and a second integrated circuit die having a second circuit and a second inductive interface. A substrate is coupled to support the first integrated circuit die and the second integrated circuit die, the substrate including a magnetic communication path aligned with the first inductive interface and the second inductive interface, to magnetically communicate signals between the first circuit and the second circuit.

Abstract: In a semiconductor device, a plurality of triple-stacked structures all having the same structure are provided. Each of the triple-stacked structures includes one lower electrode layer, at least one upper electrode layer and one dielectric layer sandwiched by the lower electrode layer and the upper electrode layer.

Abstract: A semiconductor device 1 includes an interconnect 12, a conductive layer 14 (first conductive layer), an insulating layer 20 (first insulating layer), another conductive layer 30 (second conductive layer), another insulating layer 40 (second insulating layer), a via plug 52 (first via plug), and another via plug 54 (second via plug). In the semiconductor device 1, the conductive layer 14, the insulating layer 20 and the conductive layer 30 constitute a MIM capacitor (capacitor element). To be more detailed, the conductive layer 14, the insulating layer 20 and the conductive layer 30 serve as a lower electrode, an insulating capacitor film and an upper electrode, respectively. The insulating layer 40 covers both the conductive layer 30 and the interconnect 12. The insulating layer 40 works as the etching stopper for the via plugs 52, 54.

Abstract: One embodiment of the present invention provides advice for providing a low noise power supply package to an integrated circuit comprising a semiconductor die, input/output power supply terminals, and an array of embedded ceramic capacitors selected from discrete, planar and combinations thereof wherein said capacitors are placed in the locations selected from within the perimeter of the shadow of the semiconductor die, partially within the perimeter of the shadow of the semiconductor die, near the perimeter of the shadow of the semiconductor die, and combinations thereof.

Abstract: An integrated current sensor package includes an integrated circuit having a coil in a metal layer of the circuit. A wire is placed close enough to the coil such that the coil and the wire are inductively coupled with each other.

Abstract: A capacitive interposer (caposer) is disposed inside an integrated circuit package between a die and an inside surface of the package. Conductive layers within the caposer constitute a bypass capacitor. In a through-hole caposer, micro-bumps on the die pass through through-holes in the caposer and contact corresponding landing pads on the package. As they pass through the caposer, power and ground micro-bumps make contact with the plates of the bypass capacitor. In a via caposer, power and ground micro-bumps on the die are coupled to power and ground landing pads on the package as well as to the plates of the bypass capacitor by power and ground vias that extend through the caposer. In signal redistribution caposer, conductors within the caposer redistribute signals between die micro-bumps and package landing pads. In an impedance matching caposer, termination structures within the caposer provide impedance matching to a printed circuit board trace.

Abstract: One embodiment of the present invention provides a device for providing a low noise power supply package to an IC in the mid-frequency range of 1 MHz to 3 GHz including installing in said package an array of embedded discrete ceramic capacitors, and optionally planar capacitor layers. A further embodiment provides a device for providing a low noise power supply package to an IC in the mid-frequency range of 1 MHz to 3 GHz including an array of embedded discrete ceramic capacitors with different resonance frequencies, arranged in such a way that the capacitor array's impedance vs frequency curve in the critical mid-frequency range yields impedance values at or below a targeted impedance value.

Abstract: An integrated broadband array capacitor includes at least two regions with varying capacitance and response times. The broadband array capacitor is disposable on a socket or is integral with a socket. A method of operating the broadband array capacitor includes responding to load transients from each of the at least two regions. A computing system is also disclosed that includes the broadband array capacitor.

Abstract: An semiconductor device package (10) includes a semiconductor device (die) (12) and passive devices (14) electrically connected to a common lead frame (17). The lead frame (17) is formed from a stamped and/or etched metallic structure and includes a plurality of conductive leads (16) and a plurality of interposers (20). The passive devices (14) are electrically connected to the interposers (20), and I/O pads (22) on the die (12) are electrically connected to the leads (16). The die (12), passive devices (14), and lead frame (17) are encapsulated in a molding compound (28), which forms a package body (30). Bottom surfaces (38) of the leads (16) are exposed at a bottom face (34) of the package (10).

Abstract: A semiconductor device includes a capacitor which includes a capacitor insulating film at least including a first insulating film and a ferroelectric film formed in contact with the first insulating film, containing a compound of a preset metal element and a constituent element of the first insulating film as a main component and having a dielectric constant larger than that of the first insulating film, a first capacitor electrode formed of one of Cu and a material containing Cu as a main component, and a second capacitor electrode formed to sandwich the capacitor insulating film in cooperation with the first capacitor electrode.

Abstract: A capacitive element is characterized by including: a base (12); a lower barrier layer (13) formed on the base (12); capacitors (Q1 and Q2) made by forming a lower electrode (14a), capacitor dielectric layers (15a), and upper electrodes (16a) in this order on the lower barrier layer (13); and an upper barrier layer (20) covering at least the capacitor dielectric layers (15a) and the lower barrier layer (13).

Abstract: A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394.

Abstract: One embodiment of the present invention provides capacitive decoupling on the surface of a semiconductor die, instead of providing the decoupling on a package or printed circuit board to which the semiconductor die is attached. In this embodiment, a surface of a semiconductor die includes exposed power and ground conductors, which are electrically coupled to internal power and ground nodes within the semiconductor die. To provide the wafer-level decoupling, a plurality of bypass capacitors are electrically coupled between pairs of exposed power and ground conductors, so that the plurality of bypass capacitors reduce voltage noise between the power and ground conductors on the semiconductor die.

Abstract: The invention provides methods for packaging for electronic devices that are light or other radiation-sensitive, such as image sensors including CCD or CMOS chips. In one embodiment of the invention, an image sensor package is assembled by surrounding a chip with a barrier of transfer mold compound and covering the chip with a transparent lid. In another embodiment of the invention, the perimeter area of a chip, including interconnections such as wire bonds and bond pads, is encapsulated with a liquid dispensed epoxy, and a transparent lid is attached. In yet another embodiment of the invention, chip encapsulation is accomplished with a unitary shell of entirely transparent material. In yet another embodiment of the invention, a substrate-mounted chip and a transparent lid are loaded into a transfer mold that holds them in optimal alignment. The transfer mold is then filled with molding compound.

Abstract: An apparatus for filtering noise from an input/output (I/O) signal is disclosed. In various embodiments, the apparatus may be an array capacitor, and may be disposed between an electronic package and an underlying substrate such as a printed circuit board.

Abstract: A package for semiconductor light emitting element is described. The package includes a first metal substrate having a cup shaped recess portion, an insulating member having a first cup shaped opening, provided on the first metal substrate, and a second metal substrate having a second cup shaped opening, provided on the insulating member with being electrically insulated from the first metal substrate, having a cavity in the inner surface.

Abstract: Systems are provided for producing a low frequency filter pole. A first bond pad is coupled to a power source. A second bond pad is inductively connected to the first bond pad by a first bond wire. A capacitor is connected to the second bond pad. A third bond pad is inductively connected to the second bond pad by a second bond wire. The second bond wire, in conjunction with the capacitor, forms a low frequency filter pole to mitigate noise in a regulated signal provided at the third bond pad.

Abstract: A multilayer ceramic capacitor (10) having reduced inductance which is separated into a first layer body (11) and a second layer body (12). The first layer body (11) and the second layer body (12) are formed by alternately layering inner electrodes (inner electrode 13a, inner electrode 13b) so as to face each other and sandwich ceramic layers (14). The ceramic layers (14) of the second layer body (12) are thicker than the ceramic layers (14) of the first layer body (11), so as to compensate for electrode height difference. Moreover, in the second layer body (12), the inner electrodes (13b) are electrically connected by via electrode (15b) so that the part of the via electrode (15b) extending without connection to an inner electrode (13b) is shortened.

Abstract: An optical scanner package having a heating dam is provided. The optical scanner package having a heating dam includes: an optical scanner on which a mirror surface is formed; a ceramic package in which the optical scanner is installed at the bottom of a cavity thereof; a glass lid covering a sidewall of the ceramic package; a heating dam formed on the sidewall of the ceramic package; and solder on the heating dam sealing between the glass lid and the sidewall of the ceramic package. The heating dam locally heats the solder to form hermetic sealing.

Abstract: An integrated circuit which includes a circuit board having passive elements embedded in its body.

Abstract: A semiconductor device comprises a BGA substrate having one principal plane furnished with a large number of solder balls, the solder balls constituting a ball grid array; a semiconductor chip mounted on another principal plane of the BGA substrate, the semiconductor chip being electrically connected to the BGA substrate by metal wires; and chip capacitors mounted on the semiconductor chip to reduce power source noise.

Abstract: In one embodiment, a sacrificial layer is deposited over a base layer. The sacrificial layer is used to define a subsequently formed floating metal structure. The floating metal structure may be anchored into the base layer. Once the floating metal structure is formed, the sacrificial layer surrounding the floating metal structure is etched to create a unity-k dielectric region separating the floating metal structure from the base layer. The unity-k dielectric region also separates the floating metal structure from another floating metal structure. In one embodiment, a noble gas fluoride such as xenon difluoride is used to etch a sacrificial layer of polycrystalline silicon.

Abstract: Systems and methods for substrate layers used in attaching devices to a semiconductor package are disclosed. A novel pad structure may be employed on a substrate layer which has pads, each pad having a common electrical potential. Multiple pad openings may be employed on a single pad, allowing the attachment of multiple terminals of one or more decoupling capacitors to a single pad. These pads and pad openings can be arranged according to the type of decoupling capacitor employed, allowing a greater total pad area to be utilized in conjunction with a set of pad openings, while simultaneously allowing the multiple pad openings on the pad to be placed closer together, reducing the ESL and ESR of the path between the semiconductor and the decoupling capacitors, increasing the mechanical reliability of the semiconductor package and allowing a higher density of decoupling capacitors to be coupled to a given area.

Abstract: A lower interconnection is provided on a semiconductor substrate. A MIM capacitive element is provided on a first interlayer insulation film in which the lower interconnection is buried, and includes a lower electrode, an upper electrode, and a dielectric film sandwiched therebetween. An upper interconnection is provided on a second interlayer insulation film in which the MIM capacitive element is buried. A contact electrically connects the lower electrode and the upper interconnection. The lower electrode is mainly formed of Al, so that they are lower in electrical resistance than barrier metal, and also low in stress value. Therefore, it becomes possible to widen the area of the lower electrode for electrically connecting the contact while restraining their influences on charge accumulation and close contact between the lower electrode and the insulation film. In addition, since the electrical resistance is lowered, the thickness of the lower electrode can be increased.

Abstract: A high frequency integrated circuit includes a die, a package and capacitive bond. The die includes a circuit that processes a high frequency signal and also includes at least one bonding pad coupled to the circuit. The package includes a plurality of bonding posts, at least one of the bonding posts is allocated to the at least one bond pad of the die. A bonding capacitor couples the at least one bond pad on the die to the at least one bond post of the package.

Abstract: A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394.

Abstract: A hermetic sealing cap member capable of suppressing deterioration of characteristics of an electronic component resulting from a sealant such as solder coming into contact with the electronic component in a package is obtained. This hermetic sealing cap, which is a hermetic sealing cap employed for an electronic component storing package for storing an electronic component (5, 34), comprises a hermetic sealing cap member (11, 41), a first plating layer (12, 42) formed at least on a region other than a region of the hermetic sealing cap member formed with a sealant (3, 32) and a second plating layer (13, 43), formed on the region of the hermetic sealing cap member on which the sealant is arranged, containing a material superior in wettability with the sealant to the first plating layer.

Abstract: A method for patterning layers made of ruthenium or ruthenium(IV) oxide and a capacitor comprising at least one electrode which is constructed from ruthenium or ruthenium(IV) oxide at least in sections. A layer made of ruthenium or ruthenium(IV) oxide is deposited on a substrate and said layer is subsequently covered with a covering layer at least in sections. Through heat treatment of the construction thus obtained in an oxygen atmosphere, the ruthenium is converted into RuO4 in the uncovered sections and removed by sublimation. The method enables the simple patterning of layers made of ruthenium or ruthenium(IV) oxide and the construction of complex structures, such as trench capacitors, for example.

Abstract: A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394.

Abstract: This invention miniaturizes a package of a semiconductor device and simplifies a manufacturing procedure to reduce a manufacturing cost. A semiconductor wafer formed of a plurality of semiconductor chips formed with MEMS devices and wiring thereof on front surface thereof and a cap arrayed wafer disposed with a plurality of sealing caps are attached to seal the MEMS devices in cavities between them. Then, a plurality of via-holes is provided penetrating through the semiconductor wafer to form embedded electrodes therein, and bump electrodes are formed thereon. After this procedure, this structure is cut along scribe lines to be divided into each of packages.

Abstract: A circuit carrier and a package structure thereof are provided. The circuit carrier comprises a substrate having a surface, a plurality of passive component electrode pads or a plurality of passive component electrode planes on the surface of the substrate for electrically connecting a passive component corresponding to the plurality of passive component electrode pads, and a solder mask layer covering the surface of the substrate and including at least a solder mask opening, that entirely exposing the passive component electrode pads or a portion of the surface of each the passive component electrode plane corresponding to the passive component. Because there is no solder mask layer between the bottom of the passive component and the substrate, the gap between the passive component and the substrate will become wider. Hence, remaining flux can be entirely removed in order to increase the yield rate of the subsequent high temperature process.

Abstract: A system to package high performance microelectronic devices, such as processors, responds to component transients. In one embodiment, the system includes a decoupling capacitor that is disposed between a Vcc electrical bump and a Vss electrical bump. The decoupling capacitor has Vcc and Vss terminals. The Vcc and Vss terminals share electrical pads with the Vcc electrical bump and the Vss electrical bump. A simple current loop is created that improves the power delivery for the system.

Abstract: In a chip type solid electrolytic capacitor including a capacitor element and a packaging resin covering the capacitor element, the packaging resin has a mount surface and a side surface adjacent to the mount surface. A terminal is electrically connected to the capacitor element and coupled to the packaging resin. The terminal extends along the mount surface and the side surface to have an outer surface exposed from the packaging resin and to have an inner surface opposite to the outer terminal surface. The inner surface has a stepwise shape formed by forging.

Abstract: A semiconductor chip package has a substrate that includes circuit lines provided on first and/or second surfaces, a power plane provided on the second surface, bump lands provided on the second surface and coupled to the circuit lines, and ball lands provided on the first surface. The package further has a semiconductor chip attached to the second surface of the substrate and electrically coupled to the circuit lines, and a dielectric layer provided on the second surface of the substrate. The dielectric layer surrounds laterally the chip, covers the power plane, and exposes the bump lands. The package further has a ground plane provided on both the chip and the dielectric layer, vertical connection bumps provided within the dielectric layer and on the bump lands and electrically coupled to the ground plane, and solder balls provided on the ball lands.

Abstract: A semiconductor device is arranged so as to include (i) a wire L1, connected directly to an LSI chip, which serves as a VGL wire for supplying a voltage VGL to the LSI chip, and (ii) a wire LB1 connected not directly to but to one of a pair of electrodes of a capacitor provided between the wire LB1 and a voltage VGH wire, each of the wire L1 and the wire LB1 including a voltage input terminal. This arrangement provides (i) a semiconductor device, including a built-in capacitor, which makes it possible to shorten time required in an electrical screening test (final test) so as to reduce cost, and (ii) an electrical inspection method of the semiconductor device.

Abstract: A method of fabricating an apparatus including a sealed cavity and an apparatus embodying the method is disclosed. To fabricate the apparatus, a device chip including a substrate and at least one circuit element on the substrate is fabricated. Also, a cap is fabricated. The cap is attached to the device chip using single phase metal alloy to achieve sealed cavity over the circuit element. The single phase metal alloy allows the cap to be diffusion bonded to the device chip at a higher diffusivity thus allowing diffusion at a lower temperature, lower pressure, shorter period, or a combination of these.

Abstract: A multi-chip BGA package has two or more rerouted chips, each of which has one or more electrode plates. The electrode plate is coplanar with rerouting lines on the rerouted chip and may act as a decoupling capacitor, reducing simultaneous switching noise from fluctuations in power voltage, without causing an increase in thickness of the package. Further, each pair of rerouting lines on upper and lower rerouted chips includes two or more interconnection bumps. This reduces inductance and resistance of electric signal propagation. Therefore, the multi-chip BGA package of this invention can realize small, thin, high-speed and high-density memory devices.