With Shorted Pn Or Schottky Junction Other Than Emitter Junction Patents (Class 257/928)
  • Patent number: 8487415
    Abstract: The present invention provides a rectifier element that has a titanium oxide layer interposed between first and second electrodes containing a transition metal with an electronegativity larger than that of Ti, wherein, in the titanium oxide layer, only the interface on the side facing any one of the electrodes has a stoichiometric composition, and wherein the average composition of the whole layer is represented by the formula TiOx (wherein x satisfies the relationship 1.6?x<2), and wherein the rectifying characteristics can be reversed by applying a reverse electrical signal that exceeds the critical reverse electric power between the first and second electrodes in an opposite direction. The present invention also provides a process for producing a rectifier element, which includes the steps of depositing a first electrode that contains a transition metal with an electronegativity larger than that of Ti on a substrate; depositing a layer of titanium oxide (TiOx, wherein x satisfies the relationship 1.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: July 16, 2013
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Hisashi Shima, Hiroyuki Akinaga, Shoji Ishibashi, Tomoyuki Tamura
  • Patent number: 7982285
    Abstract: The present invention provides antifuse structures having an integrated heating element and methods of programming the same, the antifuse structures comprising first and second conductors and a dielectric layer formed between the conductors, where one or both of the conductors functions as both a conventional antifuse conductor and as a heating element for directly heating the antifuse dielectric layer during programming.
    Type: Grant
    Filed: January 8, 2008
    Date of Patent: July 19, 2011
    Assignee: International Business Machines Corporation
    Inventors: Byeongju Park, Subramanian S. Iyer, Chandrasekharan Kothandaraman
  • Patent number: 7671371
    Abstract: A semiconductor layer structure includes a donor substrate and a detach region carried by the donor substrate. A device structure is carried by the donor substrate and positioned proximate to the detach region. The device structure includes a stack of crystalline semiconductor layers. The stack of crystalline semiconductor layers includes a pn junction.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: March 2, 2010
    Inventor: Sang-Yun Lee
  • Patent number: 7569911
    Abstract: An ohmic electrode is formed by stacking a lower Ti layer, a diffusion preventing layer, an upper Ti layers and a metallic (Au) layer on a p-type GaAs layer. The diffusion preventing layer includes tantalum (Ta) or niobium (Nb). Thus, interdiffusion of Ga and As in the p-type GaAs layer and Au in the metallic layer can be prevented, and variation in resistivity of the ohmic electrode in a high-temperature, high-humidity environment can be suppressed.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: August 4, 2009
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshihiko Shiga, Hitoshi Nakamura, Junji Tanimura
  • Patent number: 7358590
    Abstract: A semiconductor device includes a memory with a simple structure, an inexpensive semiconductor device, a manufacturing method and a driving method thereof. One feature is that, in a memory which has a layer including an organic compound as a dielectric, by applying a voltage to a pair of electrodes, the state change caused by the precipitous change in volume (such as bubble generation) is generated between the pair of electrodes. Short-circuiting between a pair of electrodes is promoted by acting force based on this state change. Concretely, a bubble generating area is provided in the memory element to generate a bubble between the first conductive layer and the second conductive layer.
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: April 15, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Mikio Yukawa, Yoshinobu Asami, Ryoji Nomura
  • Patent number: 7276771
    Abstract: A diode is provided which includes a first-conductivity-type cathode layer, a first-conductivity-type drift layer placed on the cathode region and having a lower concentration than the cathode layer, a generally ring-like second-conductivity-type ring region formed in the drift layer, second-conductivity-type anode region formed in the drift layer located inside the ring region, a cathode electrode formed in contact with the cathode layer, and an anode electrode formed in contact with the anode region, wherein the lowest resistivity of the second-conductivity-type anode region is at least 1/100 of the resistivity of the drift layer, and the thickness of the anode region is smaller than the diffusion depth of the ring region.
    Type: Grant
    Filed: June 23, 2006
    Date of Patent: October 2, 2007
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Tatsuhiko Fujihira, Yasushi Miyasaka
  • Patent number: 7187054
    Abstract: A diode is provided which includes a first-conductivity-type cathode layer, a first-conductivity-type drift layer placed on the cathode region and having a lower concentration than the cathode layer, a generally ring-like second-conductivity-type ring region formed in the drift layer, second-conductivity-type anode region formed in the drift layer located inside the ring region, a cathode electrode formed in contact with the cathode layer, and an anode electrode formed in contact with the anode region, wherein the lowest resistivity of the second-conductivity-type anode region is at least 1/100 of the resistivity of the drift layer, and the thickness of the anode region is smaller than the diffusion depth of the ring region.
    Type: Grant
    Filed: March 4, 2005
    Date of Patent: March 6, 2007
    Assignee: Fuji Electric Holdings Co., Ltd.
    Inventors: Tatsuhiko Fujihira, Yasushi Miyasaka
  • Patent number: 7071534
    Abstract: An antifuse structure and method of use are disclosed. According to one embodiment of the present invention a first programming voltage is coupled to a well of a first conductivity type in a substrate of a second conductivity type in an antifuse. A second programming voltage is coupled to a conductive terminal of the second conductivity type in the antifuse to create a current path through an insulator between the conductive terminal and the well to program the antifuse. The first programming voltage may be coupled to an ohmic contact in the well in the antifuse.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: July 4, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Kenneth W. Marr, Shubneesh Batra
  • Patent number: 6975013
    Abstract: A diode is provided which includes a first-conductivity-type cathode layer, a first-conductivity-type drift layer placed on the cathode region and having a lower concentration than the cathode layer, a generally ring-like second-conductivity-type ring region formed in the drift layer, second-conductivity-type anode region formed in the drift layer located inside the ring region, a cathode electrode formed in contact with the cathode layer, and an anode electrode formed in contact with the anode region, wherein the lowest resistivity of the second-conductivity-type anode region is at least 1/100 of the resistivity of the drift layer, and the thickness of the anode region is smaller than the diffusion depth of the ring region.
    Type: Grant
    Filed: October 2, 2002
    Date of Patent: December 13, 2005
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Tatsuhiko Fujihira, Yasushi Miyasaka
  • Patent number: 6770950
    Abstract: A non-volatile semiconductor memory cell structure and method of manufacture. The method includes the steps of forming a shallow first-type well layer, a second-type well layer and a deep first-type well layer over a substrate, forming stack gates over the shallow first-type well layer and finally forming source terminals and drain terminals. The source terminals penetrate through the shallow first-type well layer and connect with the second-type well layer. The drain terminals are close to the surface of the shallow first-type well layer. Both the source terminals and the drain terminals contain second type dopants.
    Type: Grant
    Filed: March 13, 2002
    Date of Patent: August 3, 2004
    Assignee: eMemory Technology Inc.
    Inventors: Ching-Song Yang, Shih-Jye Shen, Ching-Hsiang Hsu
  • Patent number: 6677612
    Abstract: A method of forming a MOS device using doped and activated n-type and p-type polysilicon layers includes forming a first doped and activated polysilicon area (either n-type and p-type) on a substrate. An isolation material layer is formed abutting the first activated area. A second doped and activated polysilicon area of opposite conductivity type from the first activated area is formed adjacent to the isolation material layer. The second activated opposite area has a height that does not exceed that of the first doped and activated polysilicon layer. Further processing may be effected to complete the MOS device. The method of the present invention eliminates ion implantation and annealing steps used in previously existing methods.
    Type: Grant
    Filed: August 28, 2001
    Date of Patent: January 13, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Salman Akram
  • Patent number: 6320203
    Abstract: A method of forming a MOS device using doped and activated n-type and p-type polysilicon layers wherein a first doped and activated polysilicon layer (either n-type and p-type) is patterned on a substrate. An isolation material layer is formed abutting the first doped and activated polysilicon layer in the corners formed at the junction between the first doped and activated polysilicon layer and the substrate. A second doped and activated polysilicon layer (either n-type or p-type) is applied over the first doped and activated polysilicon layer and the isolation material layer. The second doped and activated polysilicon layer is planarized to the height of the first doped and activated polysilicon layer. The first and second doped and activated polysilicon layers are etched to substantially bifurcate the first and second doped and activated polysilicon layers. Further processing steps known in the art are utilized to complete the MOS device.
    Type: Grant
    Filed: February 12, 1999
    Date of Patent: November 20, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Salman Akram
  • Patent number: 6300661
    Abstract: An integrated circuit fabrication process is provided for forming, a mutual implant region within a well which is shared by a source region of a transistor residing within the well and a well-tie region coupled to the well, thereby providing a single electrical link to the well and the source region. Contacts may be coupled to the mutual implant region, and a conductor may be connected to the contacts. In the instance that the well is a p-type well in which NMOS transistors are formed, a ground voltage may be applied to the conductor to bias both the source region and the well. On the other hand, if the well is an n-type well in which PMOS transistors are formed, a power voltage, VCC, may be applied to the conductor to bias both the source region and the well. Absent the need to form contacts to both the source region and the well-tie region and conductors to such contacts, less space is required to bias the well and the source region.
    Type: Grant
    Filed: April 14, 1998
    Date of Patent: October 9, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Daniel Kadosh, Mark I. Gardner, Michael P. Duane
  • Patent number: 6281563
    Abstract: A CMOS semiconductor device is programmed by a laser beam which causes a PN junction in a silicon substrate to be permanently altered. This produces a leakage path between a program node and a tank region in the substrate; the program node can be an input to a transistor in a CMOS circuit, for example, so this node will always hold the transistor on or off depending whether or not it has been laser-programmed. Preferably, the tank region is of opposite type compared to the substrate, so the program node is electrically isolated from the substrate in either case.
    Type: Grant
    Filed: April 30, 1997
    Date of Patent: August 28, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Kendall Scott Wills, Paul A. Rodriguez
  • Patent number: 6252282
    Abstract: The invention relates to a semiconductor device including a preferably discrete bipolar transistor with a collector region, a base region, and an emitter region which are provided with connection conductors. A known means of preventing a saturation of the transistor is that the latter is provided with a Schottky clamping diode. The latter is formed in that case in that the connection conductor of the base region is also put into contact with the collector region. In a device according to the invention, the second connection conductor is exclusively connected to the base region, and a partial region of that portion of the base region which lies outside the emitter region, as seen in projection, lying below the second connection conductor is given a smaller flux of dopant atoms. The bipolar transistor in a device according to the invention is provided with a pn clamping diode which is formed between the partial region and the collector region.
    Type: Grant
    Filed: February 9, 1999
    Date of Patent: June 26, 2001
    Assignee: U.S. Philips Corporation
    Inventors: Godefridus A. M. Hurkx, Holger Schligtenhorst, Bernd Sievers
  • Patent number: 6222202
    Abstract: A light emitting device and photodetector combination having a structure where the layer of the photodetector that contacts the light emitting device has a semiconductor conductivity type polarity opposite that of the light emitting device. This configuration results in a light emitting device and photodetector structure that has a very low bias voltage requirement. Additionally, by shunting any current flowing through the junction formed where the light emitting device meets the photodetector, the bias voltage requirement is further reduced.
    Type: Grant
    Filed: October 6, 1998
    Date of Patent: April 24, 2001
    Assignee: Agilent Technologies, Inc.
    Inventors: Dubravko I. Babic, Scott W. Corzine
  • Patent number: 6175143
    Abstract: A diode is provided which includes a first-conductivity-type cathode layer, a first-conductivity-type drift layer placed on the cathode region and having a lower concentration than the cathode layer, a generally ring-like second-conductivity-type ring region formed in the drift layer, second-conductivity-type anode region formed in the drift layer located inside the ring region, a cathode electrode formed in contact with the cathode layer, and an anode electrode formed in contact with the anode region, wherein the lowest resistivity of the second-conductivity-type anode region is at least {fraction (1/100)} of the resistivity of the drift layer, and the thickness of the anode region is smaller than the diffusion depth of the ring region.
    Type: Grant
    Filed: June 2, 1998
    Date of Patent: January 16, 2001
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Tatsuhiko Fujihira, Yasushi Miyasaka
  • Patent number: 6133617
    Abstract: Disclosed is a high breakdown voltage semiconductor device comprising a semiconductor substrate, an active layer consisting of a high resistivity semiconductor layer of a first conductivity type formed on the substrate with an insulating layer interposed therebetween, a first impurity region of the first conductivity type formed within the active layer, a second impurity region of a second conductivity type formed within the active layer, a third impurity region of the second conductivity type formed within the second impurity region and having a high impurity concentration, a first electrode being in ohmic contact with the first impurity region and the fourth impurity region, and a second electrode being in Schottky contact with the second impurity region and in ohmic contact with the third impurity region.
    Type: Grant
    Filed: September 10, 1999
    Date of Patent: October 17, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keizo Hirayama, Hideyuki Funaki, Fumito Suzuki, Akio Nakagawa
  • Patent number: 5982015
    Abstract: Disclosed is a high breakdown voltage semiconductor device comprising a semiconductor substrate, an active layer consisting of a high resistivity semiconductor layer of a first conductivity type formed on the substrate with an insulating layer interposed therebetween, a first impurity region of the first conductivity type formed within the active layer, a second impurity region of a second conductivity type formed within the active layer, a third impurity region of the second conductivity type formed within the second impurity region and having a high impurity concentration, a first electrode being in ohmic contact with the first impurity region and the fourth impurity region, and a second electrode being in Schottky contact with the second impurity region and in ohmic contact with the third impurity region.
    Type: Grant
    Filed: February 17, 1999
    Date of Patent: November 9, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keizo Hirayama, Hideyuki Funaki, Fumito Suzuki, Akio Nakagawa
  • Patent number: 5814832
    Abstract: An electron emitting semiconductor device is provided with a P-type semiconductor layer arranged on a semiconductor substrate having an impurity concentration. A Schottky barrier electrode is arranged on a surface of the P-type semiconductor layer. Plural P.sup.+ -type area units are positioned under and facing the Schottky barrier electrode. An N.sup.+ -type area is disposed in the vicinity of the P.sup.+ -type units. The impurity concentration is such as to cause an avalanche breakdown in at least a portion of the surfaces.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: September 29, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventors: Toshihiko Takeda, Takeo Tsukamoto, Nobuo Watanabe, Masahiko Okunuki
  • Patent number: 5574307
    Abstract: A semiconductor apparatus has a silicon substrate sliced off from a silicon ingot produced by the pulling method or floating zone method, wherein the concentration of interstitial oxygen in a region with a depth of approximately 10 .mu.m or less from a device forming surface is minimum except for the device forming surface. According to the present invention, in the semiconductor apparatus production process, in the inner region with a depth of approximately 10 .mu.m from the device forming surface of the silicon substrate, the inner region affecting the device operation, oxygen does not precipitate. Moreover, in a more inner region, oxygen precipitates, thereby providing a gettering effect with respect to metal impurities.
    Type: Grant
    Filed: December 16, 1994
    Date of Patent: November 12, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mokuji Kageyama, Yoshiaki Matsushita
  • Patent number: 5523610
    Abstract: A photodiode array is provided which includes a cell comprised of at least a substrate, an insulating film formed on the substrate, a semiconductor layer containing an impurity of first conductivity type and provided on the insulating film, an impurity-diffusion layer of second conductivity type formed in the semiconductor layer and reaching the insulating film, and at least one impurity-diffusion layer of the first conductivity type formed within the impurity-diffusion layer of the second conductivity type and reaching the insulating film, wherein pn junctions are defined between the layers of opposite conductivity types and arranged laterally, and of the pn junctions, any pn junction of a predetermined order are connected to each other in series. By virtue of this arrangement, the area of pn junctions per unit area of a substrate is increased thereby contributing to a reduction in chip size and in production cost.
    Type: Grant
    Filed: July 7, 1994
    Date of Patent: June 4, 1996
    Assignee: Rohm Co., Ltd.
    Inventors: Koichi Kudo, Yasuo Aki
  • Patent number: 5502348
    Abstract: A ballistic charge transport device including an edge electron emitter defining an elongated central opening therethrough with a receiving terminal (e.g. an anode) at one end of the opening and a getter at the other end. A suitable potential is applied between the emitter and the receiving terminal to attract emitted electrons to the receiving terminal and a different suitable potential is applied between the emitter and the getter so that contaminants, such as ions and other undesirable particles, are accelerated toward and absorbed by the getter.
    Type: Grant
    Filed: December 20, 1993
    Date of Patent: March 26, 1996
    Assignee: Motorola, Inc.
    Inventors: Curtis D. Moyer, Lawrence N. Dworsky, Robert C. Kane
  • Patent number: 5488247
    Abstract: A MOS-type semiconductor clamping circuit includes a semiconductor substrate receiving a substrate potential, a well isolated electrically from the substrate potential, and MOS-type transistors formed in the well. Those transistors are connected with each other in series, each transistor has its gate connected to its drain, and a stable potential different from the substrate potential is applied to the well.
    Type: Grant
    Filed: July 20, 1994
    Date of Patent: January 30, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Mikio Sakurai
  • Patent number: 5436498
    Abstract: Reactor atoms (22) are introduced into a silicon substrate (10) by ion implantation to combine with metal impurities (18) to form stable chemical compounds (24). The stable compounds do not decompose and release the metal impurities during subsequent processing steps. Such metal impurities are detrimental to semiconductor devices formed in active regions (16, 17) in the silicon substrate. The reactor atoms such as sulfur are chosen to be substantially immobile in silicon at normal semiconductor processing temperatures. The metal impurities such as iron are effectively gettered to increase performance and reliability of semiconductor devices formed in the active regions (16, 17) in the silicon substrate.
    Type: Grant
    Filed: February 4, 1994
    Date of Patent: July 25, 1995
    Assignee: Motorola, Inc.
    Inventor: Israel A. Lesk
  • Patent number: 5341022
    Abstract: A semiconductor device having a reduced leakage current is fabricated in a short time at a low cost with excellent controllability. A buried layer (20) which includes a principal buried layer (21) of high ion concentration containing secondary defects (22) sandwiched between secondary buried layers (3a, 3b) of low ion concentration from upper and lower directions is formed on a semiconductor substrate (1). The secondary defects (22) have stable gettering effects for reducing defects caused during formation of a transistor (200) and contamination by heavy metals. Further, the secondary buried layers (3a, 3b) prevent depletion layers from reaching the secondary defects (22). The semiconductor device can be formed in a short time since no epitaxial growth is employed.
    Type: Grant
    Filed: March 16, 1993
    Date of Patent: August 23, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takashi Kuroi, Shigeru Kusunoki
  • Patent number: 5317186
    Abstract: A ring of polycrystalline material is developed around the edge of a wafer by general heating of the wafer and localized heating with a laser beam followed by rapid cooling. The ring of polycrystalline material helps prevent wafer breakage due to thermal shock. One or more additional ring, loop or closed figures of polycrystalline material can be formed inside of said ring of polycrystalline material developed around the edge of the wafer to further reinforce the wafer.
    Type: Grant
    Filed: June 15, 1992
    Date of Patent: May 31, 1994
    Assignee: Texas Instruments Incorporated
    Inventors: Kendall S. Wills, Paul A. Rodriguez, Melvin L. Brewer
  • Patent number: 5243213
    Abstract: The present invention is directed to a MIS semiconductor device having a semiconductor layer formed on an insulating substrate and a gate electrode formed on this semiconductor layer through a gate insulating film, which is provided with a semiconductor region of a second conductivity type or a metal layer formed adjacent to a source region of a first conductivity type but separated from a channel region, thereby suppressing degradation of breakdown voltage caused by impact ionization, which is a defect of the MIS semiconductor device formed on an SOI substrate, to improve the reliability of this kind of MIS semiconductor devices.
    Type: Grant
    Filed: July 8, 1991
    Date of Patent: September 7, 1993
    Assignee: Sony Corporation
    Inventors: Yoshihiro Miyazawa, Eric Minami, Takeshi Matsushita
  • Patent number: 5185275
    Abstract: A process for improving the high voltage performances of a MOSFET transistor, and suppressing parasitic current induced snap-back behavior by placing a heavily doped P+ region around the grounded source. A first P+ region is placed adjacently to and in contact with the source and its metal lead, and a second P+ region may be placed under and in contact with the source and first P+ region, or form a layer under the entire transistor connected to the source by a P+ plug. Additional grounding of the source may be accomplished by a succession of alternating P+ region and N+ regions along the source edge.
    Type: Grant
    Filed: March 30, 1992
    Date of Patent: February 9, 1993
    Assignee: Micron Technology, Inc.
    Inventor: Kirk Prall
  • Patent number: 5166760
    Abstract: A semiconductor device is provided wherein a first diode having a pn junction and a second diode having a combination of a Schottky barrier and a pn junction in a current-passing direction are provided side by side in a direction perpendicular to the current-passing direction. When a forward current with a current density J.sub.F is passed into the second diode, the relation ##EQU1## is established in a forward voltage V.sub.F range of 0.1 (V) to 0.3 (V), where k represents the Boltzmann constant (.apprxeq.1.38.times.10.sup.-23 J/K), T represents the absolute temperature, and q represents the quantity of electron charges (.apprxeq.1.6.times.10.sup.-19 C).
    Type: Grant
    Filed: February 11, 1992
    Date of Patent: November 24, 1992
    Assignees: Hitachi, Ltd., Hitachi Haramachi Semiconductor Ltd.
    Inventors: Mutsuhiro Mori, Yasumiti Yasuda, Naoki Sakurai, Hidetoshi Arakawa, Hiroshi Owada
  • Patent number: 5162876
    Abstract: A p-type emitter layer 2 is formed in one surface portion of an n.sup.- -type base layer 1 of high resistance. p.sup.+ -type contact layers 2b and n.sup.+ -type current blocking layers 6 are formed in a preset area ratio in the surface area of the p-type emitter layer. A cathode electrode 4 is formed in contact with the contact layer 2b as well as the current blocking layer 6 of the pn junction diode section. With this cathode structure, the electron injection in the ON state can be suppressed so as to reduce the carrier concentration of a portion of the n.sup.- -type base layer 1 lying on the cathode side, and the parasitic transistor effect caused at the time of reverse recovery can be suppressed by provision of the current blocking layer 6.
    Type: Grant
    Filed: September 27, 1991
    Date of Patent: November 10, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuhiko Kitagawa, Akio Nakagawa