All Devices Being Of Same Type, E.g., Assemblies Of Rectifier Diodes (epo) Patents (Class 257/E25.002)
  • Patent number: 9245772
    Abstract: A semiconductor package comprises a substrate, a first semiconductor die mounted to the substrate, and a first double side mold (DSM) internal stackable module (ISM) bonded directly to the first semiconductor die through a first adhesive. The first DSM ISM includes a first molding compound, and a second semiconductor die disposed in the first molding compound. The semiconductor package further comprises a first electrical connection coupled between the first semiconductor die and the substrate, and a second electrical connection coupled between the first DSM ISM and the substrate.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: January 26, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: JoungIn Yang, ChoongBin Yim, KeonTeak Kang, YoungChul Kim
  • Patent number: 8866123
    Abstract: A vertical chain memory includes two-layer select transistors having first select transistors which are vertical transistors arranged in a matrix, and second select transistors which are vertical transistors formed on the respective first select transistors, and a plurality of memory cells connected in series on the two-layer select transistors. With this configuration, the adjacent select transistors are prevented from being selected by respective shared gates, the plurality of two-layer select transistors can be selected, independently, and a storage capacity of a non-volatile storage device is prevented from being reduced.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: October 21, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Yoshitaka Sasago, Masaharu Kinoshita, Takahiro Morikawa, Akio Shima, Takashi Kobayashi
  • Patent number: 8723218
    Abstract: Silicon carbide PiN diodes are presented with reduced temperature coefficient crossover points by limited p type contact area to limit hole injection in the n type drift layer in order to provide a lower current at which the diode shifts from negative temperature coefficient to a positive temperature coefficient of forward voltage for mitigating thermal runaway.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: May 13, 2014
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Karl D. Hobart, Francis J. Kub, Mario Ancona, Eugene A. Imhoff
  • Patent number: 8502237
    Abstract: A semiconductor rectifying device of an embodiment includes a first-conductive-type semiconductor substrate made of a wide bandgap semiconductor, a first-conductive-type semiconductor layer formed on an upper surface of the semiconductor substrate and made of the wide bandgap semiconductor having an impurity concentration lower than that of the semiconductor substrate, a first-conductive-type first semiconductor region formed at a surface of the semiconductor layer and made of the wide bandgap semiconductor, a second-conductive-type second semiconductor region formed around the first semiconductor region and made of the wide bandgap semiconductor, a second-conductive-type third semiconductor region formed around the first semiconductor region and made of the wide bandgap semiconductor having a junction depth deeper than a junction depth of the second semiconductor region, a first electrode that is formed on the first, second, and third semiconductor regions, and a second electrode formed on a lower surface of
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: August 6, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masamu Kamaga, Makoto Mizukami
  • Publication number: 20130082382
    Abstract: First and second sub-bumps are provided on both surfaces of each substrate along with a usual bump structure (first and second main bumps), and at least one of the first and second sub-bumps is made greater in height than the first and second main bumps, so that the sub-bumps come into contact with one another earlier than the main bumps at the time of joining semiconductor chips, thereby securing margins of joint among the main bumps and suppressing the thin-filming of a layer, such as a solder layer, to be fluidized by heating.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 4, 2013
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Elpida Memory, Inc.
  • Patent number: 8329495
    Abstract: A method of forming a PV module includes forming conductors on a top surface of a PV coated substrate; forming insulators on the top surface of the PV coated substrate; and cutting the PV coated substrate to form a plurality of individual PV cells. The PV coated substrate is cut so that each of the PV cells has some of the conductors and an insulator on its top surface. Multiple PV cells are then joined to form a PV module by attaching an edge of a first one of the PV cells under an edge of a second one of the PV cells so that at least a portion of the conductors on the first PV cell electrically contacts a bottom surface of the second PV cell.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: December 11, 2012
    Assignee: Preco, Inc.
    Inventor: Chris Walker
  • Patent number: 8304856
    Abstract: A serially-connected diode pair made of diodes having a high withstand voltage and a low on-resistance is formed based on a high withstand voltage vertical PNP bipolar transistor process technology. Two of the diode pairs are connected in parallel to form a bridge so that there is formed a high-efficiency full-wave rectifier circuit that is free from a leakage current due to a parasitic transistor. The serially-connected diode pair is formed by connecting a diode composed of a P type semiconductor substrate, that makes an anode, and an N type buried layer, that makes a cathode, and a diode composed of a P+ type conductive layer, that makes an anode, and an N type epitaxial layer, that makes a cathode, in series with an electrode AC1.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: November 6, 2012
    Assignees: Sanyo Semiconductor Co., Ltd., Sanyo Semiconductor Manufacturing Co., Ltd., Semiconductor Components Industries, LLC
    Inventors: Keiji Mita, Yasuhiro Tamada, Masao Takahashi, Takao Maruyama
  • Publication number: 20120241982
    Abstract: Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites.
    Type: Application
    Filed: April 6, 2012
    Publication date: September 27, 2012
    Applicant: Micron Technology, Inc.
    Inventors: Boon Suan Jeung, Eng Meow Koon, Chia Yong Poo
  • Publication number: 20120112360
    Abstract: A semiconductor chip includes a semiconductor chip body including a peripheral region, a first region and a second region, and having a plurality of memory banks formed in each of the first region and the second region; a plurality of first through electrodes formed in the peripheral region; and a plurality of second through electrodes formed in the first and second regions along a direction parallel to a minor axis of the semiconductor chip body.
    Type: Application
    Filed: September 23, 2011
    Publication date: May 10, 2012
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Ho Young SON
  • Publication number: 20120074378
    Abstract: A memory element is provided that includes a first electrode, a second electrode, and an active region disposed between the first electrode and the second electrode, wherein at least a portion of the active region comprises an elastically deformable material, and wherein deformation of the elastically deformable material causes said memory element to change from a lower conductive state to a higher conductive state. A multilayer structure also is provided that includes a base and a multilayer circuit disposed above the base, where the multilayer circuit includes at least of the memory elements including the elastically deformable material.
    Type: Application
    Filed: September 23, 2010
    Publication date: March 29, 2012
    Inventors: Wei Wu, Jianhua Yang, Zhiyong Li, Shih-Yuan Wang, Dmitri Strukov, Alexandre Bratkovski
  • Publication number: 20120013027
    Abstract: A method including forming an intermediate product, the intermediate product being configured to include a wiring substrate including a plurality of first electrodes, a plurality of second electrodes and a plurality of test electrodes, a first semiconductor chip mounted over the wiring substrate and including a plurality of first pads electrically connected respectively to the first electrodes, and a second semiconductor chip stacked over the first semiconductor chip and including a plurality of second pads electrically connected respectively to the second electrodes; encapsulating the first and second semiconductor chips; and performing electrical tests on the first and second semiconductor chips by use of the test electrodes, after the encapsulating of the first and second semiconductor chips.
    Type: Application
    Filed: September 23, 2011
    Publication date: January 19, 2012
    Inventors: Masachika MASUDA, Toshihiko Usami
  • Publication number: 20110298011
    Abstract: Example embodiments relate to a semiconductor memory device and a system in which a plurality of semiconductor layers are stacked on each other. A 3-dimensional (3D) semiconductor memory device may include a plurality of semiconductor layers that are stacked on each other. The plurality of semiconductor layers may have the same memory cell structure. The 3D semiconductor memory device may include a first memory region including at least one semiconductor layer for storing system data and a second memory region including at least one semiconductor layer for storing data aside from the system data. The system data may include at least one piece of data selected from the group consisting of a booting code, a system code, and application software.
    Type: Application
    Filed: June 2, 2011
    Publication date: December 8, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-bo Lee, Kye-hyun Kyung
  • Patent number: 8039873
    Abstract: A semiconductor device includes a substrate including an element region having a polygonal shape defined by a plurality of edges, and an isolation region surrounding the element region, and a plurality of gate electrodes provided on the substrate, crossing the element region, arranged in parallel with each other, and electrically connected with each other, wherein at least one of the edges does not cross any of the gate electrodes, and is not parallel to the gate electrodes.
    Type: Grant
    Filed: November 24, 2008
    Date of Patent: October 18, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhide Abe, Tadahiro Sasaki, Kazuhiko Itaya
  • Publication number: 20110147694
    Abstract: A resistive memory device includes a plurality of resistive units, each resistive unit including: a lower electrode formed over a substrate; a resistive layer formed over the lower electrode; and an upper electrode formed over the resistive layer, wherein edge parts of the lower and upper electrodes, which come in contact with the resistive layer, is formed with a rounding shape.
    Type: Application
    Filed: December 17, 2010
    Publication date: June 23, 2011
    Inventors: Seok-Pyo SONG, Yu-Jin Lee
  • Patent number: 7947522
    Abstract: A method of production of a semiconductor device includes: forming a pattern having open element isolation regions on a first insulating film situated on a semiconductor substrate; forming trenches at the element isolation regions on the semiconductor substrate; forming a second insulating film on the first insulating film and inside the trenches; forming holes in the second insulating film in active regions sectioned by the element isolation regions; and leaving the second insulating film inside the trenches only. An interval between an outer perimeter of each the active regions and an outer perimeter of each of the holes in each of the active regions is set such that the interval in the first circuit region, in which a total area of the active regions is relatively large, is smaller than the interval in the second circuit region, in which the total area of the active regions is relatively small.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: May 24, 2011
    Assignee: Panasonic Corporation
    Inventor: Emi Ohtsuka
  • Publication number: 20100171212
    Abstract: A semiconductor package structure includes a carrier, a chip or multi-chips mounted on a top surface of the carrier, a molding compound encapsulating the top surface and the chips, a plurality of solder balls distributed on a bottom surface of the carrier, and a protection bar formed of thermosetting plastic material formed on the bottom surface.
    Type: Application
    Filed: February 3, 2009
    Publication date: July 8, 2010
    Inventor: Jen-Chung Chen
  • Publication number: 20100155855
    Abstract: Band edge engineered Vt offset devices, design structures for band edge engineered Vt offset devices and methods of fabricating such structures is provided herein. The structure includes a first FET having a channel of a first compound semiconductor of first atomic proportions resulting in a first band structure and a first type. The structure further includes a second FET having a channel of a second compound semiconductor of second atomic proportions resulting in a second band structure and a first type. The first compound semiconductor is different from the second compound semiconductor such that the first FET has a first band structure different from second band structure, giving rise to a threshold voltage different from that of the second FET.
    Type: Application
    Filed: December 23, 2008
    Publication date: June 24, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. ANDERSON, Edward J. NOWAK
  • Patent number: 7679122
    Abstract: A semiconductor device includes a plurality of source regions and drain regions disposed on a semiconductor substrate. The semiconductor device also includes a plurality of word lines disposed on the semiconductor substrate between the source regions and the drain regions. The semiconductor device also includes a conductive line disposed on the semiconductor substrate parallel to the word lines. The semiconductor device also includes a plurality of bit lines connected to the drain regions and crossing over the word lines. The semiconductor device also includes a plurality of source strapping lines crossing over the plurality of word lines, the plurality of source strapping lines being connected to at least one of the plurality of source regions and the conductive line. The semiconductor device also includes a ground line connected to the conductive line.
    Type: Grant
    Filed: September 14, 2006
    Date of Patent: March 16, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Wook-Hyoung Lee
  • Publication number: 20090311816
    Abstract: Disclosed is an AC light emitting device having photonic crystal structures and a method of fabricating the same. The light emitting device includes a plurality of light emitting cells and metallic wirings electrically connecting the light emitting cells with one another. Further, each of the light emitting cells includes a first conductive type semiconductor layer, a second conductive type semiconductor layer disposed on one region of the first conductive type semiconductor layer, and an active layer interposed between the first and second conductive type semiconductor layers. In addition, a photonic crystal structure is formed in the second conductive type semiconductor layer. The photonic crystal structure prevents light emitted from the active layer from laterally propagating by means of a periodic array, such that light extraction efficiency of the light emitting device can be improved.
    Type: Application
    Filed: August 24, 2009
    Publication date: December 17, 2009
    Applicant: SEOUL OPTO DEVICE CO., LTD.
    Inventors: Jae Ho LEE, Yeo Jin YOON, Eu Jin HWANG, Jong Kyu KIM, Jun Hee LEE
  • Patent number: 7573069
    Abstract: A semiconductor device having high operating performance and reliability, and a manufacturing method thereof are provided. An LDD region 207 provided in an n-channel TFT 302 forming a driving circuit enhances the tolerance for hot carrier injection. LDD regions 217-220 provided in an n-channel TFT (pixel TFT) 304 forming a pixel portion greatly contribute to the decrease in the OFF current value. Here, the LDD region of the n-channel TFF of the driving circuit is formed such that the concentration of the n-type impurity element becomes higher as the distance from an adjoining drain region decreases.
    Type: Grant
    Filed: January 12, 2006
    Date of Patent: August 11, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Publication number: 20090134466
    Abstract: A method of manufacturing dual work function devices starting from a single metal electrode and the device resulting therefrom are disclosed. In one aspect, the method includes a single-metal-single-dielectric (SMSD) CMOS integration scheme. A single dielectric stack comprising a gate dielectric layer and a dielectric capping layer and one metal layer overlying the dielectric stack are first deposited, forming a metal-dielectric interface. Upon forming the dielectric stack and the metal layer, at least part of the dielectric capping layer is selectively modified by adding work function tuning elements, the part being adjacent to the metal-dielectric interface.
    Type: Application
    Filed: October 24, 2008
    Publication date: May 28, 2009
    Applicants: Interuniversitair Mcroelektronica Centrum vzw(IMEC), Taiwan Semiconductor Manufacturing Company, Ltd., Samsung Electonics Co. Ltd.
    Inventors: Hag-Ju Cho, Shih-Hsun Chang
  • Publication number: 20090124036
    Abstract: A method of production of a semiconductor device includes: forming a pattern having open element isolation regions on a first insulating film situated on a semiconductor substrate; forming trenches at the element isolation regions on the semiconductor substrate; forming a second insulating film on the first insulating film and inside the trenches; forming holes in the second insulating film in active regions sectioned by the element isolation regions; and leaving the second insulating film inside the trenches only. An interval between an outer perimeter of each the active regions and an outer perimeter of each of the holes in each of the active regions is set such that the interval in the first circuit region, in which a total area of the active regions is relatively large, is smaller than the interval in the second circuit region, in which the total area of the active regions is relatively small.
    Type: Application
    Filed: October 1, 2008
    Publication date: May 14, 2009
    Inventor: Emi OHTSUKA
  • Publication number: 20080258129
    Abstract: A phase-change memory device has a plurality of first wiring lines WL extending in parallel to each other, a plurality of second wiring lines BL which are disposed to cross the first wiring lines WL while being separated or isolated therefrom, and memory cells MC which are disposed at respective cross points of the first wiring lines WL and the second wiring lines BL and each of which has one end connected to a first wiring line WL and the other end connected to a second wiring line BL. The memory cell MC has a variable resistive element VR which stores as information a resistance value determined due to phase change between crystalline and amorphous states thereof, and a Schottky diode SD which is connected in series to the variable resistive element VR.
    Type: Application
    Filed: January 10, 2003
    Publication date: October 23, 2008
    Inventor: Haruki Toda
  • Patent number: 7326965
    Abstract: A surface-emitting type device includes a substrate including a first face, a second face that is tilted with respect to the first face and has a plane index different from a plane index of the first face, and a third face that is tilted with respect to the second face and has a plane index equal to the plane index of the first face, an emission section formed above the first face, and a rectification section formed above each of the second face and the third face, wherein the emission section includes a first semiconductor layer of a first conductivity type, an active layer formed above the first semiconductor layer, and a second semiconductor layer of a second conductivity type formed above the active layer, the rectification section includes a first semiconductor layer of the second conductivity type formed above the second face, and a second semiconductor layer of the first conductivity type formed continuously with the first semiconductor layer above the third face, at least a portion of the first semico
    Type: Grant
    Filed: February 1, 2006
    Date of Patent: February 5, 2008
    Assignee: Seiko Epson Corporation
    Inventors: Hajime Onishi, Tetsuo Nishida
  • Patent number: 7291926
    Abstract: The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate. The bottom surface of the sub-package is attached to the first chip. The sub-package comprises a second substrate, a second chip and a second molding compound. The second substrate has a top surface and a bottom surface, and is electrically connected to the first chip. The second chip is attached to the top surface of the second substrate to which the second chip is electrically connected. The second molding compound encapsulates the second chip and part of the top surface of the second substrate. Whereby, the relative large area caused by the parallel arrangement of a plurality of conventional package structures can be reduced, and there is no need to redesign signal-transmitting path.
    Type: Grant
    Filed: February 14, 2006
    Date of Patent: November 6, 2007
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Su Tao, Yu-Fang Tsai
  • Patent number: 7129583
    Abstract: The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate. The bottom surface of the sub-package is attached to the first chip. The sub-package comprises a second substrate, a second chip and a second molding compound. The second substrate has a top surface and a bottom surface, and is electrically connected to the first chip. The second chip is attached to the top surface of the second substrate to which the second chip is electrically connected. The second molding compound encapsulates the second chip and part of the top surface of the second substrate. Whereby, the relative large area caused by the parallel arrangement of a plurality of conventional package structures can be reduced, and there is no need to redesign signal-transmitting path.
    Type: Grant
    Filed: December 31, 2004
    Date of Patent: October 31, 2006
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Su Tao, Yu-Fang Tsai
  • Publication number: 20040262786
    Abstract: Hermetically sealed high-voltage assemblies are made up of series-connected diodes. Exposed tabs bonding adjacent diodes allow for greater thermal dissipation than previous products. This allows higher current-carrying capacity especially if used in oil.
    Type: Application
    Filed: May 1, 2004
    Publication date: December 30, 2004
    Applicant: SEMTECH CORPORATION
    Inventors: David Francis Courtney, Gary Bridges, Albin Gary Stanulis, Todd Allan Albright