With Pn Junction Gate (e.g., Field-controlled Thyristor (fcth), Static Induction Thyristor (sith)) (epo) Patents (Class 257/E29.196)

Patent number: 8866125
Abstract: Various embodiments provide materials and methods for integrating exemplary heterostructure field-effect transistor (HFET) driver circuit or thyristor driver circuit with LED structures to reduce or eliminate resistance and/or inductance associated with their conventional connections.
Type: Grant
Filed: May 1, 2013
Issued: October 21, 2014
Assignee: STC.UNM
Inventor: Stephen D. Hersee
Patent number: 8569117
Abstract: An integrated trench-MOS-controlled-thyristor plus trench gated diode combination, in which the trenches are preferably formed at the same time. A backside polarity reversal process permits a backside p+ region in the thyristor areas, and only a backside n+ region in the diode areas (for an n-type device). This is particularly advantageous in motor control circuits and the like, where the antiparallel diode permits the thyristor to be dropped into existing power MOSFET circuit designs. In power conversion circuits, the antiparallel diode can conveniently serve as a freewheeling diode.
Type: Grant
Filed: October 10, 2012
Issued: October 29, 2013
Assignee: Pakal Technologies LLC
Inventors: Hidenori Akiyama, Richard A. Blanchard, Woytek Tworzydlo
Application number: 20130082768
Abstract: Disclosed is a diode. An embodiment of the diode includes a semiconductor body, a first emitter region of a first conductivity type, a second emitter region of a second conductivity type, and a base region arranged between the first and second emitter regions and having a lower doping concentration than the first and second emitter regions. The diode further includes a first emitter electrode only electrically coupled to the first emitter region, a second emitter electrode in electrical contact with the second emitter region, and a control electrode arrangement including a first control electrode section, and a first dielectric layer arranged between the first control electrode section and the semiconductor body. At least one pn junction extends to the first dielectric layer or is arranged distant to the first dielectric layer by less than 250 nm.
Type: Application
Filed: September 30, 2011
Issued: April 4, 2013
Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
Inventors: Franz Hirler, Joachim Weyers
Patent number: 8242537
Abstract: An IGBT with a fast reverse recovery time rectifier includes an N-type drift epitaxial layer, a gate, a gate insulating layer, a P-type doped base region, an N-type doped source region, a P-type doped contact region, and a P-type lightly doped region. The P-type doped base region is disposed in the N-type drift epitaxial layer, and the P-type doped contact region is disposed in the N-type drift epitaxial layer. The P-type lightly doped region is disposed between the P-type contact doped region and the N-type drift epitaxial layer, and is in contact with the N-type drift epitaxial layer.
Type: Grant
Filed: November 10, 2009
Issued: August 14, 2012
Assignee: Anpec Electronics Corporation
Inventors: Wei-Chieh Lin, Jen-Hao Yeh, Ho-Tai Chen
Application number: 20110220959
Abstract: A high-frequency metal-insulator-metal (MIM) type diode is constructed as a bridge suspended above a substrate to significantly reduce parasitic capacitances affecting the operation frequency of the diode thereby permitting improved high-frequency rectification, demodulation, or the like.
Type: Application
Filed: March 11, 2010
Issued: September 15, 2011
Inventors: Robert H. Blick, Chulki Kim, Jonghoo Park
Patent number: 7902051
Abstract: The present invention, in one embodiment, provides a method of producing a PN junction the method including providing a single crystal substrate; forming an insulating layer on the single crystal substrate; forming a via through the insulating layer to provide an exposed portion of the single crystal substrate; forming amorphous Si on at least the exposed portion of the single crystal substrate; converting at least a portion of the amorphous Si into single crystal Si; and forming dopant regions in the single crystal Si. In one embodiment the diode of the present invention is integrated with a memory device.
Type: Grant
Filed: January 7, 2008
Issued: March 8, 2011
Assignees: International Business Machines Corporation, Qimonda AG, Macronix International Co., Ltd.
Inventors: Bipin Rajendran, Thomas Happ, Hsiang-Lan Lung
Application number: 20100193837
Abstract: Provided is a semiconductor device in which on-resistance is largely reduced based on a new principle of operation. In the semiconductor device (1), if an embedded electrode (5) is at negative potential, a depletion layer (11) is formed from a trench (3a) to a neighboring trench so that a channel (10) is turned off. If the embedded electrode is at a positive potential, the depletion layer is not formed in every region between the neighboring trenches so that the channel is turned on.
Type: Application
Filed: June 17, 2008
Issued: August 5, 2010
Assignee: Rohm Co., Ltd.
Inventor: Masaru Takaishi
Patent number: 7595516
Abstract: An optoelectronic circuit includes a resonant cavity formed on a substrate and into which is injected an input digital optical signal that encodes bits of information (each bit representing an OFF logic level or an ON logic level). A heterojunction thyristor device, formed in the resonant cavity, produces an output digital electrical signal corresponding to the input digital optical signal. A sampling clock defines sampling periods that overlap the bits (e.g., ON/OFF pulse durations) in the input digital optical signal. The sampling clock can be in the form of electrical pulses supplied to the n-channel injector terminal(s) and/or p-channel injector terminals of the heterojunction thyristor device. Alternatively, the sampling clock can be in the form of optical pulses that are part of the Optical IN signal that is resonantly absorbed by the device. The heterojunction thyristor device operates in an OFF state and an ON state.
Type: Grant
Filed: February 19, 2008
Issued: September 29, 2009
Assignees: The University of Connecticut, Opel, Inc.
Inventors: Geoff W. Taylor, Jianhong Cai
Patent number: 7547586
Abstract: A method of making a semiconductor structure for use in a static induction transistor. Three layers of a SiC material are on a substrate with the top layer covered with a thick oxide. A mask having a plurality of strips is deposited on the top of the oxide to protect the area underneath it, and an etch removes the oxide, the third layer and a small amount of the second layer, leaving a plurality of pillars. An oxidation step grows an oxide skirt around the base of each pillar and consumes the edge portions of the third layer under the oxide to form a source. An ion implantation forms gate regions between the skirts. At the same time, a plurality of guard rings is formed. Removal of all oxide results in a semiconductor structure to which source, gate and drain connections may be made to form a static induction transistor. A greater separation between a source and gate is obtained by placing a spacer layer on the sidewalls of the pillars, either before or after formation of the skirt.
Type: Grant
Filed: June 2, 2006
Issued: June 16, 2009
Assignee: Northrop Grumman Corp
Inventor: Li-Shu Chen
Patent number: 7535039
Abstract: A dual gate power switch comprised of a vertical arrangement of a normally off SIT (static induction transistor) in series with a normally on SIT in a monolithic semiconductor structure. The structure includes a first pillar having at the base thereof laterally extending shoulder portions having sections of a first gate for controlling the normally off SIT. The structure includes a second pillar, of a width greater than the first pillar and which also has laterally extending shoulder portions having sections of a second gate for controlling the normally on SIT. Contacts are provided for SIT operation.
Type: Grant
Filed: June 16, 2006
Issued: May 19, 2009
Assignee: Northrop Grumman Corp
Inventors: Eric J. Stewart, Stephen Van Campen, Rowland C. Clarke
Patent number: 7504286
Abstract: A method is provided for fabricating a memory device. A semiconductor substrate is provided which includes a first well region having a first conductivity type, a second well region having the first conductivity type, a first gate structure overlying the first well region and the second gate structure overlying the second well region. An insulating material layer is conformally deposited overlying exposed portions of the semiconductor substrate. Photosensitive material is provided over a portion of the insulating material layer which overlies a portion of the second well region. The photosensitive material exposes portions of the insulating material layer. The exposed portions of the insulating material layer are anisotropically etched to provide a sidewall spacer adjacent a first sidewall of the second gate structure, and an insulating spacer block formed overlying a portion of the second gate structure and adjacent a second sidewall of the second gate structure.
Type: Grant
Filed: March 28, 2007
Issued: March 17, 2009
Assignee: Advanced Micro Devices, Inc.
Inventor: Hyun-Jin Cho
Patent number: 7405435
Abstract: A semiconductor device includes a thyristor, trigger circuit and surge detection/leakage reduction circuit. The anode of the thyristor is connected to a first terminal and the cathode thereof is connected to a second terminal. The trigger circuit is configured to fire the thyristor when surge voltage is applied to the first terminal. The surge detection/leakage reduction circuit is provided between the gate of the thyristor and the second terminal and configured to interrupt current flowing from the trigger circuit to the second terminal in the normal operation mode and set trigger voltage which is used to fire the thyristor in cooperation with the trigger circuit at the surge voltage application time.
Type: Grant
Filed: October 4, 2004
Issued: July 29, 2008
Assignee: Kabushiki Kaisha Toshiba
Inventor: Koichi Sato