Abstract: Methods, systems, and apparatus for producing CCZ states and T states. In one aspect, a method for distilling a CCZ state includes preparing multiple target qubits, ancilla qubits and stabilizer qubits in a zero state, performing an X gate for each stabilizer qubit on multiple ancilla qubits or multiple ancilla qubits and one of the target qubits using the stabilizer qubit as a control, measuring the stabilizer qubits, performing, on each of the ancilla qubits, a Z1/4 gate and a Hadamard gate, measuring each of the ancilla qubits, performing, conditioned on each measured ancilla qubit state, a NOT operation on a selected stabilizer qubit, or a NOT operation on the selected stabilizer qubit and a Z gate on one or more respective target qubits, performing, on each target qubit and conditioned on a measured state of a respective stabilizer qubit, a Z gate on the target qubit, and performing an X gate on each of the target qubits.

Abstract: A semiconductor device includes a MOSFET including a PN junction diode. A unipolar device is connected in parallel to the MOSFET and has two terminals. A first wire connects the PN junction diode to one of the two terminals of the unipolar device. A second wire connects the one of the two terminals of the unipolar device to an output line, so that the output line is connected to the MOSFET and the unipolar device via the first wire and the second wire. In one embodiment the connection of the first wire to the diode is with its anode, and in another the connection is with the cathode.

Abstract: A method of multiplexing control lines of a qubit array includes applying a qubit control signal to a single driveline. The qubit control signal is split on the single driveline between a first resonator and a second resonator. The first driveline is operative to control a first qubit, a second tunable qubit, a third qubit, and a fourth tunable qubit. The first qubit is coupled to the second tunable qubit by the first resonator. The third qubit is coupled to the fourth tunable qubit by the second resonator. A variation in amplitude of the qubit control signal is compensated by adjusting a frequency of the second tunable qubit and a frequency of the fourth tunable qubit.

Abstract: Provided are a quantum pulse determining method, apparatus, device and readable storage medium, where basic pulses corresponding to basic logic gates are set in advance, the method including: when manipulating a qubit according to a quantum logic gate, splitting the quantum logic gate to obtain sub-logic gates; and searching for sub-pulses corresponding to the sub-logic gates among the basic pulses, and manipulating the qubit according to the sub-pulse. Basic pulses are set in advance in the method, apparatus, device and readable storage medium provided by the embodiments. When a qubit is to be manipulated, the quantum logic gate can be split into multiple sub-logic gates, and then sub-pulses corresponding to the sub-logic gates are searched for among the basic pulses. Thus, sub-pulses read can be used directly to manipulate the qubit, avoiding the computing power consumed in generating pulses according to the quantum logic gate, thereby improving an operation speed.

Abstract: One example includes a memory cell system that includes a quantizing loop that conducts a quantizing current in a first direction corresponding to a first stored memory state and to conduct the quantizing current in a second direction corresponding to a second stored memory state. The system also includes a bias element configured to provide a substantially constant flux bias of the quantizing loop in each of the first and second states of the stored memory state. The stored memory state can be read from the memory cell system in response to the substantially constant flux bias and a read current that is provided to the memory cell system. The system further includes a tunable energy element that is responsive to a write current that is provided to the memory cell system to change the state of the stored memory state between the first state and the second state.

Abstract: Superconducting device applications implemented with two surface acoustic wave resonators coupled to a Josephson ring modulator are provided. A method can include receiving, by a unitary Josephson mixer and from a first superconducting surface acoustic wave resonator of a superconducting device, a first surface acoustic wave signal that comprises one or more phonons that resonate at a first frequency, and receiving, by the unitary Josephson mixer and from a radio frequency source operatively coupled to the unitary Josephson mixer, a radio frequency control signal. The method can also include mixing the first surface acoustic wave signal and the radio frequency control signal and outputting a second surface acoustic wave signal based on mixing the first surface acoustic wave signal and the radio frequency control signal. The second surface acoustic wave signal can comprise one or more phonons that resonate at a second frequency.

Abstract: Methods are provided for exact synthesis of unitaries for qudit and multi-qubit systems. In addition, state preparation methods are provided. The syntheses produce circuits that have lowest cost for a given cost function.

Abstract: Repeat-Until-Success (RUS) circuits are compiled in a Clifford+T basis by selecting a suitable cyclotomic integer approximation of a target rotation so that the rotation is approximated within a predetermined precision. The cyclotomic integer approximation is randomly modified until a modified value can be expanded into a single-qubit unitary matrix by solving one or more norm equations. The matrix is then expanded into a two-qubit unitary matrix of special form, which is then decomposed into an optimal two-qubit Clifford+T circuit. A two-qubit RUS circuit using a primary qubit and an ancillary qubit is then obtained based on the latter decomposition. An alternate embodiment is disclosed that keeps the total T-depth of the derived circuit small using at most 3 additional ancilla qubits. Arbitrary unitary matrices defined over the cyclotomic field of 8th roots of unity are implemented with RUS circuits.

Abstract: In an integrated-circuit component having a signal transmitter receives a transmitter power supply that cycles periodically between power-off and power-on voltage levels to define a sequence of enable intervals during which the signal transmitter is to output voltage levels corresponding to respective transmit data bits onto an external signaling link. The signal transmitter generates, at the start of each output-enable interval, an initial nonzero voltage having a first polarity across conductors of the external signaling link, and then conditionally transitions the initial nonzero voltage to a second nonzero voltage according to whether the transmit data bit corresponding to the output-enable interval has a predetermined one of two binary states, the second nonzero voltage having a polarity opposite the first polarity.

Abstract: One example includes a current driver system. The system includes a current source configured to provide a source current to a transition node. The system also includes a Josephson latch comprising at least one Josephson junction stage. The at least one Josephson junction stage can be configured to conduct the source current from the transition node as a current-clamped bias current in a deactivated state of the Josephson latch. The Josephson latch can be configured to activate in response to the bias current and a trigger pulse to switch the at least one Josephson junction stage to a voltage state to conduct at least a portion of the source current from the transition node as an output current to a load in response to activation of the Josephson latch.

Abstract: An reciprocal quantum logic (RQL) gate circuit has a first stage having four logical inputs asserted based on receiving positive single flux quantum (SFQ) pulses and storing the SFQ pulses in respective storage loops each associated with a logical input, and a second stage having two more storage loops. First and second logical decision Josephson junctions (JJs) make determinations based on signals stored in the first-stage storage loops. A third logical decision JJ makes a third determination based on the first and second determinations. Each logical decision JJ triggers based on biasing provided by one or more currents stored in its associated storage loops and a bias signal having an AC component. The second stage asserts an output based on the triggering of the third logical decision JJ. Four-input AND, OR, AO22, and OA22 gates are thereby provided.

Abstract: A Josephson parametric converter is provided. The Josephson parametric converter includes a multi-Josephson junction ring modulator having arrays of N Josephson junctions arranged in a ring configuration with ring nodes inter-dispersed between the arrays. The multi-Josephson junction ring modulator further has a center node inter-connecting the ring nodes. N is an integer having a value greater than one. The Josephson parametric also includes a first and a second resonator formed from lumped-element capacitors that shunt the multi-Josephson junction ring modulator and respectively enable a first and a second mode of the Josephson parametric converter.

Abstract: A Josephson parametric converter is provided. The Josephson parametric converter includes a multi-Josephson junction ring modulator having arrays of N Josephson junctions arranged in a ring configuration with nodes inter-dispersed between the arrays. N is an integer having a value greater than one. The Josephson parametric converter includes a first and a second resonator formed from lumped-element capacitors that shunt the multi-Josephson junction ring modulator and respectively enable a first and a second mode of the Josephson parametric converter.

Abstract: The present disclosure provides a voltage system of a DRAM and a method for operating the same. The voltage system includes a first regulator, a second regulator and a control device. The control device determines the amount of regulators required based on an operation mode which the DRAM is instructed to operate under, and, based on the determination, enables one or more regulators between the first regulator and the second regulator and disables the remaining regulators. The amount of the one or more enabled regulators is equal to the determined amount of regulators required. The one or more enabled regulators provide a current which serves as an operation current of a bank of the DRAM.

Abstract: In a general aspect, a qubit device includes two circuit loops. In some aspects, a first circuit loop includes a first Josephson junction, a second circuit loop includes a second Josephson junction, and the first and second loops are configured to receive a magnetic flux that defines a transition frequency of a qubit device. In some aspects, a quantum integrated circuit includes an inductor connected between a first circuit node and a second circuit node; the first Josephson junction connected in parallel with the inductor between the first circuit node and the second circuit node; and the second Josephson junction connected in parallel with the inductor between the first circuit node and the second circuit node.

Abstract: A technique relates to a router. The router includes a qubit signal distributor, a readout signal distributor, and diplexers communicatively coupled to the qubit signal distributor and the readout signal distributor.

Abstract: A Josephson parametric converter is provided. The Josephson parametric converter includes a multi-Josephson junction ring modulator having arrays of N Josephson junctions arranged in a ring configuration with nodes inter-dispersed between the arrays. N is an integer having a value greater than one. The Josephson parametric converter further includes a first and a second resonator formed from lumped-element capacitors that shunt the multi-Josephson junction ring modulator and respectively enable a first and a second mode of the Josephson parametric converter. The Josephson parametric converter also includes a first and a second LC circuit for respectively coupling the first and the second resonator to external feedlines.

Abstract: A Josephson parametric converter is provided. The Josephson parametric converter includes a multi-Josephson junction ring modulator having a first, a second, a third, and a fourth node and a first, a second, a third, and a fourth array of N Josephson junctions arranged in a ring configuration with the nodes inter-dispersed between the arrays. The first array is between the first and second nodes, the second array is between the second and third nodes, the third array is between the third and fourth nodes, and the fourth array is between the fourth and first nodes. N is an integer having a value greater than one. The Josephson parametric converter further includes a first and a second resonator formed from lumped-element capacitors that shunt the multi-Josephson junction ring modulator and respectively enable a first and a second mode of the Josephson parametric converter.

Abstract: Introduced is an active shield method providing security to a security critical integrated circuit against some physical attacks like probing, manipulation and modification, while providing the ability to detect any physical modification made on the active shield itself. Electrically controllable switching circuits are used to construct the upper layer conductive bit lines with electrically selectable different interconnection configurations. These bit lines arranged in a shielding pattern are used to carry a test data between a transmitter circuitry and a number of receiver circuitries which verify the integrity of the shielding lines to provide the security for the integrated circuit. By changing the selected interconnection configuration of the bit lines with a select signal produced by the transmitter, the self detection ability of the proposed active shield is provided as a countermeasure against the vulnerability to physical modification made on the active shield itself.

Abstract: A superconducting integrated circuit may include a magnetic flux transformer having an inner inductive coupling element and an outer inductive coupling element that surrounds the inner inductive coupling element along at least a portion of a length thereof. The magnetic flux transformer may have a coaxial-like geometry such that a mutual inductance between the first inductive coupling element and the second inductive coupling element is sub-linearly proportional to a distance that separates the first inner inductive coupling element from the first outer inductive coupling element. At least one of the first inductive coupling element and the second inductive coupling element may be coupled to a superconducting programmable device, such as a superconducting qubit.

Abstract: A superconducting integrated circuit, comprising a plurality of superconducting circuit elements, each having a variation in operating voltage over time; a common power line; and a plurality of bias circuits, each connected to the common power line, and to a respective superconducting circuit element, wherein each respective bias circuit is superconducting during at least one time portion of the operation of a respective superconducting circuit element, and is configured to supply the variation in operating voltage over time to the respective superconducting circuit element.

Abstract: One embodiment of the invention includes a quantum system. The system includes a superconducting qubit that is controlled by a control parameter to manipulate a photon for performing quantum operations. The system also includes a quantum resonator system coupled to the superconducting qubit and which includes a first resonator and a second resonator having approximately equal resonator frequencies. The quantum resonator system can represent a first quantum logic state based on a first physical quantum state of the first and second resonators with respect to storage of the photon and a second quantum logic state based on a second physical quantum state of the first and second resonators with respect to storage of the photon.

Abstract: A superconducting readout system includes a computation qubit; a measurement device to measure a state of the computation qubit; and a latch qubit that mediates communicative coupling between the computation qubit and the measurement device. The latch qubit includes a qubit loop that includes at least two superconducting inductors coupled in series with each other; a compound Josephson junction that interrupts the qubit loop that includes at least two Josephson junctions coupled in series with each other in the compound Josephson junction and coupled in parallel with each other with respect to the qubit loop; and a first clock signal input structure to couple clock signals to the compound Josephson junction.

Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a Boolean logic circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A quantum processor may include multiple sets of qubits, each set coupled to respective annealing signal lines such that dynamic evolution of each set of qubits is controlled independently from the dynamic evolutions of the other sets of qubits.

Abstract: An architecture for a quantum processor may include a set of superconducting flux qubits operated as computation qubits and a set of superconducting flux qubits operated as latching qubits. Latching qubits may include a first closed superconducting loop with serially coupled superconducting inductors, interrupted by a split junction loop with at least two Josephson junctions; and a clock signal input structure configured to couple clock signals to the split junction loop. Flux-based superconducting shift registers may be formed from latching qubits and sets of dummy latching qubits. The devices may include clock lines to clock signals to latch the latching qubits. Thus, latching qubits may be used to program and configure computation qubits in a quantum processor.

Abstract: An architecture for a quantum processor may include a set of superconducting flux qubits operated as computation qubits and a set of superconducting flux qubits operated as latching qubits. Latching qubits may include a first closed superconducting loop with serially coupled superconducting inductors, interrupted by a split junction loop with at least two Josephson junctions; and a clock signal input structure configured to couple clock signals to the split junction loop. Flux-based superconducting shift registers may be formed from latching qubits and sets of dummy latching qubits. The devices may include clock lines to clock signals to latch the latching qubits. Thus, latching qubits may be used to program and configure computation qubits in a quantum processor.

Abstract: A coupling system to couple a first and a second qubit in response to a state of the coupling system that may be set by two input signals.

Abstract: A superconductor crossbar switch for connecting a plurality of inputs with a plurality of outputs, including a switching cell having an input, an output and a circuit for connecting the input with the output for bidirectionally transmitting data therebetween. The connection of the retaining and releasing circuitry of a plurality of cells enables the switch to simultaneously retain a selected cell or cells of a group of cells and disable the remaining cells of that group, whereby a subsequent query on a disabled cell is inoperative until the selected cell or cells is released. The crossbar switch is characterized by latency on the order of nanoseconds, a data rate per channel on the order of gigabits per second, essentially zero crosstalk, and detection of contention in nanoseconds or less and resolution of contention in nanoseconds or less.

Abstract: The disclosure generally relates to a method and apparatus for providing high-speed, low signal power amplification. In an exemplary embodiment, the disclosure relates to a method for providing a wideband amplification of a signal by forming a first transmission line in parallel with a second transmission line, each of the first transmission line and the second transmission line having a plurality of superconducting transmission elements, each transmission line having a transmission line delay; interposing a plurality of amplification stages between the first transmission line and the second transmission line, each amplification stage having an resonant circuit with a resonant circuit delay; and substantially matching the resonant circuit delay for at least one of the plurality of amplification stages with the transmission line delay of at least one of the superconducting transmission lines.

Abstract: Reversible and self reversing multi-value scrambling functions created by applying multi-value inverters are disclosed. The generation of possible multi-value inverters is also presented. Corresponding multi-value descrambling functions are also disclosed. The multi-value functions are used in circuits that scramble and descramble multi-value signals. The multi-value functions can also be used in signal generators. Such signal generators do not require the use of multipliers. The auto-correlation of the signals generated by the signal generators is also presented. Electronic circuits that implement the multi-value functions are also described.

Abstract: Apparatus, articles and methods relate to anti-symmetric superconducting devices for coupling superconducting qubits.

Abstract: A superconductor crossbar switch for connecting a plurality of inputs with a plurality of outputs, including a switching cell having an input, an output and a circuit for connecting the input with the output for bidirectionally transmitting data therebetween. The connection of the retaining and releasing circuitry of a plurality of cells enables the switch to simultaneously retain a selected cell or cells of a group of cells and disable the remaining cells of that group, whereby a subsequent query on a disabled cell is inoperative until the selected cell or cells is released. The crossbar switch is characterized by latency on the order of nanoseconds, a data rate per channel on the order of gigabits per second, essentially zero crosstalk, and detection of contention in nanoseconds or less and resolution of contention in nanoseconds or less.

Abstract: The present invention relates to a finely programmable Josephson voltage standard device employing microwave driving of multiple frequencies. To this end, the programmable Josephson voltage standard device includes a first element group 10a having the plurality of Josephson junctions 2 connected in series and applied with a first frequency f1; a second element group 20a having a plurality of Josephson junctions 2 connected in series and applied with a second frequency f2 different from the first frequency f1; and current bias meant for selectively applying positive (+) current or negative (?) current to the Josephson junctions 2 of the element groups 10a, 20a or stopping the supply of the current, in response to an input command. The first element group 10a and the second element group 20a are connected in series.

Abstract: A superconductor crossbar switch for connecting a plurality of inputs with a plurality of outputs, including a switching cell having an input, an output and a circuit for connecting the input with the output for bidirectionally transmitting data therebetween. The connection of the retaining and releasing circuitry of a plurality of cells enables the switch to simultaneously retain a selected cell or cells of a group of cells and disable the remaining cells of that group, whereby a subsequent query on a disabled cell is inoperative until the selected cell or cells is released. The crossbar switch is characterized by latency on the order of nanoseconds, a data rate per channel on the order of gigabits per second, essentially zero crosstalk, and detection of contention in nanoseconds or less and resolution of contention in nanoseconds or less.

Abstract: A single electron-transistor is used to read out charge states of two coupled qubits formed by two Cooper pair boxes. Detection is made about a gate voltage shift of the peak of the current that flows in the single electron transistor in accordance with the charge states. Since the current peak position varies depending on the particular charge state, all four charge states can be independently measured, or read out.

Abstract: A superconducting circuit includes a first transformer to produce a first alternating-current output at a secondary-side inductor, a second transformer to produce a second alternating-current output at a secondary-side inductor, a first pulse generating circuit to produce a single flux quantum pulse responsive to the first alternating-current output, a second pulse generating circuit to produce a single flux quantum pulse responsive to the second alternating-current output, and a confluence buffer circuit to merge the single flux quantum pulses from the pulse generating circuits, wherein each of the pulse generating circuits includes a superconducting loop including the secondary-side inductor, a first Josephson junction situated in the superconducting loop to generate the single flux quantum pulse, and a second Josephson junction situated in the superconducting loop, a threshold value of the second Josephson junction for an electric current flowing through the secondary-side inductor being different from tha

Abstract: Spin-orbital quantum cellular automata logic devices and integrated circuits in the form of a substrate having a thin film of material on the substrate having strongly coupled spin-orbital states, the thin film being patterned to define at least one input and at least one output, and to perform at least one logic operation by associated arrangement of the spin-orbital states between the input and the output. The logic devices and integrated circuits further include an input device at each input to define the spin-orbital states at each input, and an output sensor at each output for sensing the spin-orbital states of the thin film at the output. In an integrated circuit, the output of one gate or circuit, in the form of the ferromagnetically aligned spins, can be directly coupled to the next gate or circuit, so that entire circuits can be fabricated and effectively interconnected, only requiring interfacing for overall.

Abstract: A superconductor crossbar switch for connecting a plurality of inputs with a plurality of outputs, including a switching cell having an input, an output and a circuit for connecting the input with the output for bidirectionally transmitting data therebetween. The connection of the retaining and releasing circuitry of a plurality of cells enables the switch to simultaneously retain a selected cell or cells of a group of cells and disable the remaining cells of that group, whereby a subsequent query on a disabled cell is inoperative until the selected cell or cells is released. The crossbar switch is characterized by latency on the order of nanoseconds, a data rate per channel on the order of gigabits per second, essentially zero crosstalk, and detection of contention in nanoseconds or less and resolution of contention in nanoseconds or less.

Abstract: A crossbar switch includes a cross-point matrix with n input rows of cross-points and m output columns of cross-points. The crossbar switch further includes n decoders connected to the n input rows. Each of the n rows includes a single serial address input, a shift input and a data input. A serial address and data enter the address input and the data input in parallel. A shift sequence is transmitted on the single shift input. The data flows before the shift sequence on the shift input is complete. The data is shifted through the crossbar switch using a clock that is generated on-chip using a clock recovery circuit. The decoder converts a binary address input into a serial address and includes an N-bit counter with a plurality of toggle flip-flops. The crossbar switch is implemented using superconductor digital electronics such as rapid single flux quantum (RSFQ) logic.

Abstract: A superconductor memory array (10) has a high associated throughput with low power dissipation and a simple architecture. The superconductor memory array (10) includes memory cells (12a-12d) arranged in a row-column format and each including a storage loop (14a-14d) with a Josephson junction (16a-16d) for storing a binary value. Row address lines (24a, 24b) each are magnetically coupled in series to a row of the memory cells (12a-12d), and column address lines (26a, 26b) each are connected in series to a column of the memory cells (12a-12d). A sense amplifier (38a, 38b) is located on each of the column address lines (26a, 26b) for sensing state changes in the memory cells (12a-12d) located in the columns during a READ operation initiated by row address line READ signals.

Abstract: A superconducting self-clocked complementary SFQ logic family. The basic element of the circuit is a plurality of Josephson junctions and a control inductance coupled across a pair of voltage rails. An important aspect of the invention relates to the use of voltage biasing for the Josephson junctions, which provides several benefits. First, voltage biasing eliminates the need for biasing resistors as used in constant current mode devices. Such biasing resistors are known to be the dominant source of power dissipation in such logic circuits. Elimination of the biasing resistors thus reduce the power dissipation to the lowest possible value to that of the power dissipation of the switching devices themselves. In addition, the voltage biasing takes advantage of the voltage to frequency relationship of Josephson junctions and automatically establishes a global clock at the Josephson frequency without the need for extra circuitry; thus increasing the practical clock rate.

Abstract: An integrated circuit comprises plural superconducting circuit blocks connected through superconducting wiring strips, and each superconducting circuit block includes at least one superconducting logic circuit, constant input/output circuits connected between the input/output nodes of the circuit block and the superconducting logic circuit; parameters of the constant input/output circuits are regulated such that statically flow-in/flow-out current is approximately equal to zero at the input/output nodes of the superconducting logic circuit, whereby the superconducting logic circuit operates at the optimum operating point after the integration.

Abstract: An input voltage detecting circuit for detecting an input voltage is provided inside a PFM control charge pump circuit, and potential differences between potentials appearing at gate terminals and potentials appearing at source terminals are reduced by gate voltage controlling circuits for in response to a signal from the input voltage detecting circuit, suppressing gate voltages of switch transistors of a charge pump to suppress a rush current value to thereby reduce a current to prevent generation of a noise.

Abstract: Half-bridge assembly for switching electrical power, wherein at least two semiconductor switches are connected in series forming a half-bridge; each semiconductor switch comprises a control input, the first semiconductor switch comprises a first power terminal which can be connected with a high voltage potential; the second semiconductor switch comprises a second power terminal which can be connected with a low voltage potential; a second power terminal of each first semiconductor switch is connected with a first power terminal of the respective second semiconductor switch; each of the semiconductor switches comprises a free-wheeling diode which is located parallel to both power terminals of the respective semiconductor switch; and a Schottky diode is connected in parallel to each free-wheeling diode, each semiconductor switch with its free-wheeling diode and each Schottky diode is connected with a heat sink in a heat conductive manner, with the thermal resistance between each Schottky diode and the heat sink

Abstract: An apparatus for protecting an integrated circuit formed in a substrate and a method for protecting the integrated circuit against reverse engineering includes an active shield having a signal transmitter, a signal receiver, at least two conductor tracks running between the signal transmitter and the signal receiver, and a drive and evaluation device connected to the signal transmitter and to the signal receiver. The shield at least partially covers the integrated circuit. A covering composition applied on the substrate forms a mechanical protection of the integrated circuit. The shield has a switching apparatus. As a result, a capacitive measurement method can be carried out in a first switching state and damage to the shield can be detected in a second switching state.

Abstract: An integrated circuit comprises plural superconducting circuit blocks connected through superconducting wiring strips, and each superconducting circuit block includes at least one superconducting logic circuit, constant input/output circuits connected between the input/output nodes of the circuit block and the superconducting logic circuit; parameters of the constant input/output circuits are regulated such that statically flow-in/flow-out current is approximately equal to zero at the input/output nodes of the superconducting logic circuit, whereby the superconducting logic circuit operates at the optimum operating point after the integration.

Abstract: A logical processing part is formed by a pass transistor logic element, and an output signal of the pass transistor logic element is applied to the gates of MOS transistors for differentially amplifying and latching the output signal in the latch stage. This latch stage is formed by master and slave latch circuits, and power supply to the master latch circuit is cut off while holding an information signal only in the slave latch circuit with the level of a power supply voltage thereto increased, reducing a leakage current in a sleep mode or a power down mode. A logic circuit correctly operating at a high speed with low current consumption under a low power supply voltage is provided.

Abstract: The invention utilizes the linear complexity of orthogonal vectors to reduce the number of equations (or variables) to be solved. The present invention constructs a power model of a set of combinations of states without considering irrelevant combinations. The invention distinguishes between the switching direction on the input and the output pin. The invention considers state-dependency as a function of power consumed and depending on the paths through internal nodes. The model considers switching input pins that do not cause the output pin to switch to overcome inaccuracies caused by combining the power pin model with the state and arc power model with state. The model considers switching input pins that cause the output pin to switch. For cells in which the slewrate propagation effect from input to output is negligible, the invention uses a model of 2 power pins with state. The invention also determines the validity of this model.

Abstract: A receiver (50) for providing chip-to-chip communication in a superconductor integrated circuit. The receiver (50) includes a detector circuit (52) for asynchronously receiving an input current, a splitter circuit (60) connected to the detector circuit (52) for generating first and second signals, a delay circuit (62) receiving the second signal from the splitter circuit for generating a delayed signal and a register circuit (64) receiving the first signal from the splitter circuit (60) and the delayed signal from the delay circuit (62) for producing a single flux quantum (SFQ) pulse. The receiver (50) according to the present invention provides an asynchronous chip-to-chip communication between a multi-chip superconductive circuit having low input current without an external rf clock.

Abstract: A single-flux-quantum digital device includes a first superconducting line extended in a large ring, a second superconducting line connected to the first superconducting line, a superconducting single electron transistor for regulating a supercurrent flowing through the second superconducting line, and a small tunnel junction device for detecting a change in the supercurrent flowing through the first superconducting line. The first superconducting line is extended in a large ring. The second superconducting line divides the large ring into two small rings which are substantially the same in shape and area. The small tunnel junction device is connected to a point where the first and the second superconducting line are joined.