Abstract: It is described an electrical installation measuring system comprising a control and measuring device configured to be installed on an electrical panel of an electrical installation and perform at least one measure of an electrical parameter of the electrical installation depending on an electrical load connected to the electrical installation and transmit command signals along a telecommunication link. The system further comprises a variable load device connectable to the electrical installation and configured to: receive the command signals from the telecommunication link; and assume a plurality of load configurations according to the command signals.

Abstract: An integrated circuit memory device having: a memory cell; and a voltage driver of depletion type connected to the memory cell. In a first polarity, the voltage driver is powered by a negative voltage relative to ground to drive a negative selection voltage or a first de-selection voltage; In a second polarity, the voltage driver is powered by a positive voltage relative to ground to drive a positive selection voltage or a second de-selection voltage. The voltage driver is configured to transition between the first polarity and the second polarity. During the transition, the voltage driver is configured to have a control voltage swing for outputting de-selection voltages smaller than a control voltage swing for output selection voltages.

Abstract: Heterojunction structure, also referred to as a heterostructure, of semiconductor material, in particular for a high electron mobility transistor (HEMT), includes a substrate, a stack of at least three buffer layers of a same semiconductor material with a wide bandgap EG1 based on a column-III nitride, namely an unintentionally doped first buffer layer, a second buffer layer, an unintentionally doped third buffer layer, an unintentionally doped intermediate layer, and a barrier layer arranged on the intermediate layer, said barrier layer being of a semiconductor material with a wide bandgap EG2 based on a column-III nitride; the second buffer layer has constant P+ doping throughout some or all of its thickness; and the third buffer layer includes a first region which is unintentionally doped throughout its entire thickness and at least one second region adjacent to said first region with N+ doping surrounding the first region.

Abstract: A method of forming a high electron mobility transistor may include: forming a second III-V compound layer on a first III-V compound layer, the second III-V compound layer and the first III-V compound layer differing in composition; forming a p-type doped region in the first III-V compound layer; forming an n-type doped region in the second III-V compound layer, the n-type doped region overlying the p-type doped region; forming a source feature over the second III-V compound layer, the source feature overlying the n-type doped region; and forming a gate electrode over the second III-V compound layer, the gate electrode disposed laterally adjacent to the source feature.

Abstract: A control device (42) for use in a motor vehicle includes at least one input that has an input port (12), at least one input channel (20, 38), and an input circuitry (43) and receives signals from a sensor (10, 34) via the input port (12) and sends the signals via the input circuitry (43) to the input channel (20, 38). The input port (12) is connected to a defined voltage via a resistor. The input circuitry (43) has a pull-up switch (44) that can be actuated by the control device (42), which controls connection of the input port (12) to a high voltage, and a pull-down switch (46) that can be actuated by the control device (42), which controls connection of the input port (12) to a low voltage. A method adapts the control device (42) to the sensor (10, 34), which is connected to the control device (42).

Abstract: PICA test circuits are shown that include a first transistor and a second transistor laid out drain-to-drain, such that a gap between respective drain regions of the first and second transistors has a minimum size allowed by a given fabrication technology.

Abstract: Provided is a programmable circuit. The programmable circuit includes a first path and a second path connected in parallel between a first voltage node and a second voltage node. The first path includes a first programmable element, a first node, a first pull-up transistor, a second node, and a first pull-down transistor connected in series between the first voltage node and the second voltage node. The second path includes a second programmable element, a third node, a second pull-up transistor, a fourth node, and a second pull-down transistor connected in series between the first and second voltage nodes. A gate electrode of the first pull-up transistor, a gate electrode of the first pull-down transistor, and the fourth node are electrically connected to one another. A gate electrode of the second pull-up transistor, a gate electrode of the second pull-down transistor, and the second node are electrically connected to one another.

Abstract: A field-programmable analog array (FPAA) includes a digital signal routing network, an analog signal routing network, switch elements to interconnect the digital signal routing network with the analog signal routing network, and a configurable analog block (CAB) connected to the analog signal routing network and having a programmable resistor array. The switch elements are implemented via digital memristors, the programmable resistor array is implemented via analog memristors, and/or antifuses within one or more of the digital signal routing network and the analog signal routing network are implemented via digital memristors.

Abstract: Programmable integrated circuits with configurable logic circuitry and routing resources are provided. Portions of the routing resources on a programmable integrated circuit may be used in implementing a desired user-specified custom logic function, whereas other portions of the routing resources on the programmable integrated circuit may be unused. The unused routing resources may include adjacent pairs of routing paths. These paths may be coupled to control circuitry configured to drive the routing paths to desired voltage levels to provide an optimal amount of decoupling capacitance. In one suitable arrangement, two adjacent routing paths may both be driven to a positive power supply voltage level. In another suitable arrangement, the two adjacent routing paths may be driven to the positive power supply voltage level and a ground power supply voltage level, respectively.

Abstract: A method for driving a semiconductor device capable of reducing an area of a multiplexer and reducing its power consumption is provided. In a method for operating a semiconductor device including a memory and a multiplexer, a first transistor is connected to a first capacitor, and a second transistor is connected to a second capacitor. In the multiplexer, in a third transistor, a source is connected to a first input terminal and a drain is connected to an output terminal and, in a fourth transistor, a source is connected to a second input terminal and a drain is connected to the output terminal. Further, a step of holding a first potential in a node to which the first transistor, the first capacitor, and a gate of the third transistor are connected and holding a second potential higher than the first potential in the node is included.

Abstract: As semiconductor devices including semiconductors, logic circuits are given. Logic circuits include dynamic logic circuits and static logic circuits and are formed using transistors and the like. Dynamic logic circuits can store data for a certain period of time. Thus, leakage current from transistors causes more severe problems in dynamic logic circuits than in static logic circuits. A logic circuit includes a first transistor whose off-state current is small and a second transistor whose gate is electrically connected to the first transistor. Electric charge is supplied to a node of the gate of the second transistor through the first transistor. Electric charge is supplied to the node through a first capacitor and a second capacitor. On/off of the second transistor is controlled depending on a state of the electric charge. The first transistor includes an oxide semiconductor in a channel formation region.

Abstract: A semiconductor device includes multiple transistors (70, 75, 80, 85), each of the transistors (70, 75, 80, 85) including a gate electrode (18) formed above a semiconductor substrate (30), source/drain regions (10, 12, 14, 16) formed on both sides of the gate electrode (18), and a charge storage layer (38) interposed between the gate electrode (18) and the semiconductor substrate (30). One of the source/drain regions (10, 12, 14, 16) of adjacent transistors (70, 75, 80, 85) is respectively connected in series, so the above-mentioned multiple transistors (70, 75, 80, 85) form a closed loop in the semiconductor device. Accordingly, it is possible to provide a semiconductor device (60) in which the circuit function of the logic circuit (64) can be reconfigured in a non-volatile manner, thereby enabling wide selectivity and excellent design facility in terms of the circuit design and making it possible to readily fabricate the logic circuit (64) and a non-volatile memory (62) on a single chip (60).

Abstract: A logic device includes: a substrate having a channel layer; two input terminal patterns of ferromagnetic material formed on the substrate and spaced apart from each other along a longitudinal direction of the channel layer so as to serve as the input terminals of a logic gate; and an output terminal pattern of ferromagnetic material formed on the substrate and disposed between the two input terminal patterns to serve as an output terminal of the logic gate. The output terminal pattern reads an output voltage by using spin accumulation and diffusion of electron spins which are injected into the channel layer from the input terminal patterns.

Abstract: A repair circuit having a repair controller which is capable of reducing unnecessary current dissipation by interrupting a control operation to redundant cells that are unused for replacement of defective cells is presented. The repair circuit includes a repair controller and a repair signal generator. The repair controller is configured to generate a first drive voltage, a second drive voltage and a repair control signal depending on whether or not a defective cell exists. The repair signal generator driven by the first and second drive voltages in which the repair signal generator is configured to generate a repair signal, for repairing the defective cell, in response to receiving the repair control signal and an external address.

Abstract: A method and apparatus of providing a programmable system using non-volatile programmable transistors are disclosed. A programmable logic circuit, in one embodiment, includes a first programmable transistor and a second programmable transistor. The first programmable transistor includes a first gate terminal, a first source terminal, a first drain terminal, and a first programming terminal. The second programmable transistor includes a second gate terminal, a second source terminal, and a second drain terminal, and a second programmable terminal. The first and second programmable transistors include non-volatile memory elements. The first and the second gate terminals are coupled to an input terminal, and the first drain terminal and the second source terminal are coupled to an output terminal to perform a logic function.

Abstract: A semiconductor integrated circuit includes an n-channel spin FET including one of a magnetic tunnel junction and a magneto-semiconductor junction, the n-channel spin FET including a gate terminal to receive an input signal, a source terminal to receive a first power supply potential, and a drain terminal connected to an output terminal, a p-channel FET including a gate terminal to receive a clock signal, a source terminal to receive a second power supply potential, and a drain terminal connected to the output terminal, a subsequent circuit connected to the output terminal, and a control circuit which turns on the p-channel FET to start charging the output terminal, then turns off the p-channel FET to end the charging, and supplies the input signal to the gate terminal of the n-channel spin FET.

Abstract: A normally-off power field-effect transistor semiconductor structure is provided. The structure includes a channel, a source electrode, a gate electrode and trapped charges which arranged between the gate electrode and the channel such that the channel is in an off-state when the source electrode and the gate electrode are on the same electric potential. Further, a method for forming a semiconductor device and a method for programming a power field effect transistor are provided.

Abstract: A convertible logic circuit includes a plurality of carbon nanotube transistors. Each carbon nanotube transistors are configurable as p-type or an n-type transistors according to a voltage of a power source voltage. Each carbon nanotube transistor includes a source electrode, a drain electrode, a channel formed of a carbon nanotube between the source electrode and the drain electrode, a gate insulating layer formed on the carbon nanotubes, and a gate electrode formed on the gate insulating layer.

Abstract: A method and apparatus of providing a programmable system using non-volatile programmable transistors are disclosed. A programmable logic circuit, in one embodiment, includes a first programmable transistor and a second programmable transistor. The first programmable transistor includes a first gate terminal, a first source terminal, a first drain terminal, and a first programming terminal. The second programmable transistor includes a second gate terminal, a second source terminal, and a second drain terminal, and a second programmable terminal. The first and second programmable transistors include non-volatile memory elements. The first and the second gate terminals are coupled to an input terminal, and the first drain terminal and the second source terminal are coupled to an output terminal to perform a logic function.

Abstract: A method and apparatus of providing a programmable system using non-volatile programmable transistors are disclosed. A programmable logic circuit, in one embodiment, includes a first programmable transistor and a second programmable transistor. The first programmable transistor includes a first gate terminal, a first source terminal, a first drain terminal, and a first programming terminal. The second programmable transistor includes a second gate terminal, a second source terminal, and a second drain terminal, and a second programmable terminal. The first and second programmable transistors include non-volatile memory elements. The first and the second gate terminals are coupled to an input terminal, and the first drain terminal and the second source terminal are coupled to an output terminal to perform a logic function.

Abstract: An antifuse circuit includes a terminal, an antifuse, and a select transistor. The antifuse is coupled to the terminal and has an associated program voltage. The select transistor is coupled to the antifuse and has a gate terminal coupled to receive a first select signal. The select transistor operates in a snapback mode of operation in response to an assertion of the first select signal and the program voltage at the terminal.

Abstract: An apparatus and method provides the foundation for designing reconfigurable electronic computing systems. The invention relies on an ability to change the resistance state of a memristor device to achieve an optimal voltage at specific circuit nodes, whereby this dynamically and autonomously causes the circuit to reconfigure itself and produce a different output for the same input relative to the circuit's initial state. The circuit's state remains constant until the memristor's resistance is changed, at which point the circuit's function is “reprogrammed”.

Abstract: A method and apparatus of providing a programmable system using non-volatile programmable transistors are disclosed. A programmable logic circuit, in one embodiment, includes a first programmable transistor and a second programmable transistor. The first programmable transistor includes a first gate terminal, a first source terminal, a first drain terminal, and a first programming terminal. The second programmable transistor includes a second gate terminal, a second source terminal, and a second drain terminal, and a second programmable terminal. The first and second programmable transistors include non-volatile memory elements. The first and the second gate terminals are coupled to an input terminal, and the first drain terminal and the second source terminal are coupled to an output terminal to perform a logic function.

Abstract: A mixed signal integrated circuit includes a digital logic array and an analog cell array. Each cell of the analog cell array shares a common architecture and is fully programmable. An analog cell includes mirror NFETs, cascode NFETs, differential pair NFETs, differential pair PFETs, cascode PFETs and mirror PFETs. An analog cell may also include special purpose components, such as low value resistors, high value resistors and PFETs.

Abstract: A method and apparatus of providing a programmable system using non-volatile programmable transistors are disclosed. A programmable logic circuit, in one embodiment, includes a first programmable transistor and a second programmable transistor. The first programmable transistor includes a first gate terminal, a first source terminal, a first drain terminal, and a first programming terminal. The second programmable transistor includes a second gate terminal, a second source terminal, and a second drain terminal, and a second programmable terminal. The first and second programmable transistors include non-volatile memory elements. The first and the second gate terminals are coupled to an input terminal, and the first drain terminal and the second source terminal are coupled to an output terminal to perform a logic function.

Abstract: A spin MOSFET includes: a first ferromagnetic layer provided on an upper face of a semiconductor substrate, and having a fixed magnetization direction perpendicular to a film plane; a semiconductor layer provided on an upper face of the first ferromagnetic layer, including a lower face opposed to the upper face of the first ferromagnetic layer, an upper face opposed to the lower face, and side faces different from the lower face and the upper face; a second ferromagnetic layer provided on the upper face of the semiconductor layer, and having a variable magnetization direction perpendicular to a film plane; a first tunnel barrier provided on an upper face of the second ferromagnetic layer; a third ferromagnetic layer provided on an upper face of the first tunnel barrier; a gate insulating film provided on the side faces of the semiconductor layer; and a gate electrode provided on the side faces of the semiconductor layer with the gate insulating film being interposed therebetween.

Abstract: A programmable transistor array circuit is disclosed comprising a semiconductor substrate; and a plurality of basic transistor units (BTUs) arranged in rows and columns of uniformly spaced cells, the BTUs further comprising PMOS transistor units (PTUs), NMOS transistor units (NTUs) and dummy transistor units (DTUs) each BTU having conductors arranged in a single direction running through the BTUs and the conductors being uniformly spaced with respect to each other. The arrangement of the BTUs is subject to restricted design rules. Logical transistor units (LTUs) are formed from the BTUs using first and second layers of metallization. Methods for producing integrated circuits are disclosed forming programmable transistor arrays and implementing customer specified system designs upon the programmable transistor arrays.

Abstract: A semiconductor device may be created using multiple metal layers and a layer including programmable vias that may be used to form various patterns of interconnections among segments of metal layers. The programmable vias may be formed of materials whose resistance is changeable between a high-resistance state and a low-resistance state.

Abstract: An e-fuse circuit, a method of programming the e-fuse circuit, and a design structure of the e-fuse circuit. The method includes in changing the threshold voltage of one selected field effect transistor of two field effect transistors connected to different storage nodes of the circuit so as to predispose the circuit place the storage nodes in predetermined and opposite states.

Abstract: A programmable logic device architecture having logic elements with dedicated hardware to configure the look up tables of the logic element to either perform logic functions or to operate as a register for pipelining or other purposes. The programmable logic device includes a general interconnect and a plurality of logic array blocks interconnected by the general interconnect. Each of the plurality of logic blocks further includes one or more logic elements. The logic elements each include a first look up table, a second look up table, and dedicated hardware within the logic element to configure the first look table and the second look up table as a register without having to use the general interconnect. In one embodiment, the dedicated hardware includes a plurality of dedicated interconnects within the logic element to configure the two look up tables as a pair of cross coupled muxes or latches when configured as a register.

Abstract: A packaged PLD solution includes a first die having a masked-Read Only Memory (ROM) that is programmed during its fabrication to store configuration data, and includes a second die having a PLD including a number of configurable resources collectively configured to implement a circuit design embodied by the configuration data. The first die is electrically connected to the second die, and both the first die and second die are stacked and encapsulated together to form the packaged PLD solution. The configuration data is programmed into the masked-ROM by a manufacturer of both the masked-ROM and the PLD.

Abstract: It is made possible to provide a spin MOSFET that can minimize the increase in production costs and can perform both spin injection writing and reading. A spin MOSFET includes: a substrate that has a semiconductor region of a first conductivity type; first and second ferromagnetic stacked films that are formed at a distance from each other on the semiconductor region, and each have the same stacked structure comprising a first ferromagnetic layer, a nonmagnetic layer, and a second ferromagnetic layer stacked in this order, the second ferromagnetic stacked film having a film-plane area different from that of the first ferromagnetic stacked film; a gate insulating film that is formed on a portion of the semiconductor region, the portion being located between the first ferromagnetic stacked film and the second ferromagnetic stacked film; and a gate that is formed on the gate insulating film.

Abstract: A semiconductor integrated circuit has a voltage supply terminal; a first input terminal fed with a first input signal; an output terminal that outputs an output signal; a second input terminal fed with a second input signal; a first MOS transistor having one end connected to the voltage supply terminal and a gate electrode connected to the first input terminal; a second MOS transistor having one end connected to a first potential, an other end connected to the output terminal, and a gate electrode connected to the second input terminal; and a program element acting as a MOS transistor having one end connected to the other end of the second MOS transistor and an other end connected to a second potential higher than the first potential.

Abstract: A convertible logic circuit includes a plurality of carbon nanotube transistors. Each carbon nanotube transistors are configurable as p-type or an n-type transistors according to a voltage of a power source voltage. Each carbon nanotube transistor includes a source electrode, a drain electrode, a channel formed of a carbon nanotube between the source electrode and the drain electrode, a gate insulating layer formed on the carbon nanotubes, and a gate electrode formed on the gate insulating layer.

Abstract: A semiconductor integrated circuit includes an n-channel spin FET including one of a magnetic tunnel junction and a magneto-semiconductor junction, the n-channel spin FET including a gate terminal to receive an input signal, a source terminal to receive a first power supply potential, and a drain terminal connected to an output terminal, a p-channel FET including a gate terminal to receive a clock signal, a source terminal to receive a second power supply potential, and a drain terminal connected to the output terminal, a subsequent circuit connected to the output terminal, and a control circuit which turns on the p-channel FET to start charging the output terminal, then turns off the p-channel FET to end the charging, and supplies the input signal to the gate terminal of the n-channel spin FET.

Abstract: It is made possible to provide a reconfigurable logic circuit with which high integration can be achieved. A reconfigurable logic circuit includes: a multiplexer which includes a plurality of spin MOSFETs each having a source and drain containing a magnetic material, and a selecting portion including a plurality of MOSFETs and selecting a spin MOSFET from the plurality of spin MOSFETs, based on control data transmitted from control lines; a determining circuit which determines whether magnetization of the magnetic material of the source and drain of a selected spin MOSFET, which is selected by the selecting portion, is in a first state or in a second state; and a first and second write circuits which put the magnetization of the magnetic material of the source and drain of the selected spin MOSFET into the second and first states respectively by supplying a write current flowing between the source and drain of the selected spin MOSFET.

Abstract: A circuit is attached in parallel to a universal serial bus interface of a data processing system. A capacitor in the circuit is charged by receiving power from a power pin of the universal serial bus interface while the data processing system is not in a reduced power state. A vibration sensor is unpowered while the data processing system is not in a reduced power state. The vibration sensor is disconnected from a data pin of the universal serial bus interface while the data processing system is not in a reduced power state. When the data processing system enters a reduced power state, the capacitor provides power to the vibration sensor. When a vibration is detected by the vibration sensor, a switch connects the vibration sensor to the data pin of the universal serial bus interface, providing a wake up signal to the data processing system.

Abstract: Methods and circuitry for reducing ground bounce and VCC sag effects in integrated circuit (“IC”) devices is provided. In particular, a via-programmable design for I/O circuitry in IC devices is provided. The via-programmable I/O circuitry is used to disconnect I/O pin driver circuitry from and create a substantially direct connection between unused I/O pins and the ground and/or VCC signals of an IC device to reduce ground bounce and VCC sag, respectively.

Abstract: A method of operating a programmable logic device, including the steps of using a full VDD supply voltage to operate one or more active blocks of the programmable logic device, and using a reduced supply voltage (e.g., ½ VDD) to operate one or more inactive blocks of the programmable logic device. The full VDD supply voltage and reduced supply voltage can be provided to the blocks of the programmable logic device through high-voltage n-channel transistors. A boosted voltage, greater than VDD, is applied to the gate of an n-channel transistor to provide the full VDD supply voltage to an active block. A standby voltage, less than VDD, is applied to the gate of an n-channel transistor to provide the reduced supply voltage to an inactive block. The inactive blocks can be determined during run time and/or design time of the programmable logic device.

Abstract: A logic gate is described that implements complex logic within a memory array. The logic gate receives at least three of a first storage cell signal, a second storage cell signal, a first external signal, or a second external signal at a first input circuitry and second input circuitry. The logic gate then performs one of a set of logic functions using the first storage cell signal, the second storage cell signal, the first external signal, or the second external signal. The set of logic functions includes at least one of a matching function, an OR-AND function, or an AND function.

Abstract: A logic basic cell contains a first logic function block and a second logic function block for the logic combination of a first input signal and a second input signal in accordance with a predeterminable first or second logic subfunction, and a first logic transistor coupled to the first logic function block, having a gate terminal, at which a third input signal can be provided, and having a source/drain terminal at which the output signal can be provided. Furthermore, a second logic transistor coupled to the second logic function block is provided, having a gate terminal, at which a complementary signal with respect to the third input signal can be provided, and having a source/drain terminal, which is coupled to the source/drain terminal of the first logic transistor.

Abstract: A non-volatile memory cell comprises a first floating gate transistor having a source, a drain, and a gate electrically coupled to a row line. A second floating gate transistor has a source, a drain, and a gate electrically coupled to the row line. A first p-channel MOS transistor has a source, a drain, and a gate, the drain of the first p-channel MOS transistor electrically coupled to the drain of the first floating gate transistor forming a first common node. A second p-channel MOS transistor has a source, a drain, and a gate, the first drain of the second p-channel MOS transistor electrically coupled to the drain of the second floating gate transistor forming a second common node, the gate of the second p-channel MOS transistor electrically coupled to the first common node, and the second common node electrically coupled to the gate of the first p-channel MOS transistor.

Abstract: A power supply circuit contains a plurality of DC-DC converter control loops that provide respectively different control signals. A plurality of output driver stages of given current drive capabilities have their inputs programmably connectable via a set of switches to control signals that may be generated by any of the converter control loops. The output of each output driver stage is externally selectively connectable to any of plural output voltage ports, so that each output voltage port is capable of supplying any of the respectively different output voltages associated with the voltage control signals generated by the DC-DC converter control loops, and has an output current capability that depends upon which output driver stages are coupled to it.

Abstract: A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A non-volatile memory transistor is coupled to each of the n inputs of the multiplexer. The multiplexer has x address inputs wherein 2x=n as is known in the art. The output of the multiplexer is coupled to VCC through a pullup transistor. The gate of the pullup transistor is coupled to the output of an address transition detector circuit that has inputs coupled to the address inputs of the multiplexer. A sense amplifier is coupled to the output of the multiplexer.

Abstract: An apparatus and method for reducing leakage current of transistors used in an integrated circuit, which selectively switch a processor circuit in the integrated circuit to a standby state. A cooling device is included and selectively located in an area of the integrated circuit that is in close proximity to a transistor used to switch a processor circuit between active and standby states. The cooling device cools the transistor in order to improve both its leakage and active current states, thereby increasing efficiency of the transistor and reducing its leakage current.

Abstract: A manufacturing method of a semiconductor device capable of obtaining highly reliable semiconductor devices with the realization of high integration and high speed intended is provided. During processes after a desired circuit including a CMOS static type circuit is formed on a semiconductor substrate until product shipment, a first operation of feeding a predetermined input signal to the circuit and retrieving a first output signal corresponding to it and a second operation of giving an operating condition of increasing an ON resistance value of MOSFETs constituting the CMOS static type circuit and retrieving a second output signal corresponding to the condition are conducted, and a testing step of determining a failure by the first output signal varying from the second output signal.

Abstract: A field programmable gate array (FPGA) cell useful in a FPGA array having column bitlines, read bitlines, and row wordlines is disclosed. The cell comprises a capacitor having a first terminal and a second terminal, the first terminal connected to a column bitline, said second terminal connected to a switch control node, the capacitor having a dielectric between the first and second terminal. The cell also includes a select transistor having a gate, a source, and a drain, the gate connected to the read bitline, the source connected to the switch control node, and the drain connected to a row wordline. Finally, the cell includes a switch being controlled by the switch control node.

Abstract: A one transistor, non-volatile programmable switch includes uni-directional and in some embodiments, bi-directional, states. The programmable switch is used in an integrated circuit, and comprises a first node and a second node coupled with corresponding circuit elements in the integrated circuit. A non-volatile programmable transistor having a drain coupled to one of the first node and second node, a source coupled to the other of the first node and second node, gate coupled to an energizing conductor, and a data storage structure constitute the programmable switch. The non-volatile programmable transistor used in the switch is a charge programmable device (e.g. SONOS cell), in which the data storage structure comprises a nitride layer, or other charge trapping layer, between oxides or other insulators.

Abstract: A bifurcation circuit uses dynamic asP* protocol. to exchange data among three or more FIFOs. Each FIFO contains a plurality of places containing data and a plurality of paths that exchange data between neighboring places. The bifurcator circuit generally comprises a control FIFO, two subordinate FIFOs and a bifurcation path coupled to all three FIFOs. The bifurcator circuit further comprises a chain of data latches coupled to all three FIFOs at the bifurcation path. A data value carried in the control FIFO determines which of the subordinate FIFOs exchanges data with the control FIFO. Each place in the FIFOs contains a set reset flip-flop in which the state of each place is held by a single wire and stabilized by a keeper. A single transistor sets or resets the state of the place. The pulse that changes the state of the control flip-flops also makes the data latches momentarily transparent. The bifurcator circuit is generally capable of a branch or join operations.

Abstract: Logic array circuits are formed on SOI substrates. The pull-down network (130) of the logic array circuit comprises NMOS transistors (125) and PMOS transistors (120) configured in series.