Abstract: A level shifter causes a switch to open or close by selecting one of two stored logical values to generate a gate-drive voltage to cause a transition in the switch.

Abstract: An impedance measurement device of the present disclosure includes: an electrochemical energy device; an amplifier connected to each connection terminal of the electrochemical energy device and configured to amplify a signal introduced into a wiring; and a main board configured to receive the signal from the amplifier and measure an impedance. Accordingly, the present invention has advantages in that high resistance to electromagnetic interference may be achieved by disposing a preamplifier close to a terminal of an electrochemical energy device to amplify only the signal without amplifying a noise introduced into a wiring.

Abstract: A level shift circuit includes first to fourth n-type transistors, first and second p-type transistors, and first and second inverters. The first n-type transistor receives an input signal at its gate and has a drain connected to an inverted output node. The first p-type transistor is placed between a third power supply and the inverted output node. The second n-type transistor receives an inverted input signal at its gate and has a drain connected to an output node. The second p-type transistor is placed between the third power supply and the output node. The third n-type transistor is between the inverted output node and an inverted input node, and the first inverter between the drain and gate of the third n-type transistor. The fourth n-type transistor is between the output node and an input node, and the second inverter between the drain and gate of the fourth n-type transistor.

Abstract: A data transmission system includes a first circuit, a second circuit, and a reference voltage generation circuit. The first circuit includes a transmitter powered by a first power supply voltage and having an input for receiving a data output signal, and an output. The second circuit includes a receiver powered by a second power supply voltage and having a first input coupled to the output of the transmitter, a second input for receiving a reference voltage, and an output for providing a data input signal. The reference voltage generation circuit forms the reference voltage by mixing a first signal generated by the first circuit based on the first power supply voltage and a second signal generated by the second circuit based on the second power supply voltage.

Abstract: Each of latch circuits outputs a pulse of a first kind of signal to a pixel circuit row. Shift register units serially output pulses of a second kind of signal. Each of the latch circuits receives the pulse of the second kind of signal from a first shift register unit and the pulse of the second kind of signal from a second shift register unit of a later stage than the first shift register unit. The pulse of the first kind of signal from each of the latch circuits changes from a first potential level to a second potential level in response to the pulse of the second kind of signal from the first shift register unit and changes from the second potential level to the first potential level in response to the pulse of the second kind of signal from the second shift register unit.

Abstract: An electrostatic discharge (ESD) protection circuit includes an ESD detector connected between a pad and a first power source and configured to generate a detection signal when ESD is detected at the pad, a switch transistor including a gate controlled by the detection signal and a source and a drain connected between the pad and the memory, and a leakage current prevention circuit including a first transistor including a first gate connected to a second power source and a source and a drain connected between the pad and a first node, and a second transistor including a second gate connected to the pad and a source and a drain connected between the first node and the second power source. The first node is connected to or in electrical communication with a bulk node of the switch transistor.

Abstract: Embodiments of the present disclosure provide a level shifter, including: first and second NMOS transistors, wherein the sources of the first and second NMOS transistors are coupled to a first voltage, the gate of the first NMOS transistor is connected to an inverse of an input signal that varies between a second voltage and a third voltage, and wherein the gate of the second NMOS transistor receives a buffer of the input signal. a breakdown protection circuit has third and fourth NMOS transistors, the gates of the third and fourth NMOS transistors being connected to the third voltage, the drain of the first NMOS transistor being connected to the source of the third NMOS transistor, and the drain of the second NMOS transistor being connected to the source of the fourth NMOS transistor. A pull-up circuit is connected to the drains of the third and fourth NMOS transistors.

Abstract: A low power comparator and a self-regulated device for adjusting power saving level of an electronic device are provided. The low power comparator includes an input differential pair circuit, a self-regulated device, and a tail current switch. The input differential pair circuit is configured to receive input signals to be compared. The self-regulated device is coupled to the input differential pair circuit and includes a self-regulated circuit which has a first transistor with a first threshold voltage and a second transistor with a second threshold voltage and is configured to adjust a power saving level of the low-power comparator according to the first threshold voltage and the second threshold voltage. The tail current switch is coupled to the input differential pair circuit through the self-regulated circuit to provide a constant current to the input differential pair circuit.

Abstract: Methods, systems, and devices for redundant data bus inversion (DBI) sharing are described. A device may identify a group of channels included in a data bus. The device may determine whether the group of channels satisfies a criterion. Based on the determination, the device may allocate an overhead channel to the group of channels for a set of redundancy operations. Based on the determination, the device may allocate the overhead channel to the group of channels for a set of data bus inversion operations. The device may encode data associated with the group of channels based on the allocation of the overhead channel. The overhead channel may be included in the data bus.

Abstract: A level shifter includes a control circuit and a bias circuit. The control circuit receives a bias voltage, a first signal associated with a first voltage domain, and supply voltages associated with a second voltage domain, and outputs a second signal that is associated with the second voltage domain. The bias circuit generates the bias voltage that is indicative of the duty cycle of the second signal, and provides the bias voltage to the control circuit to control the duty cycle of the second signal. The duty cycle of the second signal is controlled such that a difference between a duty cycle of the first signal and an inverse of the duty cycle of the second signal is less than a tolerance limit.

Abstract: A circuit includes a power management circuit and a memory circuit. The power management circuit is configured to receive a first control signal and a second control signal, and to supply a first supply voltage, a second supply voltage and a third supply voltage. The first control signal has a first voltage swing, and the second control signal has a second voltage swing different from the first voltage swing. The first control signal causes the power management circuit to enter a power management mode having a first state and a second state. The memory circuit is coupled to the power management circuit, and is in the first state or the second state in response to at least the first supply voltage supplied by the power management circuit.

Abstract: Disclosed is a signaling circuit. A switch circuit generates an internal reference supply voltage and an internal lower supply voltage, from first and second power supply voltages. A transmit circuit drives a high bit from the first power supply voltage, and drives a low bit from the internal lower supply voltage. The second terminal of the data output is connected to the internal reference supply voltage.

Abstract: Disclosed are level shifters and methods of performing level shifting. In one embodiment, a level shifter is disclosed comprising an input, cross-coupled/latch circuitry, a first reference node, a second reference node, and output circuitry coupled between the cross-coupled/latch circuitry and an output, wherein the output circuitry sets the output signal to high based on rising edge of a second reference node and sets the output signal to low based on the rising edge of the first reference node. Further, in some implementations, the first reference node and the second reference node may have signals that are inverse to each other.

Abstract: A semiconductor device that can automatically transition from a standby mode to a deep power down (DPD) mode is provided. The semiconductor device includes a DPD controller supporting the DPD mode and multiple internal circuits. The DPD controller measures a time since a time point of entering the standby mode and generates multiple power down enable signals for further reducing power consumption in the standby mode in response to elapse of a measurement time, so that operations of the multiple internal circuits are stopped in stages.

Abstract: A single stage transmitter that operates at high speed is configured to operate as a driver in write mode and a termination in read mode. The driver configuration includes two circuits. The first circuit includes a PMOS cross-coupled device and a PMOS cascode circuit. The second circuit includes a NMOS cross-coupled device and a NMOS cascode circuit. The PMOS cross-coupled device and the NMOS cross-coupled device is connected in series by alternating current (AC) coupling capacitors. The termination configuration includes a third circuit including MOSFET transmission gates and an inverter controlled by a termination mode enable signal. In write mode, the third circuit of the single stage transmitter is turned off and the first and second circuits are operational. In read mode, the first and second circuits of the single stage transmitter are inactive and the third circuit is operational.

Abstract: A light emitting diode system includes at least one light emitting diode and a light emitting diode driving apparatus. The light emitting diode driving apparatus includes a burning signal detector, a burning controller, a memory and a light emitting diode circuit. The burning signal detector includes an optical element, a signal trimmer and a signal detector. The burning signal detector wirelessly receives a wireless signal. The burning signal detector converts the wireless signal into a local stored signal. The burning signal detector transmits the local stored signal to the burning controller. The burning controller burns the local stored signal into the memory, so that the memory stores a local data.

Abstract: A conversion circuit includes a main device and a voltage control switching circuit. The voltage control switching circuit includes a first terminal configured to receive an original signal, a second terminal coupled to the control terminal of the main device and configured to transmit a driving signal to drive the main device, and a reference terminal coupled to the second terminal of the main device. A voltage level of the driving signal is generated by the voltage control switching circuit. The voltage control switching circuit further includes a first voltage-control switch. The first drain terminal of the voltage-control switch is coupled to the first terminal. The first source terminal of the voltage-control switch is coupled to the second terminal. The first gate terminal of the voltage-control switch is coupled to the reference terminal.

Abstract: A system (for generating multi-gated power-on control signals) includes: a multi-gated input/out (I/O) interface configured to receive at least first and second gating signals; and a gated power-on control (POC) signals generator configured to generate at least the first and second gating signals for the multi-gated I/O interface, a waveform of the first gating signal being different from a waveform of the second gating signal.

Abstract: An eight-transistor (8T) Static Random-Access Memory (SRAM) cell has four latch transistors, and pairs of n-channel and p-channel pass transistors in parallel to only one pair of bit lines. During read, only the read word line and the n-channel pass transistors are activated, but during a write both the read word line and an extra write word line are activated to turn on all four pass transistors. The cell is powered by VDDM, one threshold above the normal VDD power supply of the read sense and write drivers and interfaces. The bit lines are precharged to VDD but pulled up to VDDM by a latch of cross-coupled p-channel transistors. Any p-channel transistors that connect to the bit lines are driven inactive by VDDM. The read margin is largely decoupled from the write margin by two additional p-channel pass transistors and one extra word line versus a standard 6T cell.

Abstract: An application processor includes a system bus, a host processor and a voice trigger system that are electrically connected to the system bus. The voice trigger system performs a voice trigger operation and issue a trigger event based on a trigger input signal that is provided through a trigger interface. The voice trigger system is secured independently of the host processor. The voice trigger system performs the voice trigger operation based on secured user voice information that is stored in a security region in the secured voice trigger system during a sleep mode in which the system bus and the host processor are disabled.

Abstract: An AESA for SATCOM includes a PCB; a plurality of ICs; an RF feed network for an array; a plurality of patch antennas; a SPI bus for controlling phase shifting of the ICs; phase shifters being operable for selectively introducing a phase shift internal to each of the plurality of ICs such that the radiation pattern resulting from the patch antennas connected to a single IC are steered; and wherein the plurality of ICs are operable to selectively provide either left hand circular polarization, right hand circular polarization, horizontal polarization or vertical polarization.

Abstract: A voltage tolerant interface circuit includes an input terminal and one or more low-voltage transistors for generating an output from the voltage tolerant interface circuit based on a voltage received at the input terminal. The voltage tolerant interface circuit also includes a blocking transistor coupled between a control terminal of at least one low-voltage transistor and the input terminal. In some implementations, the blocking transistor is configured to protect the control terminal of the low-voltage transistor by blocking the voltage received at the input terminal when the voltage exceeds a voltage tolerance of the low-voltage transistor. In other implementations, the low-voltage transistor receives a supply voltage higher than the voltage tolerance of the low-voltage transistor.

Abstract: A system and method for efficiently handling voltage level shifting are contemplated. In various embodiments, a first level shifter receives a first isolate enable signal based on a first power supply voltage and a second isolate enable signal based on a second power supply voltage different from the first power supply voltage. A second level shifter generates the first isolate enable signal based on both the second isolate enable signal and the first power supply voltage. A circuit block generates a data signal based on the first power supply voltage. When it is determined that isolation for the first level shifter is enabled, the first level shifter generates a voltage level on an internal particular node to a particular voltage level based on the first isolate enable signal, and also prevents, using the second isolate enable signal, the data signal from setting a voltage level on the particular node.

Abstract: Embodiments of the present application provide a scan driving circuit, a scan driver and a display device. The scan driving circuit includes a first control module, a second control module and an output module. The output module includes a first switching unit, a second switching unit and a scan driving signal output end. The first switching unit and the second switching unit are connected in parallel and are connected with the scan driving signal output end. A port of the first switching unit is away from the scan driving signal output end to receive a second clock signal. A port of the second switching unit is away from the scan driving signal output end to receive a first reference signal. A function of outputting the scan driving signal by using fewer components is realized with the scan driving circuit according to the embodiments of the present application.

Abstract: A conversion circuit includes a main device, a voltage control switching circuit and a trigger circuit. The trigger circuit includes an output terminal and a sense terminal. The sense terminal is electrically connected to the control terminal of the main device. The voltage control switching circuit includes a first terminal, a second terminal and a control terminal. A first terminal is configured to receive an original signal. A second terminal is connected to a control terminal of the main device, and is configured to transmit a driving signal to drive the main device. A control terminal is connected to the main device and the output terminal. The driving signal has a first voltage level generated by the voltage control switching circuit in response to a voltage level at the control terminal of the voltage control switching circuit.

Abstract: A conversion circuit includes a main device, a voltage control circuit and a trigger circuit. An output terminal of the voltage control circuit is electrically connected to a control terminal of the main device. The voltage control circuit is configured to output a driving signal having a first voltage level to the main device. The trigger circuit comprises an output terminal and a sense terminal. The output terminal of the trigger circuit is electrically connected to the control terminal of the voltage control circuit, and the sense terminal of the trigger circuit is electrically connected to the control terminal of the main device.

Abstract: A half bridge GaN circuit is disclosed. The half bridge GaN circuit includes a first power node having a first power voltage, where the first power voltage is referenced to a switch voltage at the switch node. The half bridge GaN circuit also includes a VMID power node having a VMID power voltage, where the VMID power voltage is referenced to the first power voltage and is less than the first power voltage by a DC voltage. The half bridge GaN circuit also includes a logic circuit, where a negative power terminal of the logic circuit is connected to the VMID node, and where a positive power terminal of the first logic circuit is connected to the first power node, where the logic circuit is configured to generate a logic output voltage, which controls the conductivity of the high side power switch.

Abstract: A battery charger capable of receiving AC power and delivering both AC and DC power to an electric power storage battery in accordance to different embodiments disclosed herein using a rectifier circuit supplying the DC load and absorbing power as a five-level active rectifier with low harmonics on the AC input. In one aspect, the battery charger may have a bidirectional rectifier/inverter converter providing power conversion between a DC source and AC enabling the user to not only charge an electrical vehicle (“EV”) but also convert the energy charged in the EV/battery or solar panel to AC for use.

Abstract: Logic circuitry packages for association with replaceable print apparatus components are disclosed herein. An example logic circuitry package includes logic and a serial data bus interface. The serial data bus interface is to interface with a serial data bus of a print apparatus, and the logic is, in response to a first command sent to the logic circuitry package via the serial data bus connected to the serial data bus interface, to generate a low voltage condition on the serial data bus and to monitor a duration of a time period.

Abstract: A conversion circuit includes a main device including a first terminal, a second terminal and a control terminal, and a voltage control switching circuit including a first terminal configured to receive an first driving signal, a second terminal coupled to the control terminal of the main device and configured to transmit a second driving signal to drive the main device, and a reference terminal coupled to the second terminal of the main device. A current passing through the voltage control switching device is controlled in response to a voltage level of the reference terminal.

Abstract: A level shifter includes a flying capacitor having a first plate and a second plate. The level shifter includes a circuit coupled to the first plate and coupled to the second plate. The circuit is configured to receive a received signal having a logic state using a first voltage domain and configured to generate a symmetrical output signal having the logic state using a second voltage domain based on charge stored by the flying capacitor. The level shifter has a propagation delay from the received signal to the symmetrical output signal of less than one nanosecond with negligible duty cycle distortion.

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include level shifting circuitry for translating an input signal from a first voltage domain to an output signal for a second voltage domain. The integrated circuit may include input logic circuitry for receiving multiple input signals and providing an inverted input signal to the level shifting circuitry based on the multiple input signals. The integrated circuit may include bypass switching circuitry for activating and deactivating the level shifting circuitry based on a bypass control signal and at least one of the multiple input signals.

Abstract: Various implementations described herein refer to an integrated circuit having level shifting circuitry and bypass switching circuitry. The level shifting circuitry is arranged for translating an input signal from a first voltage domain to an output signal for a second voltage domain. The bypass switching circuitry is arranged for activating and deactivating the level shifting circuitry based on a bypass control signal.

Abstract: Various transmission systems may benefit from techniques to improve the quality of the transmission. For example, certain full duplex transmission systems may include a virtual hybrid coupler. A circuit can include a first feedback resistor. The circuit can also include a second feedback resistor coupled to the first feedback resistor. The circuit can further include a first set of M transistors coupled to the first feedback resistor. The circuit can additionally include a second set of N transistors coupled to the second feedback resistor and to the first set of M transistors. The circuit can be configured to cancel a transmitted signal at a receiver input based on a ratio of resistance values of the first feedback resistor and the second feedback resistor, and based on a ratio of M to N.

Abstract: A level shifter according to some embodiments is disclosed. In some embodiments, a level shifter includes a middle-of-the-line (MOL) capacitor; and a circuit including at least one thin-film transistor coupled to the MOL capacitor, wherein an input voltage provided to the MOL capacitor is split between the MOL capacitor and the circuit. The MOL capacitor can be formed with a contact strip adjacent to a gate structure. A method of forming a level shifter using thin-oxide technologies includes forming a middle-of-the-line (MOL) capacitor; forming a circuit with one or more thin-film transistors; and coupling the MOL capacitor to the circuit such that an input voltage provided at the MOL capacitor is split between the MOL capacitor and the circuit.

Abstract: Level-shifter circuits and methods of using the same are provided. A level-shifter circuit includes a latch unit and a level-shifting unit. The latch unit is configured to generate a latch signal for storing a logic state of a first digital signal in a first power supply domain. The level-shifting unit is configured to shift a voltage of the latch signal to output a second digital signal in a second power supply domain. The latch unit and the level-shifting unit are powered by a power supply voltage in the second power supply domain.

Abstract: Between a power supply potential and a reference potential, a first PMOS transistor and a first NMOS transistor are connected in series via an inverting output node and a second PMOS transistor and a second NMOS transistor are connected in series via a non-inverting output node. A third NMOS transistor is connected in parallel to the first NMOS transistor and a fourth NMOS transistor is connected in parallel to the second NMOS transistor. A gate of the first PMOS transistor and a gate of the third NMOS transistor are connected to the non-inverting output node and a gate of the second PMOS transistor and a gate of the fourth NMOS transistor are connected to the inverting output node. The first and second NMOS transistors receive a non-inverted signal and an inverted signal of an input signal at their gates, respectively.

Abstract: The technology described herein is generally directed towards a self-bootstrap integrated gate driver circuit with high driving speed, enhanced driving capability and rail-to-rail output. A capacitor and diode are used with a first inverter coupled to a control signal input terminal, a second inverter coupled to the first inverter, a push-pull circuit comprising a pull-up transistor and a pull-down transistor and a power device comprising a power device transistor with a gate. Control signal input at one state controls the first inverter to a first output state, turns on the pull-down transistor to discharge the gate of the power device transistor, turns off the power device and charges the capacitor through the diode. The control signal input in another state controls the first inverter to a second output state, turns off the pull-down transistor and turns on the pull-up transistor via the capacitor to turn on the power device.

Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and a plurality of logic cells within at least one of the PLBs, where each logic cell includes a four input lookup table (4-LUT) configured to provide a 4-LUT output signal to associated carry logic. Each logic cell is configurable according to at least two selectable operational modes including a logic function output mode and a ripple arithmetic output mode, and at least three of the 4-LUT inputs are interchangeable when a selected operational mode comprises the ripple arithmetic output mode.

Abstract: A resistor array made of a semiconductor includes a plurality of resistor groups and a common line that electrically connects the M-th resistors of the plurality of resistor groups. Each resistor group includes first to M-th resistors connected in series, M being an integer of 2 or greater, and at least one short-circuit line, each short-circuiting at least one, but not all, of the M resistors.

Abstract: Provided is a level shift circuit capable of converting a negative voltage level as well as a positive voltage level. The level shift circuit includes a switching transistor between an input transistor and a load, the switching transistor including a gate connected to a voltage source, and an input negative voltage level is converted into a second negative voltage level based on a voltage of the voltage source and a threshold voltage of the switching transistor.

Abstract: A negative power supply control circuit which controls a negative voltage regulator circuit based on a positive voltage control signal, the negative power supply control circuit including: a control signal input terminal a negative voltage input terminal; a negative voltage input control signal output terminal; a voltage current conversation circuit; a first current source; and a first clamp circuit, wherein the first clamp circuit clamps a voltage at a first intermediate point between the first clamp circuit and the first current source by limiting a current flowing in the first clamp circuit according to the voltage at the first intermediate point in a period when a current flows in the voltage current conversation circuit, and the negative voltage controls signal is generated based on a voltage or a current in a current path through the voltage current conversation circuit, the first clamp circuit and the first current source.

Abstract: A level shifting apparatus includes a first inverter configured to receive an input signal and a second inverter capacitively coupled with an output of the first inverter, the second inverter being configured to output an output signal. A transmission gate is configured to feed back the output signal to an input of the second inverter, wherein the transmission gate is configured to selectively interrupt feedback of the output signal to the input of the second inverter.

Abstract: A system, a method, and a computer program product for visualizing an outcome of dependency checks and resolution of errors in various software applications are disclosed. At least one first configuration setting in a plurality of configuration settings for a software application is selected. At least one first graphical notification identifying an error preventing execution of the first configuration setting and another configuration setting in the plurality of configuration settings are generated and displayed. The first graphical notification is displayed on a user interface adjacent to a graphical location on the user interface associated with another configuration setting. At least one solution to the error is executed based on the at generated first graphical notification. An absence of errors preventing execution of the plurality of configuration settings is determined and the plurality of configuration settings is executed.

Abstract: A data driver and a display device using the same are disclosed. The display device includes a display panel having a display area displaying an image, signal lines including data lines, first power lines, and sensing lines connected to the display panel, and a data driver connected to the signal lines. The data driver includes first channel groups outputting a data signal, second channel groups outputting and sensing a sensing voltage, and third channel groups outputting a high potential voltage. The first channel groups and the third channel groups are defined as a first output unit, and the second channel groups are defined as a second output unit. The second channel groups are successively disposed every M channels, where M is an integer equal to or greater than 2.

Abstract: An anti-floating circuit including a first pull-high circuit, a first pull-low circuit and a first control circuit is provided. The first pull-high circuit includes a first P-type transistor and a second P-type transistor and is coupled to a first power terminal. The first pull-low circuit includes a first N-type transistor and a second N-type transistor and is coupled to a second power terminal. A first path is between the first P-type transistor and the first N-type transistor. A second path is between the second P-type transistor and the second N-type transistor. A third path is between the first P-type transistor and the second power terminal. In the first mode, the control circuit turns on the first and second paths and turns off the third path. In the second mode, the control circuit turns off the first and second paths and turns on the third path.

Abstract: Various implementations described herein are directed to a circuit for translating an input signal from a source voltage domain to an output signal for a destination voltage domain that is is different than the source voltage domain. The circuit may include a level shifting portion configured to operate with a supply voltage that exceeds a stressing threshold of one or more components within the circuit. The level shifting portion may be configured to generate the output signal for the destination voltage domain based on the input signal and a power management signal. The circuit may include an isolating portion configured to isolate the one or more components from the supply voltage during activation and deactivation of the circuit based on the power management signal.

Abstract: This document discusses, among other things, a signal receiving circuit, configured to receive an input voltage signal. The signal receiving circuit can comprise an input voltage regulating circuit and a comparing circuit. The input voltage regulating circuit can carry out a waveform pre-regulation for the input voltage signal to obtain a first voltage signal, and the comparing circuit can compare the first voltage signal with a second voltage signal, and output a comparison voltage signal having a pulse width that satisfies a first predetermined condition indicative that the input voltage signal is correctly identifiable. The present document further discusses a signal detecting circuit and a signal receiving method.

Abstract: The present invention relates to a level shifter including: a first inverter applied with a first voltage and a second voltage of different polarities and operated depending on an input voltage to output a first inverting output signal; a second inverter applied with the first voltage and the second voltage and operated depending on the first inverting output signal to output a second inverting output signal having an opposite polarity to that of the first inverting output signal; a driver applied with a third voltage and a fourth voltage, including a first load transistor having the first inverting output signal as a gate input and a second load transistor having a fifth voltage as the gate input, and outputting an output voltage having an increased level with respect to the input voltage; and a bootstrap capacitor positioned between an output terminal of the second inverter and a gate electrode of the second load transistor to help the fifth voltage to be bootstrapped depending on the second inverting outpu

Abstract: A display device includes: a display panel including pixels arranged in a matrix shape; and a source driver to apply data voltages to the pixels. The source driver includes: a shift controller to shift a sampling control signal; a latch array to sample digital video data in response to the sampling control signal shifted by the shift controller; a digital-to-analog converter array to convert the digital video data from the latch array into data voltages by decoding the digital video data and combination-outputting gamma compensation voltages on the basis of a gray value of the decoded data; an output buffer array to output the data voltages from the digital-to-analog converter array; and a bias controller to adjust a bias current, which is applied to the output buffer array, according to delay and stable intervals of the data voltage.