Abstract: Methods, systems, and devices for postamble for multi-level signal modulation are described. One or more channels of a bus may be driven with a multi-level signal having at least two (2) distinct signal levels. After driving the bus with the multi-level signal, at least one (1) of the channels may be terminated. In some examples, the channel may be terminated to a relatively high signal level. Before termination, the channel may be driven with a postamble having an intermediate signal level. Driving the channel to an intermediate signal level before terminating the channel (e.g., to a high signal level) may avoid maximum transitions of the signal. For example, transitions between a lowest potential signal level and the high signal level (e.g., the termination level) may be avoided.

Abstract: A Controller Area Network (CAN) system, method, and circuit are provided with a dual mode bus line termination circuit connected between signal lines of a serial bus and optimized for both differential and single-ended communication modes over the serial bus, where the dual mode bus line termination circuit includes first and second resistance termination paths connected in parallel between first and second bus wires of the serial bus to provide an odd mode termination impedance (RODD) that matches an impedance of the serial bus when operating in the differential communication mode, and to also provide an even mode termination impedance (REVEN) that matches an impedance of the serial bus when operating in the single-ended communication mode.

Abstract: A post-driver with low voltage operation and electrostatic discharge protection. In one embodiment, a post-driver structure includes a drive unit including a pull-up driver and a pull-down driver, a pad connected to an external resistance, and an output node connected between the pull-up driver and the pull-down driver, the output node configured to connect to a comparator for impedance calibration of the drive unit. The post-driver structure also includes an operational amplifier connected to a first transistor and the pad in a closed loop configuration, the operational amplifier further connected to a second transistor to form a current mirror circuit between the operational amplifier and the drive unit, wherein the current mirror circuit replicates a voltage at the pad with a voltage at the output node for the impedance calibration.

Abstract: One example discloses a signal driver circuit, including: an input configured to receive an input signal; an output configured to transmit an output signal; a low drop-out voltage regulator (LDO) having a regulated voltage output; a set of voltage-modulated amplifiers having a first input coupled to the regulated voltage output, and a second input configured to receive the input signal; wherein the voltage-modulated amplifier is configured to amplify the input signal and transmit an amplified input signal on the output of the signal driver circuit; a de-emphasis controller, including a set of de-emphasis levels; wherein the de-emphasis controller is configured to selectively switch-on a first subset of the set of voltage-modulated amplifiers and switch-off a second subset of the set of voltage-modulated amplifiers based on the de-emphasis levels.

Abstract: A memory device and a method of operating the same are disclosed. In one aspect, the memory device includes a plurality of memory arrays and a controller including a plurality of buffers including a first buffer connected to a first memory array and a second buffer connected to a second memory array. The first and second memory arrays are disposed on opposing sides of the controller. The memory device can include a first wire extending in a first direction and connected to the first buffer, a second wire extending in the first direction and connected to the second buffer, and a third wire connected to the first and second wires and extending in a second direction that is substantially perpendicular to the first direction. The third wire can be electrically connected to the controller, and respective lengths of the first wire and the second wire are substantially the same.

Abstract: In examples, a system includes a differential input device having a first input and a second input. The system includes a window generator configured to output, at a first output, a first voltage above a reference voltage and a second voltage, at a second output, below the reference voltage. The system includes a multiplexer coupled to the first output and the second output, the multiplexer configured to receive the first voltage, the second voltage, and an input voltage. The system includes a selector coupled to the multiplexer and configured to select the first voltage, the second voltage, or the input voltage based on a value of the input voltage, where the selector is configured to cause the multiplexer to provide the selected voltage to the first input of the differential input device, where a voltage source provides the reference voltage to the second input of the differential input device.

Abstract: Methods and systems for selecting voltage for a substrate connection of a bypass switch include a bulk voltage generation circuit coupled externally to the regulator. The bulk voltage generation circuit is configured to control selection of a voltage from among an Input/Output (I/O) supply voltage and a core supply voltage for a substrate connection of a bypass switch of the regulator. The bulk voltage generation circuit is configured to select the voltage for the substrate connection of the bypass switch based on a mode of operation of the regulator and at least one of a presence or an arrival sequence of the I/O supply voltage and the core supply voltage.

Abstract: A signal processing apparatus includes a signal processing circuit configured to process a signal obtained from a voltage bus, a high voltage circuit configured to withstand a voltage stress when a high voltage is applied to the voltage bus, and a bypass circuit configured to bypass the high voltage circuit when a low voltage is applied to the voltage bus.

Abstract: Provided is a storage system including a decoupling device having a plurality of unit capacitors. The storage system includes a storage device, a control device, and a decoupling device disposed on a circuit substrate. The storage device is configured to receive and store data from the control device. The control device is configured to generate an inner voltage. The decoupling device is connected to the control device and decouples the inner voltage. The decoupling device includes a plurality of unit capacitors constituting a plurality of decoupling capacitors. Each of the unit capacitors includes a plurality of capacitor elements, a first terminal, and a second terminal. Some of the unit capacitors are selectively connected with each other to constitute the decoupling capacitors having various capacitances.

Abstract: A single wire digital communication system for use with an ultrasonic surgical instrument and an ultrasonic surgical instrument including a single wire digital communication system. The single wire digital communication system includes first transmitter logic buffer and first receiver logic buffer operably coupled to a first single wire device via a first single wire communication bus. The single wire digital communication system also includes a first differential transceiver operational amplifier operably coupled to the first transmitter logic buffer via a first transmitter signal line and operably coupled to the first receiver logic buffer via a first receiver signal line. A second differential transceiver operational amplifier is operably coupled to the first differential transceiver operational amplifier via at least one differential bus. A second single wire device is operably coupled to the differential bus and configured to communicate with the first single wire device.

Abstract: A data output buffer includes a first driver configured to drive a data input/output (I/O) pad according to an input signal and allow data drivability to be controlled according to an impedance calibration code and a second driver configured to perform a de-emphasis operation on the data I/O pad and allow de-emphasis drivability to be controlled according to the impedance calibration code.

Abstract: A playback device includes a speaker, a controller, a first switch circuit, and a second switch circuit. The speaker has a first terminal and a second terminal. The controller is configured to output a first audio signal and a second audio signal. The controller is coupled to the first terminal of the speaker, and is configured to transmit the first audio signal to the speaker. The second switch circuit is coupled between the second terminal of the speaker and the controller, and is coupled to the first switch circuit. The second switch circuit is configured to transmit the second audio signal from the controller to the speaker when the first switch circuit is turned on.

Abstract: The interface circuit includes a first transistor, a second transistor, a first switch, a first logic circuit and a second logic circuit. The first transistor is controlled by a enable signal. The second transistor is controlled by a first control signal. The first switch is coupled between a second end of the first transistor and the output end of the interface circuit, wherein the first switch is controlled by a second control signal. The first logic circuit generates the first control signal according to the enable signal and at least one indication signal. The second logic circuit generates the second control signal according to the first control signal and the enable signal.

Abstract: A lower-power driving display device and a driving method. The driving method of the display device includes dividing the plurality of output buffers of the data driver into a plurality of output buffer groups, each of the plurality of output buffers being configured to apply the data voltage to each of the plurality of data lines connected with the display panel, and determining the magnitude of a bias current supplied to an output buffer on the basis of a pattern of a data voltage output by the output buffer which belongs to each of the plurality of divided output buffer groups.

Abstract: A device may include a ZQ calibration circuit. The ZQ calibration circuit may include a first register configured to store a first impedance code generated responsive to a ZQ calibration command. The ZQ calibration circuit may also include a second register configured to store a shift value. Further, the ZQ calibration circuit may include a compute block configured to generate a second impedance code based on the first impedance code and the shift value. Systems and related methods of operation are also described.

Abstract: A circuit includes first through fourth transistors and a device. The first transistor has a control input and first and second current terminals. The control input provides a first input to the circuit. The second transistor has a control input and first and second current terminals. The control input provides a second input to the circuit. The third transistor has a control input and first and second current terminals. The fourth transistor has a control input and first and second current terminals. The second current terminal of the fourth transistor is coupled to the second current terminal of the third transistor, and the control input of the fourth transistor is coupled to the first current terminals of the first and second transistors. The device is configured to provide a fixed voltage to the control input of the third transistor.

Abstract: Memories for receiving or transmitting voltage signals might include an input or output buffer including a first stage having first and second inputs and configured to generate a current sink and source at its first and second outputs responsive to a voltage difference between its first and second inputs, and a second stage having a first input connected to the first output of the first stage, a second input connected to the second output of the first stage, a first voltage signal node connected to its first input through a first resistance, and a second voltage signal node connected to its second input through a second resistance, wherein a first inverter is connected in parallel with the first resistance, a second inverter is connected in parallel with the second resistance, and a pair of cross-coupled inverters are connected between the first voltage signal node and the second voltage signal node.

Abstract: A power amplifier circuit includes a first power supply terminal electrically connected to a first power amplifier; a second power supply terminal electrically connected to a second power amplifier subsequent to the first power amplifier; a first external power supply line configured to electrically connect a power supply circuit configured to output a power supply potential corresponding to an amplitude level of a high-frequency input signal and the first power supply terminal; and a second external power supply line configured to electrically connect the power supply circuit and the second power supply terminal. An inductance value of the first external power supply line is higher than an inductance value of the second external power supply line.

Abstract: The energy storage system includes battery cells, a subrack, a backplane, and a battery management system BMS. The subrack reserves a plurality of battery cell slots, the battery cells are connected to the backplane through the battery cell slots. The backplane is installed in the subrack, a first power terminal is reserved at a position corresponding to the battery cell slot on the backplane, and a plug-in power terminal is formed by a second power terminal of the battery cell together with the first power terminal. A power circuit, a sampling circuit, and an equalizer circuit are integrated into the backplane, and the power circuit, the sampling circuit, and the equalizer circuit are connected after the second power terminal is plugged and docked with the first power terminal. The BMS is connected to the backplane for managing the energy storage system.

Abstract: Disclosed is a method for deadtime optimization in a half-bridge switch or full-bridge switch wherein high-side and low-side switches comprise GaN transistors; a circuit for implementing the method; and a power switching system comprising a GaN half-bridge or a GaN full-bridge and a deadtime optimization system. The circuit comprises a drain current bump filter for generating a current charge output; and circuit elements for comparing the current charge output to a reference current charge Coss and generating a deadtime adjust signal. The deadtime adjust signal may be used to adjust deadtime to reduce or minimize deadtime, and deadtime losses, while avoiding cross-conduction.

Abstract: A chip package includes an interposer comprising a silicon substrate, multiple metal vias passing through the silicon substrate, a first interconnection metal layer over the silicon substrate, a second interconnection metal layer over the silicon substrate, and an insulating dielectric layer over the silicon substrate and between the first and second interconnection metal layers; a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip over the interposer; multiple first metal bumps between the interposer and the FPGA IC chip; a first underfill between the interposer and the FPGA IC chip, wherein the first underfill encloses the first metal bumps; a non-volatile memory (NVM) IC chip over the interposer; multiple second metal bumps between the interposer and the NVM IC chip; and a second underfill between the interposer and the NVM IC chip, wherein the second underfill encloses the second metal bumps.

Abstract: A display control system includes a plurality of driver circuits connected in series. A driver circuit among the plurality of driver circuits includes a receiver, a duty cycle correction circuit and a transmitter. The receiver is configured to receive a first signal from a previous driver circuit among the plurality of driver circuits. The duty cycle correction circuit, coupled to the receiver, is configured to adjust a duty cycle of the first signal to generate a second signal. The transmitter, coupled to the duty cycle correction circuit, is configured to transmit the second signal to a next driver circuit among the plurality of driver circuits.

Abstract: In examples, a system includes a differential input device having a first input and a second input. The system includes a window generator configured to output, at a first output, a first voltage above a reference voltage and a second voltage, at a second output, below the reference voltage. The system includes a multiplexer coupled to the first output and the second output, the multiplexer configured to receive the first voltage, the second voltage, and an input voltage. The system includes a selector coupled to the multiplexer and configured to select the first voltage, the second voltage, or the input voltage based on a value of the input voltage, where the selector is configured to cause the multiplexer to provide the selected voltage to the first input of the differential input device, where a voltage source provides the reference voltage to the second input of the differential input device.

Abstract: A single wire digital communication system for use with an ultrasonic surgical instrument and an ultrasonic surgical instrument including a single wire digital communication system. The single wire digital communication system includes first transmitter logic buffer and first receiver logic buffer operably coupled to a first single wire device via a first single wire communication bus. The single wire digital communication system also includes a first differential transceiver operational amplifier operably coupled to the first transmitter logic buffer via a first transmitter signal line and operably coupled to the first receiver logic buffer via a first receiver signal line. A second differential transceiver operational amplifier is operably coupled to the first differential transceiver operational amplifier via at least one differential bus. A second single wire device is operably coupled to the differential bus and configured to communicate with the first single wire device.

Abstract: Apparatuses and methods for calibrating adjustable impedances of a semiconductor device are disclosed in the present application. An example apparatus includes a register configured to store impedance calibration information and further includes programmable termination resistances having a programmable impedance. The example apparatus further includes an impedance calibration circuit configured to perform a calibration operation to determine calibration parameters for setting the programmable impedance of the programmable termination resistances. The impedance calibration circuit is further configured to program the impedance calibration information in the register related to the calibration operation.

Abstract: A low voltage differential signal driver includes an output driver including an N-channel source follower, a P-channel source follower, and a plurality of differential switching circuits, a plurality of high-potential output control circuits to control a terminal of the N-channel source follower of the output driver to make a high-potential output of the differential output from the output driver have a prescribed value, a plurality of low-potential output control circuits to control a terminal of the P-channel source follower of the output driver to make a low-potential output of the differential output from the output driver have a prescribed value, a high-potential generation circuit used in common for the plurality of high-potential output control circuits, and a low-potential generation circuit used in common for the plurality of low-potential output control circuits. The output driver outputs a differential output, and one of the plurality of high-potential output control circuits.

Abstract: A termination for a high-frequency transmission line includes a first resistor that has a first terminal coupled to a first end of a transmission line and a second terminal coupled to a first input/output pad, and a second resistor that has a first terminal coupled to the first input/output pad. The first resistor and the second resistor may provide a combined resistance that matches a nominal value of a characteristic impedance of the transmission line. The apparatus may include a third resistor having a first terminal coupled to a second end of a transmission line, and a second terminal coupled to a second input/output pad, and a fourth resistor having a first terminal coupled to the second input/output pad. The third resistor and the fourth resistor may provide a combined resistance that matches the nominal value of the characteristic impedance of the transmission line.

Abstract: A semiconductor system includes a semiconductor apparatus and an external apparatus. The semiconductor apparatus includes a calibration code generating circuit, a code shifting circuit, and a main driver. The calibration code generating circuit performs a calibration operation to generate a calibration code. The code shifting circuit changes, based on a shifting control signal, a value of the calibration code. A resistance value of the main driver may be set on the basis of the calibration code and a shifted calibration code. The external apparatus generates the shifting control signal based on the resistance value of the main driver.

Abstract: A signal transmitting circuit and a signal receiving circuit for serial communication, and an electronic device are provided. The signal transmitting circuit includes a control module, a first transmitter, a second transmitter, a first differential pin, and a second differential pin, wherein the control module is configured to control the first transmitter to output a first signal via the first differential pin, and control the second transmitter to output a second signal via the second differential pin to record target information with a target signal after differentiating between the first signal and the second signal; and wherein if the target information includes data information and instant information, the data information is recorded in the target signal with a third signal with a first frequency while recording the instant information with a fourth signal with a second frequency, the first frequency is different from the second frequency.

Abstract: A first wafer of semiconductor material has a surface. A second wafer of semiconductor material includes a substrate and a structural layer on the substrate. The structural layer integrates a detector device for detecting electromagnetic radiation. The structural layer of the second wafer is coupled to the surface of the first wafer. The substrate of the second wafer is shaped to form a stator, a rotor, and a mobile mass of a micromirror. The stator and the rotor form an assembly for capacitively driving the mobile mass.

Abstract: A data transmission method, a timing controller, a source driver and a display device, and a data transmission technology. The method includes: a timing controller generating an idle signal, which may be a random signal with a clock edge; and the timing controller sending the idle signal to a source driver, wherein the source driver may judge whether a clock signal of the source driver is synchronous with that of the timing controller according to the idle signal.

Abstract: According to one embodiment, in a first differential amplifier circuit of a semiconductor device, a first transistor receives an input signal at the gate. A second transistor forms a differential pair with the first transistor. The second transistor receives a reference signal at the gate. A third transistor is connected in series with the first transistor. A fourth transistor is connected in series with the second transistor. A fifth transistor is disposed on the output side. The fifth transistor forms a first current mirror circuit with the fourth transistor. A sixth transistor is connected to the drain of the second transistor in parallel with the fourth transistor. The sixth transistor forms a second current mirror circuit with the fifth transistor. A first discharge circuit is connected to the source of the sixth transistor.

Abstract: A semiconductor storage device includes a first input driver configured to receive a first signal from a memory controller, a second input driver configured to receive a chip enable signal from the memory controller, and a first control circuit. The first control circuit is configured to set the semiconductor storage device in an enabled state or a disabled state depending on whether or not the first signal which is received during a time period that starts with assertion of the chip enable signal and is prior to receipt of a command sequence, corresponds to a first chip address.

Abstract: The system generally includes a crosspoint switch in a local data collection system having multiple inputs and multiple outputs including a first input connected to a first sensor and a second input connected to a second sensor. The multiple outputs include a first output and a second output configured to be switchable between a condition in which the first output is configured to switch between delivery of a first sensor signal and a second sensor signal and a condition in which there is simultaneous delivery of the first sensor signal and the second sensor signal. Each of multiple inputs is configured to be individually assigned to any of the multiple outputs. The local data collection system includes multiple data acquisition units each having an onboard card set configured to store calibration information and maintenance history. The local data collection system is configured to manage data collection bands.

Abstract: Embodiments include a power conversion circuit comprising first and second semiconductor switches, and a drive circuit configured to create a period of operational overlap for the first and second switches by setting a gate voltage of the first switch to an intermediate value above a threshold voltage of the first switch, during turn-on and turn-off operations of the second switch. Embodiments also include a method of operating first and second semiconductor devices, comprising: reducing a gate voltage of the first device to an intermediate value above a threshold voltage while the second device is off; turning off the first device after the second device is on; increasing the gate voltage of the first device to the intermediate value while the second device is on; and fully turning on the first device after the second device is off.

Abstract: A serial bus repeater includes a port circuit and a low power state detection circuit. The port circuit is configured to communicate via a serial bus. The low power state detection circuit includes a power state transaction identification circuit and a bus state identification circuit. The power state transaction identification circuit is configured to identify a power state transaction on the serial bus. The power state transaction is indicative of entering a reduced power state. The bus state identification circuit is configured to identify a value of termination resistance on the serial bus that is indicative of entering the reduced power state.

Abstract: A rectifying circuit includes a HEMT, a diode connected in antiparallel to the HEMT; and a gate drive circuit, wherein the gate drive circuit includes a gate drive power supply, a first transistor, a second transistor configured to turn on in a complementary manner with the first transistor, a first capacitor including an input capacitance of the HEMT, a second capacitor provided on a pathway configured to charge the input capacitance, a first resistor connected in parallel to the first capacitor, and a second resistor connected in parallel to the second capacitor, the gate drive circuit is configured to control a gate voltage of the HEMT to make the gate voltage lower than a source voltage of the HEMT when the HEMT is turned off.

Abstract: Systems and methods that may be implemented to provide on-board trace impedance testing for a system level board of an information handling system. A printed circuit board (PCB) of the system level board may include built-in test trace circuitry that may be used to measure board trace impedance so that the trace impedance of a fully assembled system level board may be tested and verified for compliance with trace impedance specification, and without requiring any disassembly of the board.

Abstract: In certain aspects, a delay circuit includes a multiplexer, a first delay path coupled between an input of the delay circuit and a first input of the multiplexer, and a second delay path coupled between the input of the delay circuit and a second input of the multiplexer. The first delay path includes a first delay device, and the second delay path includes a first inverter, a second delay device, and a second inverter. In other aspects, a delay circuit includes a latch including a first input, a second input, and an output. The first input of the latch is coupled to an input of the delay circuit. The delay circuit also includes a delay path coupled between the input of the delay circuit and the second input of the latch, wherein the delay path includes a pulse generator and a delay device.

Abstract: Disclosed is a method for driving a transistor device and an electronic circuit. The method includes: in an on-state of the transistor device (1), reducing a drive voltage (VGS) of the transistor device (1) from a maximum voltage level (VMAX) to an intermediate voltage level (VINT) that is higher than a threshold voltage level (VTH) of the transistor device (1); maintaining the intermediate voltage level (VINT) for a predefined time period (TINT); and reducing the drive voltage (VGS) to below the threshold voltage level (VTH) after the predefined time period (TINT) to switch the transistor device to an off-state.

Abstract: A duty-cycle adjustment circuit receives a differential pair of input signals and generates an output signal based on the differential pair. The duty-cycle adjustment circuit drives the output signal to a logic-high state based on transitions of a first polarity in a first input signal of the differential pair, and drives the output signal to a logic-low state based on transitions of the first polarity in a second input signal of the differential pair. For example, rising-edge transitions of the output signal may be aligned with rising-edge transitions of the first input signal, and falling-edge transitions of the output signal may be aligned with rising-edge transitions of the second input signal. Alternatively, rising-edge transitions of the output signal may be aligned with falling-edge transitions of the first input signal, and falling-edge transitions of the output signal may be aligned with falling-edge transitions of the second input signal.

Abstract: Devices and methods for finite impulse response (FIR) feed forward equalization (FFE) at a transmitter are provided. A voltage-mode driver circuit has a main driver and an equalization driver. The main driver drives the digital output signal based on a received digital input signal. The equalization function of the equalization driver is enabled or disabled for a short duration of time to provide at least one of FIR equalization and pre-emphasis to the digital output signal. Pre-emphasis is effected by enabling a low-resistance path of the equalization driver based on the digital input signal such that, when the low-resistance path is enabled, it reduces the transmission resistance for a short period of time.

Abstract: A radio frequency switch includes a control buffer circuit to generate a first gate voltage and a first body voltage; and a switching circuit to switch at least one signal path in response to the first gate voltage and the first body voltage. The control buffer circuit includes an off voltage detection circuit to detect whether the off voltage is a negative voltage or a ground voltage and output a voltage detection signal, a first gate buffer circuit to output a first gate voltage having a voltage level based on the voltage detection signal and the band selection signal, and a first body buffer circuit to output a first body voltage having a voltage level based on the voltage detection signal, the band selection signal, and the mode signal.

Abstract: A driver for driving a power transistor, the driver having: a first transistor, and a second transistor; wherein (1) when the first transistor is turned on, the second transistor is simultaneously turned on, and wherein after the second transistor remains on for a first time period, the second transistor is turned off for a second time period during when a switching voltage at a second terminal of the power transistor is rising, and the second transistor is turned on after the second time period is over; and (2) when the first transistor is turned off, the second transistor is simultaneously turned off.

Abstract: Methods, systems, and apparatus to increase common-mode transient immunity in isolation devices is disclosed. An example apparatus includes a current mirror including an input terminal and an output terminal; a transistor including a gate terminal, a first current terminal, and a second current terminal, the gate terminal coupled to a reference voltage terminal, the first current terminal coupled to the input terminal of the current mirror, and the second current terminal coupled to an input node; a buffer including an input terminal and an output terminal, the input terminal of the buffer coupled to the output terminal of the current mirror; and a logic gate including an input terminal and an output terminal, the input terminal of the logic gate coupled to the output terminal of the buffer.

Abstract: A first method includes determining a total length of pending packets for a network link, determining a currently preferred power mode for the network link based on the total length of pending packets for the network link, and changing a current power mode for the network link to the currently preferred power mode. A corresponding apparatus is also disclosed herein. A second method includes determining a utilization for a network link, determining a currently preferred power mode for the network link based on the utilization for the network link, and changing a current power mode for the network link to the currently preferred power mode. A corresponding apparatus is also disclosed herein.

Abstract: A method and apparatus in a receiver to determine if a high speed communication link is in an idle mode or in an active mode. Signals during the idle mode are of lower amplitude and lower frequency compared to amplitude and frequency in the active mode. A signal detector in the receiver determines if the high speed communication link has transitioned from idle mode to active mode and, if so, wakes up high power circuitry in the receiver to receive data.

Abstract: Turn-on and turn-off of a semiconductor device are controlled through control of a gate voltage in accordance with a driving control signal. At a first time after a start of a Miller period of a gate voltage in driving a gate of the semiconductor device in accordance with the driving control signal, a driving signal is changed from “1” to “0” to thereby make a gate driving ability temporarily lower than the gate driving ability during a period from a starting time of the turn-on operation to the first time. Further, at a second time corresponding to an end of the Miller period, the driving signal is changed from “0” to “1” to thereby increase the gate driving ability.

Abstract: Methods and systems of reducing a substrate noise in a charge pump having a flying capacitor are provided. An input node of the flying capacitor is pre-charged at a first slew rate. The input node of the flying capacitor is charged at a second slew rate that is faster than the first slew rate. The input node of the flying capacitor is pre-discharged at a third slew rate. The input node of the flying capacitor is discharged at a fourth slew rate that is faster than the first slew rate.

Abstract: Disclosed herein is an electronic device including an IO node, with a receiver coupled to receive input from the IO node. A transmitter driver has a first n-channel DMOS with a source coupled to the IO node. A pass gate circuit decouples the IO node from the receiver based upon presence of a negative voltage at the IO node and couples the IO node to the receiver based upon lack of presence of the negative voltage at the IO node. A transmit protection circuit applies the negative voltage from the IO node to the gate and bulk of the first n-channel DMOS based upon the presence of the negative voltage at the IO node.