Abstract: Apparatuses and methods of differential driving of adjacent electrodes for low electromagnetic interference (EMI) for scanning a touch panel are described. One apparatus generates an in-phase drive signal and an opposite-phase drive signal and applies, at a substantially same time, the in-phase drive signal to a first transmitter electrode and the opposite-phase drive signal to a second transmitter electrode adjacent to the first transmitter electrode. The apparatus receives a first sense signal from a first receiver electrode and a second sense signal from a second receiver electrode adjacent to the first receiver electrode. The apparatus combines the first sense signal and the second sense signal to obtain a third sense signal. The third sense signal represents a first self capacitance associated with the first receiver electrode. The apparatus detects a presence of an object on a touch panel using at least the first self capacitance.

Abstract: Various NLTL frequency comb generator embodiments are disclosed for broadband impedance matching to generate an output signal comprising broadband harmonics of an input signal. The NLTL frequency comb generator comprises a plurality of segments cascaded in series, with each segment comprising a series inductor and a non-linear shunt capacitor. The non-linear shunt capacitor may couple to corresponding series inductors in the same polarity. A broadband biasing circuit feeds a DC bias or DC ground to the non-linear shunt capacitors for broadband input and output impedance matching. The broadband biasing circuit may be a low pass filter to prevent RF signal from leaking through the biasing circuit. The NLTL frequency comb generator, the broadband biasing circuit, and an output DC blocking capacitor may be integrated in a single chip in a compact packaging to achieve a broadband input/output impedance matching without relying on external lumped matching components.

Abstract: A control signal generator includes an error amplifier, a first comparator, a second comparator, a logic circuit and a pulse generator. The error amplifier has a first output, a first input, a second input and a first snooze input. The first comparator has a second output, a third input and a fourth input. The third input is coupled to the first output. The second comparator has a third output, a fifth input, a sixth input and a second snooze input. The fifth input is coupled to the third input. The logic circuit has a fourth output and logic circuit inputs, including a first logic circuit input coupled to the second output. The pulse generator has a fifth output and a seventh input. The seventh input is coupled to the fourth output. A snooze mode controller has a sixth output coupled to the first snooze input and the second snooze input.

Abstract: A semiconductor device 1a includes: a first external terminal 31 to which a first voltage is to be applied; a second external terminal 32 to which a second voltage is to be applied; a third external terminal 33; first wiring 17 connected to the first external terminal 31; second wiring 18 connected to the second external terminal 32; an internal block circuit 11 connected to the first wiring 17; a first resistor 12 and a transistor 14 serially connected between the first wiring 17 and the second wiring 18; and a second resistor 13 connected between the first wiring 17 and the second wiring 18. The transistor 14 turns on or off based on a test signal fed from the third external terminal 33. This configuration enables product identification using a resistance value, even if a predetermined resistance value cannot be changed.

Abstract: In one embodiment, a device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a receiver configured to receive a data stream from a remote clock source and recover a remote clock from the data stream, and a controller configured to find a clock differential between the local clock and the remote clock identified as a master dock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential between the local clock and the remote clock identified as the master clock so that the local clock generated by the PLL is synchronized with the master clock.

Abstract: A method, a system, and a computer program for executing high resolution spectrum monitoring. A sensor receives an input signal having a varying frequency content over time. One or more samples of the received input signal are sampled. The samples of the received input signal include one or more swept signal samples generated by sweeping, using a center frequency of the sensor, the received input signal across an entire frequency spectrum associated with the received input signal. Sampling of the samples of the received signal is performed while performing the sweeping. The signal samples are processed.

Abstract: Systems are provided for implementing a hardware accelerator. The hardware accelerator emulate a stochastic neural network, and includes a first memristor crossbar array, and a second memristor crossbar array. The first memristor crossbar array can be programmed to calculate node values of the neural network. The nodes values can be calculated in accordance with rules to reduce an energy function associated with the neural network. The second memristor crossbar array is coupled to the first memristor crossbar array and programmed to introduce noise signals into the neural network. The noise signals can be introduced such that the energy function associated with the neural network converges towards a global minimum and modifies the calculated node values.

Abstract: Devices, systems, and methods for locking a voltage controlled oscillator (VCO) at a high frequency may include use of a VCO and an integrator, which generates and outputs a control signal to the VCO, based on an inverting signal and a reference signal. The control signal locks the VCO to a high frequency signal (FH). A frequency divider is coupled to the VCO, receives FH from the VCO, divides FH by a factor “F”, and outputs a low frequency signal (FL). A switched capacitor resistor circuit (SCRC) is coupled to the frequency divider and the integrator. The SCRC receives FL from the frequency divider and generates the inverting signal. An integrating capacitor is coupled across an inverting and an output terminal of op-amp in the integrator. The output of the op-amp provides an integrator signal, which may be (optionally) filtered to produce the control signal.

Abstract: A nanosecond pulser is disclosed. In some embodiments, the nanosecond pulser may include one or more switch circuits including one or more solid state switches, a transformer, and an output. In some embodiments, the transformer may include a first transformer core, a first primary winding wound at least partially around a portion of the first transformer core, and a secondary winding wound at least partially around a portion of the first transformer core. In some embodiments, each of the one or more switch circuits are coupled with at least a portion of the first primary winding. In some embodiments, the output may be electrically coupled with the secondary winding and outputs electrical pulses having a peak voltage greater than about 1 kilovolt and a rise time of less than 150 nanoseconds or less than 50 nanoseconds.

Abstract: A first drive operates directly on a machine element, whereas a second drive operates on a machine element via a speed-changing device. A position controller receives a position setpoint value and a position actual value of the machine element and determines therefrom a speed setpoint value for the machine element. A first determining device receives the speed setpoint value and determines a resulting speed setpoint value using the speed setpoint value. A first speed controller determines a first force setpoint value from the resulting speed setpoint value and the speed actual value of the machine element and controls the first drive depending on the first force setpoint value. A second speed controller determines a second force setpoint value from the resulting speed setpoint value and the speed actual value of the second drive and controls the second drive depending on the force setpoint value.

Abstract: During normal operation of a processor, voltage droop is likely to occur and there is, therefore, a need for techniques for rapidly addressing this droop so as to reduce the probability of circuit timing failures. This problem is addressed by provided an apparatus that is configured to detect the droop and react to mitigate the droop. The apparatus includes a frequency divider that is configured to receive an output of a clock signal generator (e.g. a phase locked loop) and produce an output signal in which a predefined fraction of the clock pulses in the output of the clock signal generator are removed from the output signal. By reducing the frequency of the clock signal in this way (as may be understood by examining equation 3) VDD is increased, hence mitigating the voltage droop. This technique provides a fast throttling mechanism that prevents excessive VDD droop across the processor.

Abstract: The present invention relates to a formulation containing at least one organic functional material and at least two different solvents, a first organic solvent A and a second organic solvent B, wherein the first organic solvent A comprises a group, which is capable of receiving or giving a hydrogen bonding, and wherein the second organic solvent B has a boiling point in the range from 150 to 350° C. and the solubility of the at least one organic functional material in the second organic solvent is ?5 g/l.

Abstract: In described examples, a stochastic comparator includes a first comparator that compares an input signal and a primary threshold to generate a first signal. A second comparator compares the input signal and the primary threshold to generate a second signal. A decision block generates a control signal in response to the first signal, the second signal and a PRBS (pseudo random binary sequence) signal. A XOR gate generates a detection signal in response the first signal and the second signal.

Abstract: Provided is a power amplifier circuit that can increase output power and also reduce the effect of intermodulation distortion. The power amplifier circuit includes a power divider, a distortion compensation circuit provided on the secondary path, a power combiner, and a first amplifier configured. The distortion compensation circuit includes a generation circuit configured to generate the second-harmonic wave of the input signal, a filter circuit configured to attenuate the fundamental wave and pass the second-harmonic wave, and a phase adjustment circuit configured to adjust the phase of the second-harmonic wave.

Abstract: An on-die early lifetime failure detection system with a reliability mechanism isolation circuit provides an early lifetime failure detection. The system measures and monitors reliability at time-0 (t0) and end-of-life. The measurements enable detection of latent reliability or marginality issues during the lifetime of the product. The system includes: a stress controller to adjust voltage for a power supply and voltage for a ground supply in accordance with one or more sensors; and an aging detector circuitry coupled to the stress controller, wherein the aging detector circuitry comprises a ring oscillator having delay stages, wherein each delay stage comprises an aging monitor circuitry, wherein the stress controller to adjust voltage for a power supply and voltage for a ground supply of the delay stage.

Abstract: The invention provides a semiconductor apparatus and a continuous readout method capable of achieving high speed continuous readout. The continuous readout method for NAND type flash memory of the invention includes: a detecting step of detecting a frequency of an external clock signal; a readout step of reading data from the memory cell array based on a readout timing corresponding to the frequency of the detected external clock signal; a holding step of holding the read data in a latch (L1) and a latch (L2), and an output step of outputting the held data in synchronization with the external clock signal.

Abstract: The present disclosure relates to a solid-state image sensor and an electronic device capable of simultaneously imaging a subject image and detecting a moving object. A solid-state image sensor according to an aspect of the present disclosure is provided with an infrared light detection unit which outputs a moving object image on the basis of infrared light out of incident light, and a visible light detection unit which outputs a subject image on the basis of visible light out of the incident light, in which the infrared light detection unit and the visible light detection unit are stacked and simultaneously output the moving object image and the subject image with the same frame and the same angle of view. The present disclosure is applicable to, for example, an electronic device having an imaging function for detecting a moving object.

Abstract: A radar device for providing data related to atmospheric conditions comprising a transceiver (10) with a single input/output port, the transceiver arranged to generate a frequency modulated continuous radar wave signal and direct it via the single input/output port to a first switch (20), the first switch arranged to direct the signal to a transmission branch including a first antenna (50) for transmission thereof, the radar device further comprising a receiving branch, separate from the transmission branch, arranged to direct received reflected radar waves and direct them as signals to the single input/output port of the transceiver via the first switch, wherein the first switch is arranged to isolate the transmission branch from the receiving branch.

Abstract: A clamping circuit that may be used to provide efficient and effective voltage clamping in an RF front end. The clamping circuit comprises two series coupled signal path switches and a bypass switch coupled in parallel with the series coupled signal path switches. A diode is coupled from a point between the series coupled signal path switches to a reference potential. In addition, an output selection switch within an RF front end has integrated voltage clamping to more effectively clamp the output voltage from the RF front end. Additional output clamping circuits can be used at various places along a direct gain signal path, along an attenuated gain path and along a bypass path.

Abstract: A nanosecond pulser is disclosed. In some embodiments, the nanosecond pulser may include one or more switch circuits including one or more solid state switches, a transformer, and an output. In some embodiments, the transformer may include a first transformer core, a first primary winding wound at least partially around a portion of the first transformer core, and a secondary winding wound at least partially around a portion of the first transformer core. In some embodiments, each of the one or more switch circuits are coupled with at least a portion of the first primary winding. In some embodiments, the output may be electrically coupled with the secondary winding and outputs electrical pulses having a peak voltage greater than about 1 kilovolt and a rise time of less than 150 nanoseconds or less than 50 nanoseconds.

Abstract: An improved ramp generator enables a very high degree of linearity in an output voltage ramp signal. Output ramps of the output voltage ramp signal are alternatingly produced from two preliminary ramp signals during alternating time periods. Preliminary ramps are produced at different preliminary ramp nodes that are alternatingly connected to an output node. The preliminary ramps continuously ramp during and in some cases beyond, e.g., before and/or after, the time periods. In some embodiments, switches alternatingly connect two capacitors to at least one current source, a reset voltage source, and the output node to alternatingly produce the preliminary ramps.

Abstract: The present invention relates to an integrated circuit arrangement comprising: —a plurality of capacitive micromachined ultrasound transducer (CMUT) cells (40) arranged in a hexagonal array, wherein said hexagonal array comprises a plurality of alternating even and odd columns (56, 56?) of CMUT cells (40) being parallel to a column direction (y), wherein the odd columns (56?) are arranged offset to the even columns (56) by one-half of a dimension of a CMUT cell (40) in said column direction (y), —an application-specific integrated circuit (ASIC) (52) comprising a plurality of transmit-receive (TR) cells (54), wherein each CMUT cell (40) overlays a respective TR cell (54) in a one-to-one correspondence, wherein the ASIC (52) further comprises an offset regulator (60) for providing different beamforming delays to even and odd columns (56, 56?) of the hexagonal array of CMUT cells (40) to account for the offset in the column direction (y).

Abstract: A drive device (102) with a converter function for a vehicle (100) has at least one first motor connection and one second motor connection for connecting the drive device (102) to a converter (108), a least one first motor coil and one second motor coil, wherein a first connection of the first motor coil is connected to the first motor connection and a first connection of the second motor coil is connected to the second motor connection, at least one first intermediate tap and one second intermediate tap, wherein the first intermediate tap is connected to a first tap point of the first motor coil and the second intermediate tap is connected to a first tap point of the second motor coil, and at least one first supply line connection and one second supply line connection for connecting the drive device (102) to an AC voltage supply line, wherein the first supply line connection is connected to the first intermediate tap and the second supply line connection is connected to the second intermediate tap.

Abstract: An apparatus is disclosed having a circulator having a transmit port, a receive port, and a tuner port with tuner circuitry coupled between the tuner port and an antenna port. At least one analog control branch is coupled between the receive port and at least one control input of the tuner circuitry to generate at least one control signal from a transmit leakage signal leaking into the receive port. The tuner circuitry is configured to respond to the at least one control signal by automatically electronically tuning such that a cancellation signal of substantially equal amplitude and opposite phase of that of the transmit leakage signal is reflected through the tuner port and into the receive port, thereby reducing the transmit leakage signal to a level corresponding to an isolation of at least ?30 dB between the transmit port and the receive port.

Abstract: A memory sub-system includes a power management integrated circuit (PMIC) compatible with operation at an uppermost PMIC supply voltage that is lower than a primary supply voltage of the memory sub-system. The PMIC is configured to output multiple voltages for operation of the memory sub-system based on a PMIC supply voltage. The memory sub-system further includes a capacitive voltage divider (CVD) coupled to the PMIC. The CVD is configured to receive the primary supply voltage of the memory sub-system as an input and provide a modified primary supply voltage (MPSV) to the PMIC as the PMIC supply voltage, where the MPSV is not higher than the uppermost PMIC supply voltage.

Abstract: An integrated circuit device that may include programmable logic fabric disposed on an integrated circuit die and a base die that may include clocking circuitry. Synchronization between logic resources in the programmable logic fabric may be performed using clock signals received from the clocking circuitry. The clocking circuitry in the base die may include phase-locked loops, delay-locked loops, clock trees, and other similar circuitry.

Abstract: Described is an apparatus which comprises: a Variable Gain Amplifier (VGA); a set of samplers to sample data output from the VGA according to a clock signal; and a Clock Data Recovery (CDR) circuit to adjust phase of the clock signal such that magnitude of a first post-cursor signal associated with the sampled data is substantially half of a magnitude of a primary cursor tap associated with the sampled data.

Abstract: A digital predistortion (DPD) system includes an input configured to receive a DPD input signal. In some examples, a non-linear datapath is coupled to the input, where the non-linear datapath is configured to add a non-linear mirror image component to the DPD input signal to provide a non-linear signal that is used to generate a first predistortion signal. In some embodiments, a linear datapath is coupled to the input in parallel with the non-linear datapath to generate a second predistortion signal. A first combiner is configured to combine the first predistortion signal and the second predistortion signal to generate a DPD output signal.

Abstract: The Marchand Salpingectomy is a fast, safe and minimally invasive procedure for removal of the fallopian tubes. The procedure involves minimal blood loss and gives the patient the benefit of permanent sterility as well as a decreased lifetime incidence of ovarian cancer. The procedure relies on two novel aspects of the technique which make the surgery significantly different than any surgery previously described as well as extremely minimally invasive.

Abstract: A symbol rate determination method for determining a symbol rate of an input signal is disclosed. The method comprises: receiving the input signal; determining respective pulse widths of pulses contained in the input signal; allocating the pulse widths to groups based on a magnitude of the respective pulse widths; determining a group pulse width for each of the groups, the group pulse width being representative of the pulse widths contained in the respective group; and determining the symbol rate based on the determined group pulse widths. Moreover, a measurement instrument for determining a symbol rate of an input signal is disclosed.

Abstract: A phase-locked loop (PLL) includes a detector configured to generate an error signal based on a difference between a reference signal and an output signal, a charge pump configured to generate current pulses based on the error signal, a loop filter configured to generate a control voltage based on the current pulses, and a voltage-controlled oscillator (VCO) configured to generate the output signal at a frequency which is a function of the control voltage. The loop filter includes a capacitive voltage divider configured to reduce the control voltage from a range that falls within a voltage domain of the charge pump to a range that falls within a voltage domain of the VCO, the voltage domain of the charge pump being greater than the voltage domain of the VCO.

Abstract: A semiconductor device comprises an input circuit that includes a first comparator configured to output a first output signal and a second output signal having a phase opposite to that of the first output signal, based on a comparison result of a first input signal and a second input signal which is a complementary signal of the first input signal. A duty ratio of the first output signal and a duty ratio of the second output signal are different from a duty ratio of the first input signal and a duty ratio of the second input signal, respectively.

Abstract: A power amplifier, a radio remote unit (RRU), and a base station, where the power amplifier includes an envelope controller, a main power amplifier, and an auxiliary power amplifier. The main power amplifier and the auxiliary power amplifier both set an envelope voltage output by the envelope modulator as operating voltages, and because the operating voltages of the main power amplifier and the auxiliary power amplifier may be adjusted simultaneously, symmetry of the power amplifier is improved, and an efficiency loss occurring probability is low, thereby enhancing efficiency of the power amplifier.

Abstract: Under one aspect, a method is provided for detecting events that are sparse in time. The method can include (a) receiving N analog input signals that are continuous and are independent from one another, wherein each one of the events causes a change in a corresponding one of the analog input signals, and N is 2 or greater. The method also can include (b) by a first analog circuit, for each of the N analog input signals, outputting products of that analog input signal and a plurality of gain factors. The method also can include (c) by a second analog circuit, outputting M sums of the products, wherein M is 2 or greater and is less than or equal to N. The method also can include (d) detecting a first one of the events based on the M sums of the products.

Abstract: An integrated circuit includes a degeneration network configured to improve group delay across one or more variations, wherein the degeneration network includes a transimpedance amplifier with one or more degeneration inductors. The transimpedance amplifier further includes one or more transistors, and the one or more degeneration inductors are connected after at least one emitter of the one or more transistors.

Abstract: Provided is a current output circuit that includes: a first FET that has a power supply voltage supplied to a source thereof, that has a first voltage supplied to a gate thereof and that outputs a first current from a drain thereof; a second FET that has the power supply voltage supplied to a source thereof, that has the first voltage supplied to a gate thereof and that outputs an output current from a drain thereof; a first control circuit that controls the first voltage such that the first current comes to be at a target level; and a second control circuit that performs control such that a drain voltage of the first FET and a drain voltage of the second FET are made equal to each other.

Abstract: A hybrid system-on-chip provides a plurality of memory and processor die mounted on a semiconductor carrier chip that contains a fully integrated power management system that switches DC power at speeds that match or approach processor core clock speeds, thereby supporting the transfer of data between off-chip physical memory and processor die.

Abstract: A circuit includes an ultrasonic transducer having a first terminal and a second terminal. The first terminal receives an electrical drive signal and excites the ultrasonic transducer during an excitation interval to provide an ultrasound signal. The first terminal also provides an electrical receive signal in response to the ultrasonic transducer receiving a reflected ultrasound signal. The circuit includes a capacitor having one terminal connected to the first terminal of the ultrasonic transducer. A resistor is connected to another terminal of the capacitor to form a resistor-capacitor (RC) network. At least one of resistor and the capacitor have a variable resistance or capacitance value that is set to tune the RC network to mitigate ringing of the ultrasonic transducer following the excitation interval.

Abstract: Methods and systems are described for receiving a reference clock signal and a phase of a local oscillator signal at a dynamically-weighted XOR gate comprising a plurality of logic branches, generating a plurality of weighted segments of a phase-error signal, the plurality of weighted segments including positive weighted segments and negative weighted segments, each weighted segment of the phase-error signal having a respective weight applied by a corresponding logic branch of the plurality of logic branches, generating an aggregate control signal based on an aggregation of the weighted segments of the phase-error signal, and outputting the aggregate control signal as a current-mode output for controlling a local oscillator generating the phase of the local oscillator signal, the local oscillator configured to induce a phase offset into the local oscillator signal in response to the aggregate control signal.

Abstract: A device, including a switch configured to couple a current source with an output terminal upon receipt of a data signal, is provided. The device also includes a first variable capacitor coupled in parallel to the current source at a common node on a source terminal of the switch, wherein the first variable capacitor comprises multiple capacitive elements coupled in parallel and configured to be activated by a programmable signal, and wherein the programmable signal is selected to increase a charge transfer rate from an output terminal coupled to a load, when the switch is turned on. A system and a serial interface including the above device are also provided.

Abstract: An illumination module that includes a pair of anamorphic prisms that comprises a first anamorphic prism and a second anamorphic prism; wherein the pair of anamorphic prisms is configured to (a) receive a first radiation beam that propagates along a first optical axis, and (b) asymmetrically magnify the first radiation beam to provide a second radiation beam that propagates along a second optical axis that is parallel to the first optical axis; and a rectangular prism that is configured to receive the second radiation beam and perform a lateral shift of the second radiation beam to provide a third radiation beam; and a rotating mechanism that is configured to change an asymmetrical magnification of the pair of anamorphic prisms by rotating at least one of the first anamorphic prism and the second anamorphic prism.

Abstract: A system, method, and circuit for determining signals. A bridge output is received from a Wheatstone bridge sensing a slow signal and a fast signal. A slow output associated with the slow signal and a fast output associated with the fast signal are determined from the bridge output utilizing a microcontroller. The microcontroller generates the offset signal in response to the slow output. Other systems, methods, and circuits are disclosed.

Abstract: End user on demand network resource instantiation in software-defined networks (SDN) may be provided by an SDN controller that receives an indication from a physical boost device operated by a network user. The boost device may indicate to the SDN controller that an improvement in network performance is desired by the network user. Once the indication is received, the SDN controller may implement network configuration changes for the improvement and cause the network user to be billed for the improvement.

Abstract: An apparatus comprises a first voltage-current conversion unit configured to receive a ramp signal, a second voltage-current conversion unit configured to receive a feedback signal proportional to an output voltage of a power converter, a third voltage-current conversion unit configured to receive an output signal of an error amplifier and a comparator having a first input coupled to an output of the third voltage-current conversion unit and a second input coupled to an output of the first voltage-current conversion unit and an output of the second voltage-current conversion unit through a first summing unit, wherein an output of the comparator determines a turn-on of a high-side switch of the power converter.

Abstract: A crest factor reduction (CFR) system includes a digital tilt filter coupled to an input of the CFR system. In some embodiments, the digital tilt filter is configured to receive a system input signal and generate a digital tilt filter output signal at a digital tilt filter output. In some examples, the CFR system further includes a CFR module coupled to the digital tilt filter output, where the CFR module is configured receive the digital tilt filter output signal and perform a CFR process to the digital tilt filter output signal to generate a CFR module output signal at a CFR module output. In addition, the CFR system may include a digital tilt equalizer coupled to the CFR module output, where the digital tilt equalizer is configured to receive the CFR module output signal and generate a system output signal.

Abstract: Some embodiments of the present invention describe an apparatus that includes an oscillator, a ramp generator, and an inverter. The apparatus includes an oscillator, an inverter, and a ramp generator. The oscillator is configured to generate a waveform comprising a low time and a high time. The inverter is configured to receive the waveform generated by the oscillator, and invert the waveform. The ramp generator configured to increase a gate control voltage of a transistor connected to a solar cell, and rapidly decrease the gate control voltage of the transistor. During the low time of the waveform, a measurement of a current and a voltage of the solar cell is performed as the current and voltage of the solar cell are transmitted through a first channel and to a second channel.

Abstract: A system and process for determining a communication status of an environment is disclosed. Sensors in the environment acquire data about the environment, and a first subset of the data is used to compute a first penalty about the environment, which is computed using a first algorithm that includes a maximum penalty and a decay rate at which the penalty decays over time. Further, a second subset of the data is used to compute a second penalty about the environment. The second penalty is computed using a second algorithm that also includes a maximum penalty and a decay rate at which the penalty decays over time. The first and second penalties are compiled to create an overall environmental penalty that represents a current status of the environment, which is compared to a threshold. If the overall environmental penalty exceeds the threshold, then an action, including issuing an alarm, is performed.

Abstract: Methods and systems are described for generating, with a local oscillator and an adjustable phase interpolator, a data-sampling clock and a variable-phase-offset eye-measurement clock, forming a received data signal using a multi-input comparator, generating, using a data slicer and the data sampling clock, a receive sample of the received data signal, and generating, using at least one eye slicer and the variable-phase-offset eye-measurement clock, a plurality of eye characteristic measurements by adjusting a sampling threshold of the at least one eye slicer and a phase offset of the variable-phase-offset eye-measurement clock.

Abstract: Certain aspects of the present disclosure provide a successive approximation register (SAR) analog-to-digital converter (ADC) implemented with a passive gain scaling architecture. Certain aspects provide a circuit for analog-to-digital conversion. The circuit generally includes a plurality of capacitive elements, a plurality of switches coupled to the plurality of capacitive elements, and SAR logic having an output coupled to control inputs of the plurality of switches. The circuit also includes a comparator having an output coupled to an input of the SAR logic, a sampling circuit coupled to an input node of the circuit, and a first capacitive element coupled in series between the sampling circuit and the plurality of capacitive elements.

Abstract: System and method for signal modulation. In one embodiment, a circuit includes a channel for carrying an analog RF signal, a phase offset circuit on the channel, and configured to receive a phase code for modifying the analog RF signal to produce a modified RF signal, and a feedforward cancellation path coupled in parallel to the phase offset circuit for canceling a portion of the modified analog signal.