Abstract: A driver circuit comprises a first transistor coupled to a second transistor, and a third transistor coupled to the first and second transistor and to a first current mirror. An output of the first current mirror is provided to a control input of the second transistor. A second current mirror is coupled to the output of the first current mirror. A first current source, a second current source, and a fourth transistor are coupled to the second current mirror. The second current source is further coupled to a fifth transistor. A sixth transistor is coupled to the fifth transistor and to a third current mirror. In some implementations, the driver circuit is coupled to a low side transistor in an H bridge driver and the second transistor is matched to the low side transistor.

Abstract: In some examples, the disclosure includes a circuit including a power field effect transistor (FET), a gate pull-down circuit, a pull-down bias circuit, and a radio frequency (RF) detector coupled to the source terminal of the power FET and the pull-down bias circuit. In an example, the RF detector circuit is configured to detect a presence of an alternating current signal at a source terminal of the power FET when the power FET is in a non-conductive state and control the pull-down bias circuit to bias the gate pull-down circuit to create a low impedance path between a gate terminal of the power FET and the source terminal of the power FET when the power FET is in the non-conductive state and the alternating current signal is present at the source terminal of the power FET.

Abstract: A voltage recovery circuit in an integrated circuit is provided. The voltage recovery circuit includes a bootstrap circuit coupled to a cascode switch circuit. The bootstrap circuit includes a first transistor coupled in series to a second transistor, a resistive element is coupled between the second transistor and an output of the voltage recovery circuit, and a capacitive element is coupled between control electrodes of the first and second transistors and the output. The cascode switch circuit includes a third and fourth transistor coupled in series. The third transistor includes a current electrode coupled to receive a first input voltage, and a control electrode coupled to the control electrodes of the first and second transistors. The fourth transistor includes a current electrode coupled to the output, and a control electrode coupled to a current electrode of the second transistor and a terminal of the resistive element.

Abstract: A waveform shape discriminator includes a running maximum finder circuit coupled to receive a sense signal. The running maximum finder circuit is coupled to update a running maximum signal in response to the sense signal. A first comparator is coupled to receive the sense signal and a running maximum threshold signal that is representative of the running maximum signal. A search window block is coupled to receive the input signal to detect a search window in the sense signal. An output circuit is coupled to an output of the first comparator and an output of the search window block to determine a presence of a waveform shape in the sense signal within the search window in the sense signal.

Abstract: There is provided an adjustable harmonic distortion detector that includes a clock signal source, means for the detection of a first period of evaluation, and means for the detection of a second period of evaluation. The detector has the characteristic that a first block memorizes a number equal to the clock pulses present in the first period of evaluation, a multiplier block performs a multiplication between the number stored in the first block and a multiplicative factor during the second period of evaluation, and a second block memorizes the outcome. The second block is adapted to generate an output signal when the outcome in the second block is equal to zero.

Abstract: A circuit for evaluating characteristics of duration and/or shape of an electric pulse induced in an element of an integrated circuit comprising an assembly of elements, each element being likely to receive an occasional external disturbance generating an electric pulse in the element, and a measurement circuit connected to the elements to determine said characteristics of an electric pulse generated in one of the elements.

Abstract: An improved method of preventing computer malfunction during a change of power consumption states is disclosed. The computer operates a microprocessor at a specified voltage during a normal operation. To offset the normal decrease in voltage due to an instantaneous increase in power requirements during a change of power consumption states, the specified voltage is increased prior to entering a higher power consumption state such that the voltage level remains within minimum operating limits.

Abstract: A method and apparatus for detecting a sinusoidal signal samples a received signal. An error signal generator receives at its inputs a previous sample of the received signal and a current sample of the received signal and generates an error signal based on these previous and current samples. A comparison circuit compares the generated error signal for the current sample to an error threshold value and generates a threshold comparison signal with a first value that indicates the generated error signal is below the error threshold value for a second value that indicates a generated error signal is above the error threshold value. A determination circuit then determines whether the received signal is a sinusoidal signal based on a threshold comparison signal generated for a plurality of samples. The determination circuit includes a counter that maintains a count of the number of threshold comparison signals having the first value within a sampling period.

Abstract: To realize a high frequency power detection circuit constituting a detection circuit by a GaAs semiconductor and thereby capable of realizing a small sized, low cost, and broad band detection circuit and suppressing variations in the detection characteristics due to variations in a pinchoff voltage of the field effect transistors, the invention is a detection circuit for detecting an envelope of a high frequency signal, comprising a field effect transistor to the gate of which the high frequency signal is input, a gate bias circuit for providing a gate bias voltage to the gate of the field effect transistor, a capacitor connected between the drain of the field effect transistor and the ground, and a load capacitor and a load resistor connected in parallel between the source of the field effect transistor and the ground, wherein a detection signal corresponding to the envelope of the high frequency input signal is output from the source of the field effect transistor.

Abstract: The sensing circuit is used in an Asymmetric Digital Subscriber Line (ADSL) transmission system to detect a wave signal with a predetermined shape in an input signal (IN1/IN2) transmitted over the system and applied to an input terminal (IN1/IN2) of the sensing circuit. It includes two branches with a correlated double sampling circuit (CDS1/CDS2), a counter circuit (C1/C2) and a comparator circuit (CMP1/CMP2) coupled in series. An input (IN1/IN2) of the correlated double sampling circuit of each branch is coupled to the input of the sensing circuit and an output of the comparator circuits is coupled to an output terminal (OUT) of the sensing circuit via an OR-ing circuit. The correlated double sampling circuits are adapted to provide a sampled signal and the counter circuits count the number of pulses of the sampled signals.

Abstract: This detector provides a computationally simple digital low power detector of symbol rate, also called baud rate. It uses an approximate Hilbert transform function to create approximate in-phase and quadrature signals. An approximate envelope detector (feature extractor) processes these signals to produce a signal with a strong frequency component at the symbol rate. This signal is then filtered, accumulated, and threshold detected. The approximate in-phase and quadrature signals are formed by a linear sequence of six delay elements, the output of the third delay element being the in-phase signal. A first summer receives the output of the second delay element at a minus input and the output of the fourth delay element at a plus input. A second summer receives the signal input at a minus input and the output of the sixth delay element at a plus input, and drives a right two bit shifter.