Abstract: Example flip-flops comprise a circuit that receives a primary clock signal, generates a clock buffer signal having a series of pulses, each delayed by a set amount of time relative to a corresponding pulse of the primary clock signal, generates an intermediate clock signal based on the primary clock signal and the clock buffer signal, generates inflated low pulse width clock signals, each having a low pulse width that is greater than a low pulse width of the primary clock signal. Latch stages within example flip-flops include one or more components that are controlled by the inflated low pulse width clock signals. Example flip-flops include high-speed flip-flops and standard flip-flops. Larger circuits, such as a clock divider circuits, may incorporate multiple example high-speed flip-flops to improve performance.

Abstract: Systems, apparatus and methods are provided for loopback testing techniques for memory controllers. A memory controller that may comprise loopback testing circuitry that may comprise a first multiplexer having a first input coupled to an output of an input buffer and a second input coupled to a first data output from the memory controller, an inverter coupled to the output of the input buffer, and a second multiplexer having a first input coupled to an output of the inverter and a second input coupled to a second data output from the memory controller.

Abstract: The present disclosure is to improve the power added efficiency of a power amplifier at high output power. The power amplifier includes: a first capacitor with a radio frequency signal input to one end thereof; a first transistor whose base is connected to the other end of the first capacitor to amplify the radio frequency signal; a bias circuit for supplying bias to the base of the first transistor; and a second capacitor with one end connected to the base of the first transistor and the other end connected to the emitter of the first transistor.

Abstract: The invention relates to a device and to a method for producing a signal having an adjustable pulse duty factor, in particular a pulse-width-modulated signal. For this purpose, the period duration of the pulse-width-modulated signal can be varied. Thus, the pulse duty factor of the pulse-width-modulated signal can be adapted very accurately to the desired pulse duty factor without great switching complexity by using a simple counter with a fixed clock frequency.

Abstract: Provided are a reference voltage training device and a method thereof. The reference voltage training device includes a comparator configured to compare a toggle signal with a reference voltage and output a comparison signal, a duty cycle detector configured to check a duty ratio of the comparison signal, and a reference voltage level changing unit configured to fix the reference voltage when the duty ratio meets a predetermined condition and to change a level of the reference voltage when the duty ratio does not meet the predetermined condition. The comparator outputs a changed comparison signal using the changed reference voltage.

Abstract: A circuit configuration for generating pulses within a time interval on the basis of an input signal includes a counting unit, a comparator unit and a first adder circuit; the time interval being predicted on the basis of at least two defined changes in input signals; the circuit configuration being configured for triggering at the beginning of the time interval by the first adder circuit on the basis of clock pulses, for generating and outputting pulses; for counting a number of generated and output pulses using the counting unit; for comparing the counted number to a setpoint value using the comparator unit; and for ending the generation and outputting of the pulses in response to the reaching of the setpoint value or the ending of the time interval.

Abstract: A receiver for decoding a communication signal is disclosed. The receiver includes an input port and a filter. The input port receives the communication signal from a communication medium. The communication signal comprises a sequence of symbols. Each symbol of the symbol sequence is an analog pulse that has a leading edge of exponential shape. The exponential shape has an exponential growth parameter value that has been selected from values ?0 and ?1, which are distinct positive values. For each symbol of the symbol sequence, the exponential growth parameter value for the leading edge of the symbol has been selected based on a corresponding bit from a stream of information bits. The filter receives the communication signal from the input port and filters the communication signal to obtain an output signal. The transfer function of the filter has one or more zeros at ?0.

Abstract: A first transmitter transmits symbols. The leading edge of each symbol has the form Djexp{?jt}, where Dj is real, where ?j is selected from N possible values based on a current group of bits. The receiver has N filters whose transfer functions correspond respectively to the N possible values. The filter outputs are used to recover the group of bits. A second transmitter transmits an exponential symbol or a zero symbol depending on a current bit to be transmitted. The zero symbol has zero amplitude over the symbol period. The corresponding receiver applies threshold detection to estimate the transmitted bits. A third transmitter transmits a sequence of analog pulses with known interpulse time separation(s). The pulse sequence reflects from a moving object. A receiver captures the reflected pulse sequence. The interpulse separation(s) of the reflect pulse sequence is used to determine the radial velocity of the object.

Abstract: A signal transmission circuit 200 transmits input signals IN1 and IN2 each having a different transmission speed in a mutually electrically insulated manner. Signal transmission circuit 200 includes a pulse generation unit 210, transmission units 230 and 235, a latch circuit 250, and an oscillation determination circuit 270. Transmission units 230 and 235 transmit pulse signals PLS_A and PLS_B generated by pulse generation unit 210 in accordance with logical states of input signals IN1 and IN2 to latch circuit 250 and oscillation determination circuit 270 in a mutually electrically insulated manner. Latch circuit 250 restores input signal IN1 in accordance with rising edges of pulse signals PLS_A and PLS_B. Oscillation determination circuit 270 restores input signal IN2 based on oscillation states of pulse signals PLS_A and PLS_B. With such a configuration, a plurality of signals each having a different transmission speed can be transmitted in a mutually electrically insulated manner.

Abstract: A receiver circuit. A receiving stage is coupled to a first supply voltage and an input signal, and operative to generate a first intermediate signal from the input signal based on the first supply voltage. A compensation stage is coupled to a second supply voltage and the first intermediate signal, and operative to generate a second intermediate signal by adjusting duty cycle of the first intermediate signal upon detecting changes in the first supply voltage to compensate for the changes in the first supply voltage. An outputting stage is coupled to the second supply voltage and operative to generate an output signal based on the second supply voltage upon receiving the second intermediate signal. A voltage of the output signal is adjusted to a level of the second supply voltage and the output signal has a 50% duty cycle.

Abstract: Methods of operating timers include generating a periodic timing signal having a first frequency that differs from a desired timer frequency (1 KHz) by a first amount. This periodic timing signal having the first frequency can be generated by dividing a frequency of an input clock signal (e.g., 32.768 KHz) by N, where N is a positive integer greater than one. A typical value of N may be 32. The methods also include techniques to inhibit timing error accumulation by switching a frequency of the periodic timing signal from the first frequency to a second frequency that differs from the desired timer frequency by a second amount. This periodic timing signal having the second frequency can be generated by dividing the frequency of the input clock signal by M, where M is a positive integer unequal to N (e.g., M?N equals ±1).

Abstract: A duty ratio correction circuit, includes: a frequency divider configured to output a second clock signal having a first level that is inverted at a timing of a first edge of a first clock signal and a third clock signal having a second level that is inverted at a timing of a second edge of the first clock signal; phase interpolator configured to generate a fourth clock signal and a fifth clock signal based on phase interpolation of any two of the second clock signal, the third clock signal, a first inverted signal that is obtained by inverting the second clock signal, or a second inverted signal that is obtained by inverting the third clock signal; and a multiplier configured to output an exclusive OR signal of the fourth clock signal and the fifth clock signal as a sixth clock signal.

Abstract: A margin circuit for controlling skew between first and second signals in order to determine margin, includes a variable delay circuit and a margin controller. Based on a current code value, the delay circuit applies a delay to the second signal to generate a delayed second signal. The margin controller generates the current code value for the variable delay circuit to be any one of a plurality of available code values. In one embodiment, the margin circuit is a write margin circuit that generates a first clock signal and a delayed second clock signal used to generate transmit (TX) clock and data signals having a non-zero phase offset between them. In another embodiment, the margin circuit is a read margin circuit that applies a phase offset between receive (RX) clock and data signals to enable the RX clock signal to be used to recover data from the RX data signal.

Abstract: Aspects of the disclosure provide an integrated circuit. The integrated circuit includes a signal generation circuit. The signal generation circuit is configured to generate a first output signal and a second output signal in response to a reference signal. The first output signal and the second output signal are a pair of complementary signals. The first output signal has first transitions of a first polarity and second transitions of a second polarity. The second output signal has third transitions of the second polarity that are simultaneous to the first transitions in the first output signal and has fourth transitions of the first polarity non-simultaneously corresponding to the second transitions in the first output signal.

Abstract: An interface apparatus for a semiconductor integrated circuit and an interfacing method thereof controls the VOX of differential signals to a target level in response to the differential signals being outputted by an output block. The interface apparatus for a semiconductor integrated circuit includes an output block configured to output differential signals output by an internal circuit a detector configured to detect a timing error of the differential signals; and a controller configured to control a timing of the differential signals output by the internal circuit according to a detection result of the detector.

Abstract: An electronic oscillation signal generation circuit includes an electronic oscillation circuit, a DC voltage source for providing a DC voltage to the electronic oscillation circuit, a switch for electrically connecting the electronic oscillation circuit to ground when the switch is turned on so as to generate an analog oscillation signal after the switch is turned off, a conversion circuit for converting the analog oscillation signal to a digital oscillation signal, a counter for generating a control signal when the digital oscillation signal reaches a predetermined number of periods, a delay unit for generating a delay signal a predetermined time after a falling edge of the digital oscillation signal is triggered, and a pulse signal generation circuit electrically connected to the counter and the delay unit for generating a pulse signal according to the control signal and the delay signal so as to turn on the switch.

Abstract: According to one embodiment, a clock generating circuit includes first and second current generating circuits, first and second voltage generating circuits, first and second comparing circuits, a clock output circuit, a control circuit. The first current generating circuit is configured to generate a first current. The first voltage generating circuit is configured to generate a first voltage which increases or decreases according to a phase of a clock signal as time advances by the first current. The first comparing circuit is configured to compare the first voltage with a first threshold voltage to generate a first comparison result. The second current generating circuit is configured to generate a second current. The second comparing circuit is configured to compare the second voltage with a second threshold voltage to generate a second comparison result.

Abstract: A semiconductor chip comprises an internal clock circuit, a first phase shift device, a second phase shift device, a multiplexer, a first output pad, and a controllable pad. The internal clock circuit generates an internal clock signal. The first phase shift device shifts the phase of an external clock signal and outputs a phase shifting clock signal. The multiplexer selectively outputs one of the internal clock signal and the phase shifting clock signal to be a first clock signal. The second phase shift device shifts the phase of the first clock signal and outputs a second clock signal. The first output pad outputs the first clock signal. The controllable pad is controlled to selectively act as an input pad for receiving the external signal, or act as a second output pad for transmitting the second clock signal.

Abstract: A bipolar pulse generator includes two, two-conductor transmission lines coupled together with a load positioned between the two transmission lines. Each conductor of a transmission line we define as a segment. Two segments of one transmission line are charged and switchably coupled to two segments of the other transmission line to produce a bipolar pulse on the matched load. This bipolar pulse generator may be implemented in a flat or a folded design. The generator may include two transmission line structures coupled together with a load positioned between each transmission line structures. The first transmission line structure may include a stepped transmission line and an embedded transmission line segment. A switch may be coupled between the embedded transmission line segment and another segment of the transmission line structure.

Abstract: Disclosed is an apparatus and methodology for operating an automatic darkening filter (ADF) eye protection device. An operating voltage is alternately applied to a pair of control terminals of an ADF device circuit in a continuing sequence where a first polarity voltage is applied to the pair of terminals and then reversed. A delay period is provided between application of the alternating polarities. In some embodiments ground potential is applied to both terminals of the pair of terminals during the delay period.

Abstract: A bipolar pulse generator includes two, two-conductor transmission lines coupled together with a load positioned between the two transmission lines. Each conductor of a transmission line we define as a segment. Two segments of one transmission line are charged and switchably coupled to two segments of the other transmission line to produce a bipolar pulse on the matched load. This bipolar pulse generator may be implemented in a flat or a folded design. The generator may include two transmission line structures coupled together with a load positioned between each transmission line structures. The first transmission line structure may include a stepped transmission line and an embedded transmission line segment. A switch may be coupled between the embedded transmission line segment and another segment of the transmission line structure.

Abstract: A bipolar pulse generator includes two, two-conductor transmission lines coupled together with a load positioned between the two transmission lines. Each conductor of a transmission line we define as a segment. Two segments of one transmission line are charged and switchably coupled to two segments of the other transmission line to produce a bipolar pulse on the matched load. This bipolar pulse generator may be implemented in a flat or a folded design. The generator may include two transmission line structures coupled together with a load positioned between each transmission line structures. The first transmission line structure may include a stepped transmission line and an embedded transmission line segment. A switch may be coupled between the embedded transmission line segment and another segment of the transmission line structure.

Abstract: A bipolar pulse generator includes two, two-conductor transmission lines coupled together with a load positioned between the two transmission lines. Each conductor of a transmission line we define as a segment. Two segments of one transmission line are charged and switchably coupled to two segments of the other transmission line to produce a bipolar pulse on the matched load. This bipolar pulse generator may be implemented in a flat or a folded design. The generator may include two transmission line structures coupled together with a load positioned between each transmission line structures. The first transmission line structure may include a stepped transmission line and an embedded transmission line segment. A switch may be coupled between the embedded transmission line segment and another segment of the transmission line structure.

Abstract: A control signal generation circuit includes a pulse signal generator configured to delay a column control signal by delay times different from each other and to generate first and second pulse signals, a reset signal generator configured to transfer alternatively the first and second pulse signals as a reset signal in response to a write/read flag signal, and a write-enable signal generator configured to generate a write-enable signal from the first pulse signal in response to the write/read flag signal.

Abstract: An impulse generation circuit is provided for generating an impulse using a transmission line. Impulse characteristics of the impulse generation circuit are varied with the length of a transmission line rather than the characteristic variation of various devices used therein. The length of the transmission line is adjusted, such that a width of a generated pulse is adjusted. Because an end of the transmission line is short-circuited, the transmission line length can be easily adjusted on a substrate, and a ringing phenomenon due to re-reflection can be removed using termination impedance.

Abstract: A data output driving circuit capable of optimizing a slew rate of data according to the variation of operational conditions and a method for controlling a slew rate thereof includes a slew rate control signal generating unit configured to generate slew rate control signals by using a code signal, and a plurality of drivers configured to output data by driving the data at a slew rate set according to the slew rate control signals.

Abstract: Techniques are disclosed for adjusting and programming the duty cycle of a signal generated by a circuit. In an embodiment, parallel transistors are coupled between a NAND gate and a supply voltage. Selectively enabling the parallel transistors adjusts the switching point of the NAND gate, thereby allowing control of the pulse width of the output signal. In an alternative embodiment, the size of the PMOS versus the NMOS transistors in the NAND gate is selectively varied to achieve the same effect. Further disclosed are applications of the techniques to calibrating the receiver to minimize measured second-order inter-modulation products and/or residual sideband.

Abstract: A bipolar pulse generator is implemented in a simple structure while providing a high efficiency design having a relatively low total size, while still allowing access by fibers used to control a photoconductive switch that activates the generator. The bipolar pulse generator includes a stacked Blumlein generator structure with an additional transmission line connected to a load at its near end and short-circuited at its distal end. An extra transmission line is positioned between the Blumlein generator's structure and the load provides specified limited gap between positive and negative sub-pulses. The bipolar pulse generator further includes a bended Blumlein generator structure, in which an existing intrinsic “stray” transmission line is used to provide the bipolar pulse. Still further, bipolar pulse generator includes stepped transmission lines, with additional switches positioned between steps, which are charged by different voltages.

Abstract: Disclosed herein is an apparatus for outputting complementary signals using bootstrapping technology. The apparatus for outputting complementary signals includes a precharaged logic block, one or more output nodes, and a bootstrapping circuit block. The precharged differential logic block generates a differential signal depending on an input signal. The one or more output nodes output the complementary signals depending on the differential signal. The bootstrapping circuit block is shared by the one or more output nodes, and amplifies the complementary signals.

Abstract: A transistor includes a first semiconductor layer associated with a first electrode; a second semiconductor layer associated with a second electrode; and a discontinuous layer between the first and second semiconductor layer. The discontinuous layer has a plurality of openings being formed on a nonuniform organic surface. Applications of the transistor include an inverter that operates at low supply voltage and high frequency.

Abstract: A polarity switching member of a dot inversion system is revealed. A first transistor and a second transistor are disposed in a P-well while a N-well is arranged in the P-well, located between the first transistor and the second transistor. The N-well includes a third transistor and a fourth transistor. One end of the third transistor is coupled to one end of the first transistor to generate a first input end and one end of the fourth transistor is coupled to one end of the second transistor to generate a second input end. The other end of the first transistor, the other end of the second transistor, the other end of the third transistor, and the other end of the fourth transistor are coupled to generate an output end. Thereby, by switching of voltage polarity of the P-well and the N-well, a larger range of output voltage difference is achieved.

Abstract: A single-ended to differential converter is presented. The converter may be configured to convert full-swing single-ended signals to low-swing differential signals within a single-stage, thereby reducing signal distortion. The converter may include a passive network of resistive elements, for example resistors and/or metal oxide semiconductor (MOS) devices operating in a linear region. The converter may also allow for adjustable design parameters such as a common mode, differential amplitude, and an output swing. The adjustments may all be made within the single-stage of the converter.

Abstract: A bipolar pulse generator includes two, two-conductor transmission lines coupled together with a load positioned between the two transmission lines. Each conductor of a transmission line we define as a segment. Two segments of one transmission line are charged and switchably coupled to two segments of the other transmission line to produce a bipolar pulse on the matched load. This bipolar pulse generator may be implemented in a flat or a folded design. The generator may include two transmission line structures coupled together with a load positioned between each transmission line structures. The first transmission line structure may include a stepped transmission line and an embedded transmission line segment. A switch may be coupled between the embedded transmission line segment and another segment of the transmission line structure.

Abstract: Method and apparatus for electrosurgery including tissue coagulation using very high voltage pulses of electrical energy applied to the electrosurgical probe. This minimizes heating of the surrounding tissue in the probe and is especially suitable for precise and limited coagulation and fulguration without excessive tissue charring or other damage. The power at rated load of the applied pulses to the probe is typically over 300 W and the duration of the on time is very short, so each group of pulse bursts is of relatively low duty cycle. An RF generator is also provided for delivering electrical energy to an electrosurgical probe with the proper characteristics, including fast switching times.

Abstract: A complementary signal generation circuit includes a first transmission path including a first number N of inverters and a second transmission path including a second number (N?1) of inverters. A delay circuit composed of a first resistance element and a capacity element is arranged in series between two inverters in the second transmission path so as to correspond to any one of the inverters in the first transmission path. The capacity element is formed by a capacitive inverter having the same input capacity ratio as the any one of the inverters. The complementary signal generation circuit generates output signals having the logic levels which are complementary to each other through the first and second transmission paths.

Abstract: Methods, systems, and devices are described for providing a communication system for handling pulse information. Embodiments of the invention provide a pulse shaping unit operable to avoid saturation of the pulse transformer, while being easily incorporated into IC processes. Some embodiments of the pulse shaping unit provide a two-to-three level driver unit for converting a two-level input voltage signal to a three-level driver signal for driving a pulse transformer. Other embodiments of the pulse shaping unit provide components configured to differentially drive a pulse transformer, effectively converting a two-level input voltage signal to a three-level driver signal.

Abstract: A circuit for correcting a duty cycle includes a duty ratio digital conversion block configured to output duty ratio information of an input clock signal as plural-bit digital signals, a duty ratio information analyzing block configured to analyze the duty ratio information of the input clock signal, generate edge control signals, and select any one of a plurality of delayed clock signals, and a duty ratio control block configured to control duty ratios of a selected delayed clock signal and the input clock signal in response to the edge control signals.

Abstract: Circuits and methods provide single-ended and differential signals. Single-ended drivers are used to, e.g., reduce pin capacitance. The output cell uses an inversion circuit, such as a phase splitter, to derive the differential signals from the same output signal and provide low skew between the differential signals at the output pins. Selection circuits are used to select between single-ended and differential output.

Abstract: A circuit to convert a single ended signal to differential signals is disclosed. The circuit has two paths with each of the two paths comprising a plurality of stages. The number of stages in each of the two paths is the same. A first path of the two paths includes a buffer stage and at least one inverter stage. A second path of the two paths includes at least two inverter stages. The buffer stage has a delay matched to that of a first inverter stage of the second path. The buffer stage comprises a first pair of transistors comprising a first transistor of a first category operatively connected to a first transistor of a second category with their channel connections being connected in series.

Abstract: A clock switching circuit comprises: a composite clock generation circuit, which is to receive a first clock, a second clock, and a clock switching execution signal for switching between the first clock and the second clock, and to make a level of the clock fixed to be a second level and to output the clock as a composite clock for clock switching, for a specified period including one of a leading edge and a trailing edge of the clock as well as additional time before and after the edge, when the signal becomes active while the clock is at a first level; a switching demand signal generation circuit that receives the clock and the signal, and outputs a clock switching demand signal; a clock selection signal generation circuit that changes a level of a first clock selection signal when the signal becomes active; and a first selector that selects one of the clock and the clock, according to the level of the signal, and outputs the selected clock.

Abstract: A system and method for configuring a receiver such that the duty cycle of the receiver clock accurately matches the duty cycle of the data signal received. This adaptive system and method calibrates a receiver's duty cycle to optimize the receiver timing margin for different data signal types and different slave devices. In one embodiment, a duty cycle correction circuit matches the receiver clock to a predetermined duty cycle. The receiver clock is then configured to have a duty cycle skewed from the predetermined duty cycle based on the specific data signal received. In a receiver system utilizing a clock tree, individual branches of the clock tree are configured to have respective duty cycles skewed to match the duty cycle of a data signal received from a specific transmitting device.

Abstract: A buffer design for an integrated circuit that has adjustable slew rate control, yet requires significantly less space to fabricate than does a conventional buffer with slew rate control. A new slew rate control circuit design is added to a Complementary Metal Oxide Semiconductor CMOS buffer to implement slew rate control in the buffer (e.g., selection between a high slew rate and a low slew rate). The new slew rate control circuit requires significantly less space to fabricate, and when applied to each buffer in an given integrated circuit, e.g., input/output buffers that may be placed along the periphery of the integrated circuit, the savings can be extraordinary.

Abstract: The present invention provides an inverter controller comprising a drive circuit that generates a plurality of switch drive signals for inverter applications. In some exemplary embodiments, the drive circuit operates by reversing the command level of an error signal. In other embodiments, the drive circuit operates by using a half period of a sawtooth signal. In still other embodiments, the drive circuit operates by using a double period opposite shifting pulses method. The present invention also provides a PWM signal generator circuit that generates periodic PWM switch drive signals symmetrical to the minimum or maximum of a sawtooth waveform.

Abstract: There is provided a pulse generating circuit, which generates two pulses having a sign of amplitude different from each other, including: a step recovery diode of which electric potential of an anode and a cathode is respectively output as the pulses; a bias unit operable to select either a forward bias or a backward bias according to a given control signal and apply the selected bias to the step recovery diode; a forward current source operable to prescribe a forward current to be supplied to the step recovery diode when the forward bias is applied to the step recovery diode; and a backward current source operable to prescribe a backward current to be supplied to the step recovery diode when the backward bias is applied to the step recovery diode.

Abstract: A high side switching circuit, comprising: a switching transistor; a charge pump drive circuit including a circuit for generating an oscillating signal; and a charge pump arranged to provide a gate drive voltage to the switching transistor in response to a control signal; wherein the charge pump is driven by the charge pump drive circuit, and the circuit for generating an oscillating signal comprises: an oscillator having a power supply input and first and second outputs, outputting first and second pulse trains respectively of the same frequency but out of phase such that when the first pulse train is high, the second pulse train is low and when the second pulse train is high, the first pulse train is low; first and second transistors connected in series with the drain of the first transistor connected to a high voltage input relative to the high level of the first and second pulse train pulses, the source of the first transistor connected to the drain of the second transistor, the source of the second trans

Abstract: The present invention discloses a duty ratio corrector which can reduce power consumption by blocking current paths between output terminals and a ground terminal by applying input signals for turning off switching devices for generating an auxiliary voltage for correcting a duty ratio at an initial stage, and which can improve an operational speed by changing the auxiliary voltage from a predetermined voltage, not 0V, to an target voltage, and a memory device having the same.

Abstract: A pulse generating circuit generates a pulse with a desired pulse width even when a process parameter for manufacturing fluctuates or a source voltage varies. The pulse generating circuit includes a first voltage outputting section having a first delay circuit and operating to output a first voltage changing from a high level towards a low level based on a first time constant according to a one-shot pulse, a second voltage outputting section having a second delay circuit and operating to output a second voltage changing from a low level towards a high level based on a second time constant according to the one-shot pulse, and a differential circuit to generate a pulse with a pulse width corresponding to a period from a time point of inputting the one-shot pulse to a cross time point when the first voltage coincides with the second voltage.

Abstract: A method and system for sampling on the fly one or more integrated circuit nodes coupled to one or more bus domain clocks of an integrated circuit using minimal clock cycle delay synchronization. Sample on the fly circuitry, set-reset circuitry and metastable rejection circuitry are used to provide a sufficient pulse width for sampling on the fly the one or more nodes when the one or more bus domain clocks require asynchronous operation. The sample on the fly circuitry is also operable to synchronously sample on the fly the one or more nodes.

Abstract: A pulse generator system includes a plurality of buffers at least two transmission gates. The inverters successively and input insert delays into an signal having a series of pulses, each pulse having first and second edges. The transmission gates are operatively coupled to the inverters. The first transmission gate selectively passes the input signal. The second transmission gape selectively passes inverted signal of the input signal.

Abstract: An apparatus, method and means for providing a clock signal and an inverted clock signal having corresponding rise and fall edge rates, being resistant to load variations, process variations, voltage variations, and temperature variations. The apparatus output exceeds a threshold voltage for apparatus circuit paths. In one aspect of the invention, a combination of N channel and P channel devices, viewed as symmetrical P stacks and N stacks, are utilized. Low output impedance and high gain is provided for resistance to load variations.