Abstract: A switching activity report of simulated switching activities of a semiconductor circuit is accessed. A plurality of glitch bottleneck ratios corresponding to a plurality of pins in the semiconductor circuit are determined, comprising by: setting an initial bottleneck ratio on a leaf output pin; and backward traversing the semiconductor circuit to determine a plurality of glitch bottleneck ratios of pins in a fan-in cone of the leaf output pin. A plurality of total glitch powers associated with the plurality of pins is determined, a total glitch power of the plurality of total glitch powers being determined based on a glitch bottleneck ratio and a glitch power of a corresponding pin. One or more critical bottleneck pins among the plurality of pins are identified based on the plurality of total glitch powers. One or more gates associated with the one or more critical bottleneck pins are adjusted to reduce corresponding one or more total glitch powers of the one or more gates.

Abstract: A network device including frequency generation circuitry configured to generate a clock signal, a phase-locked loop configured to generate a local clock based on the clock signal, a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream, and a controller configured to identify the remote clock recovered by one of the plurality of receivers as a master clock, find a clock differential between the identified remote clock and the local clock, provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuit to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential.

Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.

Abstract: An integrated circuit includes a detector configured to monitor a high-drive signal and a low-drive signal that drives a high-side switch and a low-side switch respectively of an integrated circuit switching regulator. The detector monitors both the rising edge and the trailing edge of each of the high-drive and the low-drive signals respectively to determine a timing overlap between the signals and generates a detection signal indicating a dead-time value proportional to the presence or absence of the timing overlap between the signals. An output circuit can be configured to process the detection signal from the detector to enable a correction of the timing overlap between the signals if timing overlap is detected.

Abstract: A receiver for decoding a communication signal is disclosed. The receiver includes an input port and a filter. The input port receives the communication signal from a communication medium. The communication signal comprises a sequence of symbols. Each symbol of the symbol sequence is an analog pulse that has a leading edge of exponential shape. The exponential shape has an exponential growth parameter value that has been selected from values ?0 and ?1, which are distinct positive values. For each symbol of the symbol sequence, the exponential growth parameter value for the leading edge of the symbol has been selected based on a corresponding bit from a stream of information bits. The filter receives the communication signal from the input port and filters the communication signal to obtain an output signal. The transfer function of the filter has one or more zeros at ?0.

Abstract: Electronic circuit arrangement for processing binary input values x?X of a word width n (n>1), with a first, second and third combinatory circuit components configured to process the binary input values x to form first, second and third binary output values. The arrangement further includes a majority voter element configured to receive the binary output values and provide a majority signal based on the received binary output values. The second and third combinatory circuit components are designed, as regards faults during processing of the binary input values x in the first combinatory circuit component, to process binary input values of a true non-empty partial quantity X1 of the quantity of binary input values X in a fault-tolerant manner and process binary input values of a further non-empty partial quantity X2 of the quantity of binary input values X different from the true non-empty partial quantity X1 in a fault-intolerant manner.

Abstract: A first transmitter transmits symbols. The leading edge of each symbol has the form Djexp{?jt}, where Dj is real, where ?j is selected from N possible values based on a current group of bits. The receiver has N filters whose transfer functions correspond respectively to the N possible values. The filter outputs are used to recover the group of bits. A second transmitter transmits an exponential symbol or a zero symbol depending on a current bit to be transmitted. The zero symbol has zero amplitude over the symbol period. The corresponding receiver applies threshold detection to estimate the transmitted bits. A third transmitter transmits a sequence of analog pulses with known interpulse time separation(s). The pulse sequence reflects from a moving object. A receiver captures the reflected pulse sequence. The interpulse separation(s) of the reflect pulse sequence is used to determine the radial velocity of the object.

Abstract: It is an object to provide a logic circuit which can be operated even when unipolar transistors are used. A logic circuit includes a source follower circuit and a logic circuit an input portion of which is connected to an output portion of the source follower circuit and all transistors are unipolar transistors. A potential of a wiring for supplying a low potential connected to the source follower circuit is lower than a potential of a wiring for supplying a low potential connected to the logic circuit which includes unipolar transistors. In this manner, a logic circuit which can be operated even with unipolar depletion transistors can be provided.

Abstract: A digital event generator includes a counter configured to provide at least one count value based on a clock signal, and a comparator configured to evaluate a first portion of a first count value to detect a near occurrence of an event, in response to a detection of a near occurrence of an event, evaluate a second portion of a second count value, and provide the event signal based on the evaluation and digital event time information. A switched mode energy converter uses said digital event generator.

Abstract: This description relates to an edge detector including a pulse generator configured to generate a first pulse when a first clock and a second clock are at a same logic level and generate a second pulse when the first clock and the second clock are at different logic levels. The edge detector further includes a first RC circuit configured to charge the first pulse and a second RC circuit configured to charge the second pulse. The edge detector further includes a circuitry that, based on a width of the first pulse or of the second pulse, is configured to provide a select signal to select an edge of the second clock for triggering.

Abstract: A laser source assembly (210) for generating an assembly output beam (212) includes a first laser source (218A), a second laser source (218B), and a dispersive beam combiner (222). The first laser source (218A) emits a first beam (220A) having a first center wavelength, and the second laser source (218B) emits a second beam (220B) having a second center wavelength that is different than the first center wavelength. The dispersive beam combiner (222) includes a common area 224 that combines the first beam (220A) and the second beam (220B) to provide the assembly output beam (212). The first beam (220A) impinges on the common area (224) at a first beam angle (226A), and the second beam (220B) impinges on the common area (224) at a second beam angle (226B) that is different than the first beam angle (226A). Further, the beams (220A) (220B) that exit from the dispersive beam combiner (222) are substantially coaxial, are fully overlapping, and are co-propagating.

Abstract: A trigger signal detection apparatus includes: a clock gating circuit which is supplied with a trigger signal and a clock signal and outputs the clock signal; a trigger signal processing circuit which outputs a first signal only for a predetermined time when the clock signal is supplied from the clock gating circuit; a counter which operates in response to the trigger signal, thus outputting a count value of the clock signal; and a time set-up circuit which outputs a second signal to the trigger signal processing circuit when count value supplied from the counter reaches a preset value, and the trigger signal processing circuit stops outputting the first signal when the trigger signal processing circuit receives the second signal.

Abstract: Provided are a lock detection circuit and a lock detecting method. The lock detection circuit includes two delay devices, four flip-flops and two logic gates, and can accurately detect a lock state of a phase locked loop (PLL) circuit. Therefore, the lock detection circuit can be implemented in a simple structure, and as a result, the lock detection circuit can be compact in size and can consume less electric power. Also, the lock detecting method enables lock detection process to be simpler, so that a lock state can be detected within a short time period.

Abstract: There is provided a digital lock detector and a frequency synthesizer using the same. The digital lock detector includes a comparator unit receiving a plurality of control bits, and generating a bit signal to notice a lock condition of the plurality of control bits; a delay cell block generating a plurality of delay signals based on the bit signal, and outputting a clock signal by combining the bit signal and the plurality of delay signals; and a detection unit detecting a shift time of the clock signal, and generating a lock indication signal according to the detection result.

Abstract: A first embodiment of the present invention relates to a frequency and phase locked loop (FPLL) synthesizer having a frequency-locked loop (FLL) operating mode and a phase-locked loop (PLL) operating mode. The FLL operating mode is used for rapid coarse tuning of the FPLL synthesizer and is followed by the PLL operating mode for fine tuning and stabilization of the frequency of an output signal from the FPLL synthesizer. A second embodiment of the present invention relates to a high resolution frequency measurement circuit that is capable of directly measuring the frequency of a high frequency signal to provide a high resolution frequency measurement using a lower frequency reference signal, and may include linear feedback shift register (LFSR) circuitry and LFSR-to-binary conversion circuitry. A third embodiment of the present invention relates to an FPLL having an FLL that includes the high resolution frequency measurement circuit.

Abstract: An electric circuit (30) for generating a clock-sampling signal (CLK) for a sampling device (31) comprises a clock generator (1, 40, 50, 60) for generating a plurality of clock signals (21-24, 51-54, 61-64), a correlation device (L) for correlating a characteristic signal section (LE) of a digital signal (DS) with the plurality of clock signals (21, 22, 23, 24, 51-56, 61-64), and a selecting device (MX) for selecting one of the clock signals (21, 22, 23, 24, 51-55, 61-64) as the clock-sampling signal (CLK) for the sampling device (31) on the basis of the correlation by the correlation device (L). The clock signals (21-24, 51-54, 61-64) have the same cycle duration (T) and are phase-shifted with respect to each other. The sampling device (31) subsequently samples the digital signal (DS) with the clock-sampling signal (CLK).

Abstract: Methods, devices and systems are provided for bit synchronizing multiple serial bitstreams (106) with a common clock signal (116). Activity occurring in each bitstream is detected (304) for each of a plurality of phases corresponding to cycles of the common clock signal. One of the plurality of phases is selected (308) for each of the serial bitstreams based upon the activity detected within the selected phase. Data is then extracted (322) from the selected phase for each of the serial bitstreams using the common clock signal to thereby bit synchronize each of the plurality of serial bitstreams to each other.

Abstract: The clock based voltage deviation detector of the present invention includes a pulse module, an indicator module and a correlation module. The pulse module generates a stream of reset pulses as a function of a clock signal. The indicator module generates a pass/fail indicator signal as a function of the reset pulse stream and a difference between an input signal and a reference voltage. The correlation module correlates an event (e.g., overvoltage or undervoltage) of the pass/fail indicator signal with a period of the clock signal at which the event occurred.

Abstract: A circuit for a parity tree is disclosed. In one embodiment, a circuit for a parity tree includes a pull-up circuit, a pull-down circuit, and a cross-couple circuit. The circuit, an XOR/XNOR circuit, includes both an output node and an inverted output node. For a given set of input signals, a pull-up path exists through the cross-couple circuit for one of the output node and the inverted output node, and wherein a pull-down path exists through the cross-couple circuit for the other one of the output node and the inverted output node.

Abstract: A method and a device for testing an embedded phase-locked loop (PLL) circuit are disclosed. A first clock signal of a first frequency is provided to an embedded phase-locked loop (PLL) circuit to be tested by a tester, so as to generate a PLL clock signal by the embedded PLL circuit in response to the first clock signal of the first frequency. The PLL clock signal is inputted to a test circuit along with a second clock signal of a second frequency. Then, the PLL clock signal is sampled with the second clock signal of the second frequency to generate a first sampled signal. The second frequency has a first correlation with the first frequency. Whether the embedded PLL circuit is in a normal operation condition is determined according to the first sampled signal.

Abstract: There is disclosed a phase detector and phase locked loop circuit in which a maximum operation frequency is high. The phase detector of the present invention comprises three S-R flip-flops each of which comprises two NAND gates, a NAND gate connected to an input terminal of the S-R flip-flop, and an inverter. Even when a phase difference between a reference clock signal and a clock signal is large, UP and DOWN signals can be outputted in accordance with the phase difference between both signals, and therefore the maximum operation frequency can be set to be higher than that of a conventional phase detector.

Abstract: In a differential output signal circuit suitable for restraining voltage overshooting/undershooting at differential output terminals due to lags in input signals and realizing stable and fast switching of differential input signals, a first differential pair of PMOS. transistors connected to a first current source and a second differential pair of NMOS transistors connected to a second current source are mutually connected at the differential output terminals, and a capacitor is connected between the connection nodes of the respective differential pairs and current sources. A transitional current path of the capacitor restrains voltage variations during differential input signal switching.

Abstract: An apparatus comprising a first arbiter cell, a second arbiter cell and a selection device. The first arbiter cell may be configured to lock if one or more requests are not resolved within a first predetermined time period. The second arbiter cell may be configured to dominate if the first arbiter cell enters a metastable state. The selection device may be configured to provide arbitration between the first and second arbiter cells within a second predetermined time period.

Abstract: Unlike prior art synchronizers and asynchronous arbiters that produce glitches in their outputs, the present invention provides a failure-free synchronizer that can sample an arbitrary and unstable inputs while maintaining zero probability of system failure. In particular, the invention addresses the synchronization failure problem and the lack of a metastable state in prior art synchronizers. Prior attempts have shown that the conditions rex and rex (where re is the control input and x is the data input) cannot be arbitrated. To overcome this, embodiments of the present invention introduce explicit signals a0 and a1 to hold the values rex and rex, respectively. One embodiment is a fast synchronizer. It has four main components—an input integrator, an inverting component, a SEL component and an output filter. Another embodiment of the present invention is a safe synchronizer that meets the strictest QDI design requirements. Other embodiments use a standard arbiter and a killable arbiter for arbitration.

Abstract: An apparatus comprising a first arbiter cell, a second arbiter cell and a selection device. The first arbiter cell may be configured to lock if one or more requests are not resolved within a first predetermined time period. The second arbiter cell may be configured to dominate if the first arbiter cell enters a metastable state. The selection device may be configured to provide arbitration between the first and second arbiter cells within a second predetermined time period.

Abstract: An apparatus comprising an arbiter cell and a delay logic circuit. The arbiter cell may be configured to receive a plurality of request signals and provide two or more grant signals. The delay logic circuit may be configured to interface the arbiter cell and force each of the plurality of request signals to be serviced in succession when a metastable state occurs.

Abstract: A method and apparatus for glitch protection for differential strobe input buffers in a source-synchronous environment. The present invention provides a solution to the problem of noise sensitivity of differential strobe input buffers in a source-synchronous environment, which may cause functional problems. The present invention enables the use of fully differential strobe signals to improve electrical performance of the source synchronous data transfers while removing the noise sensitivity problem associated with these signals. This is accomplished by providing a glitch protection circuit that provides protection against input glitches for a first predetermined period of time after each strobe transition. The present invention also provides a detection circuit that detects when both differential strobe signals are in the same logic state, which corresponds to a transition between bus masters (a dead cycle).

Abstract: An apparatus and method in an integrated circuit for detecting phase differences between clock signals originating from an oscillator circuit. The oscillator circuit is formed on a substrate, such that the oscillator circuit is coupled to coincidence elements responsive to clock signals originating from the oscillator circuit. In addition, a coincidence circuit is provided that includes the coincidence elements, such that the coincidence circuit provides output signals only in response to a change in all clock signals originating from the oscillator circuit. The apparatus includes a delay circuit responsive to the output signals, such that the delay circuit stretches delays between the clock signals. A phase detector is coupled to the delay circuit, such that the phase detector is responsible for detecting phase differences between the clock signals by identifying the delays.

Abstract: A clock recovery circuit includes a sampling phase detector and frequency detector. The sample values generated in the phase detection portion of the clock recovery circuit and applied as inputs to the frequency detector to allow for frequency “cycle slips” to be detected and corrected without requiring the use of a separate circuit.

Abstract: Arbiter circuits placed between two signal path segments on a semiconductor chip to measure the difference in propagation delay between those paths at their beginning and end. Each arbiter circuit has two inputs, and outputs signals indicating which of its inputs is the first to receive a leading edge of an input transition. External circuitry monitors the arbiter outputs, and accordingly controls the application of the input transitions. By varying the delay of the input signal paths, the relative propagation delay can be determined.

Abstract: A method for performing an “AND” operation on two independent inputs in a fail-safe manner includes cascading two charge pumps to output a condition signal representing the “AND'ed” state of the inputs. Each independent input has an active state asserted by a waveform of predetermined frequency and duty cycle, and an inactive fail-safe state asserted by a zero voltage. The method includes supplying power to a first charge pump, supplying power from the first charge pump to a second charge pump, and supplying each of the independent inputs to one of the respective charge pumps. A condition signal is output using an output from the second charge pump. Additionally, the method verifies the correctness of the frequency and duty cycle of each independent input using a cross connection scheme. This method provides a high-power, low-loss, and low-cost electrical circuit for operating devices responding to specific voltages, for example, vital relays.

Abstract: A device which reduces jitter and narrows the frequency spectrum of a jitter-ridden clock signal includes a basic unit having a plurality of series connected delay elements outputs from each delay element are all connected to an AND/NAND gate. A front end of the device locates missing clock pulses and ensures regular clock pulses are relayed to the remainder of the device. A succeeding section including plural basic units hones the signal such that jitter elements are removed. By the output of this section time duty cycles are uneven, a positive edge triggered flip-flop is then used to obtain 50% duty cycles at the expense of halving the clock signal's frequency. Optionally a frequency doubler can be employed to regain the clock signal's original frequency.

Abstract: Interrogator for an electronic identification system having a first oscillator arranged to vary in frequency in accordance with the frequency of a received signal, a second oscillator arranged to vary in accordance with the frequency of the first oscillator after a delay of a number of cycles of the received signal, a phase discriminator for detecting the phase difference between respective output signals of the first and second oscillators and a phase-change detector arranged to determine the frequency at which the phase changes occur. In this way, a modulation frequency of the received signal can be determined.

Abstract: Load-monitoring feedback is used to maintain the slew rate of a line driver circuit at a prescribed rate that is independent of the effective load of the line being driven. This load-monitoring feedback control makes it possible to drive the line with an amplified output signal that faithfully tracks the input signal and conforms with prescribed slew rate and rise/fall time specifications, irrespective of characteristics of the signal line, which may vary over a specified range of component values. In a first embodiment, slew rate control is effected by increasing or decreasing the amount of charge on a reference capacitor and thereby the drive current to an output driver FET, in accordance with the change in state of the output of an output terminal-monitoring voltage threshold comparator relative to termination of a prescribed (one-shot established) time window.

Abstract: When an edge detecting unit detects a falling edge of a digital audio broadcasting (DAB) signal, a time instant of a timer, which has a periodic characteristic, is stored via a calculating unit into a memory. If there is one piece of data continued a number of times, when an output value of a timer becomes a value of this data offset by a frame time period, the calculating unit resets the timer. Subsequently, when the value of the timer becomes equal to the period length T, the calculating unit resets the timer and at the same time, outputs an L level to an output terminal only during a preselected time period after the timer is set to 0. Accordingly, even when another signal is mixed into a frame synchronizing signal of a DAB signal, the synchronizing signal timing is detected without increasing the time required to detect a frame header.

Abstract: A method and apparatus for calibrating a programmable delay in a timing circuit of a gamma camera detector are provided. The programmable delay has an error, the value of which is to be determined. An input signal that is applied as input to the programmable delay is simultaneously applied as input to a precision fixed delay. The fixed delay has a delay value within the programmable range of the programmable delay, but has an error that is substantially smaller than that of the programmable delay. The output of the programmable delay is applied to one input of a decision circuit, and the output of the fixed delay is applied to another input of the decision circuit. The delay of the programmable delay is initially programmed to a value that is substantially greater than the delay of the fixed delay, and input pulses are then applied to both delays.

Abstract: Arbiter circuits placed between two signal path segments on a semiconductor chip to measure the difference in propagation delay between those paths at their beginning and end. Each arbiter circuit has two inputs, and outputs signals indicating which of its inputs is the first to receive a leading edge of an input transition. External circuitry monitors the arbiter outputs, and accordingly controls the application of the input transitions. By varying the delay of the input signal paths, the relative propagation delay can be determined.

Abstract: A method and apparatus for glitch protection for differential strobe input buffers in a source-synchronous environment. The present invention provides a solution to the problem of noise sensitivity of differential strobe input buffers in a source-synchronous environment, which may cause functional problems. The present invention enables the use of fully differential strobe signals to improve electrical performance of the source synchronous data transfers while removing the noise sensitivity problem associated with these signals. This is accomplished by providing a glitch protection circuit that provides protection against input glitches for a first predetermined period of time after each strobe transition. The present invention also provides a detection circuit that detects when both differential strobe signals are in the same logic state, which corresponds to a transition between bus masters (a dead cycle).

Abstract: An exclusive OR circuit is provided which detects whether or not a preceding-stage logical output value and a subsequent-stage logical output value agree. When these logical output values are found to agree, a NAND circuit functions to cut off the supply of a clock signal to a first and second switch circuits and to a latch circuit. Accordingly, when there occur no data changes between clock signal cycles, in a switch circuit and a latch circuit both arranged between each stage of a pipeline, the charge/discharge of the capacitance of gate electrodes of transistors forming these circuits is prevented, thereby reducing power consumption.

Abstract: A semiconductor integrated circuit, having circuit blocks to be evaluated in AC performance, includes a first circuit for inputting a first signal and a second signal generated in the interior of the semiconductor integrated circuit. The first circuit outputs a transient current when the first signal and the second signal change simultaneously. In the semiconductor integrated circuit, the transient current (third signal) is output to a external terminal of the semiconductor integrated circuit for evaluating the AC performance of the block.

Abstract: A system for clamping a clock signal line that prevents clock glitching is disclosed. The system is comprised of a plurality of logic gates which generates a signal to clamp the clock signal line only on the occurrence of the clock signal line being low, a clock clamping signal 26 is generated indicating that a peripheral device wants to clamp the clock signal line, and a start condition is detected indicating that the clock signal line may be clamped.

Abstract: A means and method for testing high speed phase locked loops (13) in an integrated circuit (12) at a test frequency lower than the operation speed of the phase locked loop (13). A test circuit portion (10) repeatedly tests for a zero level (42) of a recover clock signal (34) from the phase locked loop (13) and a latching flip flop (26) is set to provide a lock indication output (30) as long as repeated samples, taken at a test time (38) continue to indicate a zero level (42) of the recover clock signal (34). The test time (38) is the leading edge (40) of a reference clock signal (36) provided from an external source at a reference clock input (28) to the integrated circuit (12).

Abstract: In a frequency-to-voltage converting circuit, a clamping frequency is maintained constant without being adversely influenced by circuit constants, and temperature characteristics. The frequency-to-voltage converting apparatus has voltage converting means for converting a frequency of an input pulse signal into a voltage, arranged by frequency judging means for judging whether or not the frequency of the input pulse signal reaches a predetermined clamping frequency. Setting pulse signal generating means outputs a setting pulse signal having the clamping frequency, and means for causing the voltage converting means to convert the frequency of the input pulse signal into the voltage when the frequency of the input pulse signal does not reach the clamping frequency based on a judgement result of the frequency judging means.

Abstract: A synchronization signal detector for detecting synchronization signals or frame synchronization signals recorded on a recording medium includes a binary-valued signal detector for translating RF signals into binary-valued signals, an edge detection circuit for extracting edge portions of the binary-valued signals, a counter for counting the number of clocks generated by an external source between the edge portions, a number of latch circuits for holding successive clock count values between the edge portions and for successively shifting the clock values held by them, value coincidence circuits for comparing the numbers of clocks between transitions of the synchronization patterns and the clock count values held by the counter and the latch circuits and for outputting a signal indicating a coincidence in case of complete coincidence between the numbers of clocks and the clock count values and an AND circuit for taking a logical sum of the outputs of the value coincidence circuits and the edge detector for pr

Abstract: It is an object of the present invention to provide a phase comparator which can compare phase at high speed with simple structure. The phase is compared by a precharge type NAND gate including transistors (Q35-Q37). The result of comparison in the NAND gate is then outputted only in a period in which the input clock CLKref is at "1" by the NAND gate (NA 15), and thus the phase lag of the internal clock CLKint with respect to the input clock CLKref is detected. Phase lead of the internal clock CLKint with respect to the input clock CLKref is compared with interchanged relation of clocks inputted to a phase detecting portion (PD 2). Phase comparison can be made at high speed with a simple circuit including the precharge type NAND gate and the NAND gate (NA 15).

Abstract: A ballistic optical camera trigger having an integrated circuit capable of onverting light to a proportional frequency, wherein the integrated circuit has a fast response time and a wide dynamic range which allows it to sense positive or negative changes in light fast enough to trigger without delay for high speed imaging without computational delays or jitter causing interference. The frequency output of the integrated circuit is tracked by a phase lock loop/voltage controlled oscillator to allow it to follow slow changes in light, but not fast changes in light caused by, for example, a projectile such as a bullet. The frequency output from the integrated circuit is provided to one input of a logic gate which receives at another input thereof, a shaped pulse from the phase lock loop/voltage controlled oscillator circuit, wherein the output of the logic gate is applied to a one-shot for outputting a trigger signal.

Abstract: An arbiter circuit for determining priority as between two or more competing request signals and applicable for use in a memory system having a number of memories operating independently without interfering with one another. For each of a number of memories, a receiving circuit 10(i) and an arbitration circuit 12(i) with standardized configurations are allotted. Common memory cycle clock pulse ARB-CLK is sent from memory cycle generator 16 to all of arbiter units 14(1)-14(N) . From the arbiter units 14(1)-14(N) , the commands for the respective memories are output in synchronization to each other based on memory cycle clock pulse ARB-CLK.

Abstract: A circuit is provided for filtering asynchronous metastability. The circuit includes two or more output lines that provide signals indicative of the assertion of control or data input signals at a plurality of input lines. Despite the simultaneous assertion of two or more input signals, the circuit prevents the simultaneous assertion of more than one output signal, thereby preventing adverse effects within a digital system connected to the circuit.

Abstract: Phase of first and second signals is compared by producing an output signal in the event of a predetermined phase relationship between the first and second signals and clearing the output signal at a predetermined phase during the cycle of the second signal regardless of the state of the first signal.

Abstract: A semiconductor integrated circuit is operative in a plurality of different modes. A plurality of select signals whose number corresponds to modes selected from a plurality of different modes are outputted. In response to the select signals, it is detected whether at least two operation modes are selected simultaneously. If so, a detection signal is outputted. In response to this detection signal, the operation of the semiconductor integrated circuit is stopped. Further, in response to the select signal, the semiconductor integrated circuit is activated in a mode by means of a predetermined select signal of these select signals. Further, in response to these select signals, the selected mode can be detected.