Logarithmic Patents (Class 327/350)
  • Patent number: 11927479
    Abstract: A smart contact lens (400) for detecting a ratiometric change in an incident light (126) intensity is provided, including one or more, preferably concentric, rings (410-1, 410-2, . . . , 410-N) of a liquid crystal display, LCD, type, each ring being operable between a state having a lower attenuation of light and a state having a higher attenuation of light; a circuit (420, 100, 101) for detecting a ratiometric change in an incident light intensity; and a controller (430) configured to operate the one or more rings based on an intensity of an incident light and to, as a response to the circuit (420, 100, 10 101) detecting a ratiometric change in the intensity of the incident light from a higher intensity state to a lower intensity state indicating that at least a beginning of a blinking of an eye of a user has occurred, initiate a re-polarization of the one or more rings. A method of operating the smart contact lens and various uses of the circuit are also provided.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: March 12, 2024
    Assignees: IMEC VZW, STICHTING IMEC NEDERLAND
    Inventors: Chris Van Liempd, Andres Felipe Vasquez Quintero, Herbert De Smet
  • Patent number: 11822359
    Abstract: A current-balanced voltage source may include two regulated voltage sources, each having an input and an output, and an amplifier to receive a control voltage at a positive input and a feedback voltage at a negative input. The output of each amplifier is coupled to the input of the respective regulated voltage source. The outputs of the regulated voltage sources are coupled together to source a current to a load. A differential amplifier may include positive and negative differential inputs, and positive and negative differential outputs. The positive differential input is coupled to the output of the first regulated voltage source and the negative differential input is coupled to the output of the second regulated voltage source. The positive differential output provides the feedback to the first regulated voltage source, and the negative differential output provides the feedback to the second regulated voltage source.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: November 21, 2023
    Assignee: ACACIA COMMUNICATIONS, INC.
    Inventors: Yuval Shohet, Robert Manlick
  • Patent number: 11502655
    Abstract: A logarithmic amplifier circuit includes an adaptive gain amplifier circuit and a transistor. The adaptive gain amplifier circuit includes a gain stage and a diode. The gain stage includes an input terminal, and an output terminal. The diode includes a cathode terminal coupled to the output terminal, and an anode terminal coupled to a common terminal. The transistor includes a first terminal coupled to the input terminal, a second terminal coupled to the common terminal, and a third terminal coupled to the output terminal.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: November 15, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Martijn Fridus Snoeij, Marco Corsi
  • Patent number: 11321543
    Abstract: A logarithmic amplifier includes a logarithmic current preamplifier circuit and logarithmic amplifier circuit. The logarithmic current preamplifier circuit includes an inverting input terminal, an output terminal, and a first diode. The first diode is coupled between the inverting input terminal of the logarithmic current preamplifier circuit and the output terminal of the logarithmic current preamplifier circuit. The logarithmic amplifier circuit includes an inverting input terminal, an output terminal, and a second diode. The inverting input terminal of the logarithmic amplifier circuit is coupled to the output terminal of the logarithmic current preamplifier circuit. The second diode is coupled between the inverting input terminal of the logarithmic amplifier circuit and the output terminal of the logarithmic amplifier circuit.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: May 3, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Vadim Valerievich Ivanov
  • Patent number: 11213226
    Abstract: Methods and devices for providing application specific integrated circuit architecture for a two electrode analyte sensor or a three electrode analyte sensor are provided. Systems and kits employing the same are also provided.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: January 4, 2022
    Assignee: ABBOTT DIABETES CARE INC.
    Inventors: Martin J. Fennell, Jean-Pierre Cole, Theodore John Kunich, Udo Hoss, Benjamin Jay Feldman, Zenghe Liu
  • Patent number: 11169558
    Abstract: Provided is a logarithmic current-to-voltage conversion circuit having a temperature compensation function. The circuit includes a logarithmic current-to-voltage conversion buffer unit, a positive temperature coefficient compensation unit and a self-heating unit. The logarithmic current-to-voltage conversion buffer unit is provided with a reference circuit consistent with a basic logarithmic circuit. A temperature coefficient is reflected by a difference value ?Vbe between an output of the basic logarithmic circuit and an output of the reference circuit. The positive temperature coefficient compensation unit is provided with a voltage-to-current conversion circuit at a first stage and a current mirror at a second stage and outputs a voltage Vout through an resistor R2. The positive temperature coefficient compensation unit is connected to ?Vbe.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: November 9, 2021
    Assignee: 3PEAK INC.
    Inventor: Chuanbo Shi
  • Patent number: 11156647
    Abstract: Techniques, systems, architectures, and methods for estimating the rise time of a pulse for multi-channel and signal channel cases involving an optimization system and method that can be solved iteratively based on sparse priors for a wide span of signal-to-noise ratios.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: October 26, 2021
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventor: Masoud Farshchian
  • Patent number: 10979038
    Abstract: A method for in-phase (I) and quadrature (Q) signal generation is disclosed. The method may include a first stage receiving a differential input signal. The first stage may also generate first differential in-phase and quadrature output signals, which may be sent by the first stage to a second stage. The second stage may generate second differential in-phase and quadrature output signals, which may have amplitude and phase mismatches less than an amplitude and phase mismatches of the first differential output signals. The second stage may then output the second differential I/Q output signals.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: April 13, 2021
    Assignee: Georgia Tech Research Corporation
    Inventors: Milad Frounchi, John D. Cressler
  • Patent number: 10956687
    Abstract: A logarithmic amplifier includes a logarithmic current preamplifier circuit and logarithmic amplifier circuit. The logarithmic current preamplifier circuit includes an inverting input terminal, an output terminal, and a first diode. The first diode is coupled between the inverting input terminal of the logarithmic current preamplifier circuit and the output terminal of the logarithmic current preamplifier circuit. The logarithmic amplifier circuit includes an inverting input terminal, an output terminal, and a second diode. The inverting input terminal of the logarithmic amplifier circuit is coupled to the output terminal of the logarithmic current preamplifier circuit. The second diode is coupled between the inverting input terminal of the logarithmic amplifier circuit and the output terminal of the logarithmic amplifier circuit.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: March 23, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Vadim Valerievich Ivanov
  • Patent number: 10684634
    Abstract: A system and method for detecting and compensating for temperature effects in a device having a power supply and a remote node. The system includes a power supply unit having an adjustable voltage output and a feedback circuit. The voltage output is adjusted based on the output of the feedback circuit. A power path is coupled to the power supply unit. The power path has power connectors to supply voltage from the power supply unit to a remote node. The remote node is operable to sense a voltage drop of the power path at the remote node associated with temperature effects on the power connectors. An adjustable resistor has an output coupled to the feedback circuit. A controller is coupled to the remote node and the adjustable resistor. The controller determines a resistance value to compensate for the temperature effects and sets the adjustable resistor to change the power output.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: June 16, 2020
    Assignee: QUANTA COMPUTER INC.
    Inventors: Chih-Wei Yang, Chih-Hao Chang, Ching-Jung Liu
  • Patent number: 10419833
    Abstract: An optical receiver of an optical link having: a photodiode coupled between a detection node and a first supply voltage rail, the photodiode being adapted to receive an optical clock signal including pulses; a switch coupled between the detection node and a second supply voltage rail; and a first transistor coupled by its main conducting nodes between the second supply voltage rail and a first output node and having its control node coupled to the detection node, wherein the switch is controlled based on a voltage at the first output node.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: September 17, 2019
    Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventor: Robert Polster
  • Patent number: 10331571
    Abstract: An address control circuit includes a setting terminal connectable to a ground potential, a time constant setting circuit connected to the setting terminal, and a control unit connected to the time constant setting circuit and configured to set an address for serial communication. The time constant setting circuit includes a resistive element disposed between the setting terminal and the control unit and configured to protect the control unit against overvoltage. The control unit outputs a voltage to the time constant setting circuit, and sets an address at a predetermined timing based on the voltage input from the time constant setting circuit when a predetermined time has passed after the output of the voltage is stopped.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: June 25, 2019
    Assignee: MINEBEA MITSUMI INC.
    Inventors: Kazuo Takada, Shigeki Miyaji, Yoshiaki Motoyama, Yasuyuki Hasegawa
  • Patent number: 9746865
    Abstract: Provided is a current-to-voltage conversion circuit, including: an input/output node configured to input a current signal including a direct current component and an alternating current component, and to output a voltage based on the current signal; an amplification unit configured to input the voltage of the input/output node; an extraction unit configured to output a voltage based on a direct current component of a voltage output from the amplification unit; a first current supply unit configured to supply a current based on the voltage output from the extraction unit to the input/output node; and a second current supply unit configured to supply a current based on the alternating current component of the current signal to the input/output node. The current supplied by the second current supply unit corresponds to a difference between a current of the current signal and the current supplied by the first current supply unit.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: August 29, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Naoki Isoda
  • Patent number: 9374064
    Abstract: A series-structure, parallel-structure and combined structure of micro-step resistance network circuits is disclosed. Micro-step resistance is maintained, while the programming switches on-state resistance impact and its VC and TC effect are minimized. The programming switch area size is greatly reduced as compared to conventional systems.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: June 21, 2016
    Assignee: Texas Instruments Incorporated
    Inventor: Qunying Li
  • Patent number: 9319510
    Abstract: A personalized (i.e., speaker-derivable) bandwidth extension is provided in which the model used for bandwidth extension is personalized (e.g., tailored) to each specific user. A training phase is performed to generate a bandwidth extension model that is personalized to a user. The model may be subsequently used in a bandwidth extension phase during a phone call involving the user. The bandwidth extension phase, using the personalized bandwidth extension model, will be activated when a higher band (e.g., wideband) is not available and the call is taking place on a lower band (e.g., narrowband).
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: April 19, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Lae-Hoon Kim, Sang-Uk Ryu, Jongwon Shin
  • Patent number: 9289977
    Abstract: An apparatus includes an amplifier that employs a bias current to drive a print nozzle. A current reduction module can be employed to offset the bias current and to reduce a portion of the bias current from appearing in a subsequent stage to the amplifier in order to mitigate power in the subsequent stage.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: March 22, 2016
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Andrew Van Brocklin
  • Patent number: 9285820
    Abstract: A voltage reference circuit comprises a plurality of ?VBE cells, each comprising four bipolar junction transistors (BJTs) connected in a cross-quad configuration and arranged to generate a ?VBE voltage. The plurality of ?VBE cells are stacked such that their ?VBE voltages are summed. A last stage is coupled to the summed ?VBE voltages and arranged to generate one or more VBE voltages which are summed with the ?VBE voltages to provide a reference voltage. This arrangement serves to cancel out first-order noise and mismatch associated with the two current sources present in each ?VBE cell, such that the voltage reference circuit provides ultra-low 1/f noise in the bandgap voltage output.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: March 15, 2016
    Assignee: Analog Devices, Inc.
    Inventors: Arthur J. Kalb, John Sawa Shafran
  • Patent number: 9065691
    Abstract: An embodiment of the invention provides a sliced transmitter front-end (TX FE). The sliced TX FE includes first TX FE slices and a second TX FE slice that are connected in parallel. As a whole the first TX FE slices contributes a high-gain section to a superimposed gain range of the sliced TX FE. The second TX FE slice has a gain range that constitutes a low-gain section of the superimposed gain range of the sliced TX FE. A minimum gain of the gain range of the second TX FE slice is smaller than a minimum gain of the high-gain section.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: June 23, 2015
    Assignee: MEDIATEK INC.
    Inventors: Hsiang-Hui Chang, Augusto Marques, Li-Shin Lai, Chih-Hao Sun, George Chien
  • Publication number: 20150137868
    Abstract: A CMOS logarithmic current generator includes current mode circuitry having a design principle based on a Taylor's series expansion that approximates an exponential function. A MOSFET circuit provides a function generator core cell having a biasing current Ib. The FETs of the circuit are matched and are biased in the weak inversion region. Additional transistors are used to convert a pair of input currents to a pair of voltages to provide an output current based upon a current mode logarithmic function. The biasing current Ib can be varied to provide a variable gain in the circuit.
    Type: Application
    Filed: November 18, 2013
    Publication date: May 21, 2015
    Applicant: KING FAHD UNIVERSITY OF PETROLEUM AND MINERALS
    Inventors: MUNIR A. AL-ABSI, KARAMA M. AL-TAMIMI
  • Patent number: 8975951
    Abstract: Electronic apparatus that can suppress the operating voltage of an incorporated semiconductor integrated circuit to a low voltage is provided. Electronic apparatus 1 includes a power supply circuit 13, a semiconductor integrated circuit 10 that operates by a supply voltage supplied from the power supply circuit 13, and a temperature sensor 11 that measures the temperature of the semiconductor integrated circuit 10. The power supply circuit 13 decreases the supply voltage according to a rise in the measured temperature.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: March 10, 2015
    Assignees: Sony Corporation, Sony Computer Entertainment Inc.
    Inventors: Takeshi Inoue, Shinji Takashima
  • Patent number: 8868017
    Abstract: A received signal strength indicator is provided. The received signal strength indicator includes a plurality of differential amplifiers forming an amplifier chain for amplifying differential signals and a plurality of rectifiers for rectifying signals output from the plurality of differential amplifiers and the differential signals, and a low pass filter for combining the signals rectified by the plurality of rectifiers to output received signal strength. Each rectifier includes a class AB voltage-current converter for converting a differential voltage into a current, and two triode transistors.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: October 21, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Hoyong Kang, Nguyen Trung Kien, Se Han Kim, Tae Joon Park, Wun-Cheol Jeong, Chang Sub Shin, In Hwan Lee, Cheol Sig Pyo
  • Publication number: 20140266420
    Abstract: A logarithmic amplifier (LDA) is described that includes an amplifier configured to oscillate a modulated input signal, a feedback establishing a 180 degree phase shift between the amplifier input and the output and maintaining oscillation of the input signal, a parallel resonant circuit connected to the amplifier output causing the amplifier to resonate at or around a center frequency, and a controller connected to the amplifier input cyclically terminating oscillation of the input signal each time a pre-determined threshold of current is detected, the controller including a low pass filter configured to generate a second output signal having a repetition frequency. The LDA may be used for AM with or without a PLL and/or a superhetrodyne. The LDA may be implemented as a mixer and used for phase demodulation. The LDA may be used for phase demodulation. The LDA may be used in place of a low noise amplifier.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 18, 2014
    Inventors: Forrest Brown, Patrick Rada, Alexandre Dupuy
  • Patent number: 8786352
    Abstract: A threshold computation apparatus obtains estimated interference power for an uplink from a terminal to a base station; a predetermined communication quality value necessary for the uplink; a maximum value of transmission power of the terminal; and transmission power of the base station for a downlink from the base station to the terminal. The apparatus subtracts a logarithmic value of the maximum value of the transmission power of the terminal from a logarithmic value of the transmission power of the base station for the downlink; adds a logarithmic value of the communication quality value and a logarithmic value of the estimated interference power to a result of the subtraction; and determines a result of the addition to be a logarithmic value of received power at the terminal; and computes a threshold based on the logarithmic value of the received power at the terminal and predetermined conditions.
    Type: Grant
    Filed: February 22, 2012
    Date of Patent: July 22, 2014
    Assignee: KDDI Corporation
    Inventors: Toshihiko Komine, Toshiaki Yamamoto, Satoshi Konishi
  • Patent number: 8779833
    Abstract: The current-mode CMOS logarithmic function circuit provides an ultra-low power circuit that produces an output current proportional to the logarithm of the input current. An OTA (operational transconductance amplifier) constructed from CMOS transistors, in combination with two PMOS transistors configured in weak inversion mode for providing a reference voltage input and a voltage input from the input current to the OTA, provides the circuit with a high dynamic range, controllable amplitude, high accuracy, and insensitivity to temperature variation.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: July 15, 2014
    Assignee: King Fahd University of Petroleum and Minearals
    Inventors: Karama M. Al-Tamimi, Munir Ahmed Al-Absi
  • Patent number: 8564308
    Abstract: A signal acquisition system has a signal acquisition probe having probe tip circuitry coupled to a resistive center conductor signal cable. The resistive center conductor signal cable of the signal acquisition probe is coupled to a compensation system in a signal processing instrument via an input node and input circuitry in the signal processing instrument. The signal acquisition probe and the signal processing instrument have mismatched time constants at the input node with the compensation system having an input amplifier with feedback loop circuitry and a shunt pole-zero pair coupled to the input circuitry providing pole-zero pairs for maintaining flatness over the signal acquisition system frequency bandwidth.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: October 22, 2013
    Assignee: Tektronix, Inc.
    Inventors: Josiah A. Bartlett, Ira G. Pollock, Daniel G. Knierim, Lester L. Larson, Scott R. Jansen, Kenneth P. Dobyns, Michael Duane Stevens
  • Publication number: 20130147538
    Abstract: Disclosed is a digital pre-distortion device which includes a pre-compensation lookup table which outputs a first input value and a second input value adjacent to an input signal, a first distortion value corresponding to the first input value, and a second distortion value corresponding to the second input value; and a function generator which generates a pre-distortion function based on the first and second input values and the first and second distortion values and generates a pre-distortion value corresponding to the input signal from the pre-distortion function.
    Type: Application
    Filed: July 27, 2012
    Publication date: June 13, 2013
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Jung Hoon OH, Joon Hyung KIM, JAE HO JUNG, HYUN KYU CHUNG
  • Publication number: 20120218021
    Abstract: A threshold computation apparatus obtains estimated interference power for an uplink from a terminal to a base station; a predetermined communication quality value necessary for the uplink; a maximum value of transmission power of the terminal; and transmission power of the base station for a downlink from the base station to the terminal. The apparatus subtracts a logarithmic value of the maximum value of the transmission power of the terminal from a logarithmic value of the transmission power of the base station for the downlink; adds a logarithmic value of the communication quality value and a logarithmic value of the estimated interference power to a result of the subtraction; and determines a result of the addition to be a logarithmic value of received power at the terminal; and computes a threshold based on the logarithmic value of the received power at the terminal and predetermined conditions.
    Type: Application
    Filed: February 22, 2012
    Publication date: August 30, 2012
    Inventors: Toshihiko KOMINE, Toshiaki Yamamoto, Satoshi Konishi
  • Patent number: 8207776
    Abstract: An embodiment of a logarithmic circuit may include a logging transistor, a guard circuit arranged to force an input current into an input terminal of the logging transistor, and a positioning circuit arranged to maintain a voltage of the logging transistor. The guard and positioning circuits may include first and second feedback loops, respectively. Another embodiment of a logarithmic circuit may include a logging transistor arranged to generate a logarithmic output in response to an input current, and a feedback loop arranged to provide adaptive compensation to the logging transistor. The feedback loop may be arranged to provide compensation in response to the magnitude of the input current. Another embodiment of a logarithmic circuit may include first and second logging transistors having collectors arranged to receive input currents, and first and second feedback amplifier arranged to drive emitters of the logging transistors.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: June 26, 2012
    Assignee: Analog Devices, Inc.
    Inventor: Barrie Gilbert
  • Patent number: 8183906
    Abstract: The invention relates to an arrangement comprising a logarithmizing unit and a subtracting unit, wherein the subtracting unit has an output at which a voltage value linearly proportional to the temperature can be tapped off.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: May 22, 2012
    Assignee: Infineon Technologies AG
    Inventors: Roland Thewes, Ralf Brederlow
  • Publication number: 20120119813
    Abstract: A digital log gain to digital linear gain multiplier is disclosed. The digital log gain to digital linear gain multiplier includes a log gain splitter adapted to split a log gain input into an integer log part and a remainder log part. A log scale-to-linear scale converter is adapted to output a linear gain value in response to the integer log part and the remainder log part. A gain multiply circuit is adapted to multiply a digital signal by the linear gain value to output a gain-enhanced digital signal.
    Type: Application
    Filed: November 16, 2011
    Publication date: May 17, 2012
    Applicant: RF MICRO DEVICES, INC.
    Inventors: Nadim Khlat, Shanthi Prasad
  • Patent number: 8164377
    Abstract: A detector circuit includes a main path having a first detector to generate an output signal in response to an input signal, and a reference path having a second detector matched to the first detector to generate a reference signal in response to the input signal. The reference signal may be used to compensate the output signal for variations in operating frequency, temperature, or the like. The reference path may be arranged to reuse a signal available in the main path so that the signal applied to the second detector experiences the same operating effects as that applied to the first detector.
    Type: Grant
    Filed: February 14, 2006
    Date of Patent: April 24, 2012
    Assignee: Analog Devices, Inc.
    Inventor: Vincenzo DiTommaso
  • Patent number: 8055228
    Abstract: A received signal strength indicator according to an aspect of the invention may include a gain calibration section including a calibration limiter, a calibration load unit and a comparison and adjustment unit. The calibration load unit is connected to output terminals of the calibration limiter, and generating an output differential voltage whose gain is a unit gain when a predetermined input differential voltage is input to the calibration limiter, and a comparison and adjustment unit comparing the input differential voltage with the output differential voltage, and adjusting an output of a variable current source included in the calibration limiter so that the input differential voltage becomes identical to the output differential voltage.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: November 8, 2011
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Kyoung Seok Park, Hyun Hwan Yoo, Yoo Sam Na
  • Patent number: 8041056
    Abstract: A voltage supply circuit comprises a voltage control circuit for outputting a bias voltage control signal according to a set value based on a bias voltage of a sensor and a voltage generation circuit for generating the bias voltage to be applied to the sensor based on the bias voltage control signal.
    Type: Grant
    Filed: August 16, 2005
    Date of Patent: October 18, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroshige Kinoshita
  • Patent number: 8004341
    Abstract: An embodiment of a logarithmic circuit may include a logging transistor, a guard circuit arranged to force an input current into an input terminal of the logging transistor, and a positioning circuit arranged to maintain a voltage of the logging transistor. The guard and positioning circuits may include first and second feedback loops, respectively. Another embodiment of a logarithmic circuit may include a logging transistor arranged to generate a logarithmic output in response to an input current, and a feedback loop arranged to provide adaptive compensation to the logging transistor. The feedback loop may be arranged to provide compensation in response to the magnitude of the input current. Another embodiment of a logarithmic circuit may include first and second logging transistors having collectors arranged to receive input currents, and first and second feedback amplifier arranged to drive emitters of the logging transistors.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: August 23, 2011
    Assignee: Analog Devices, Inc.
    Inventor: Barrie Gilbert
  • Patent number: 7982527
    Abstract: A frequency mixer or modulator circuit that is reconfigurable through electronic programming among active and passive operation, and/or harmonic and sub-harmonic operation, and/or up-conversion and down-conversion, and/or no-overlap, off-overlap, and on-overlap mixing, and/or upper-sideband modulation and lower-sideband modulation. In one example, the frequency mixer or modulator circuit also includes automatic gain control.
    Type: Grant
    Filed: January 5, 2009
    Date of Patent: July 19, 2011
    Assignee: BitWave Semiconductor, Inc.
    Inventors: Geoffrey C. Dawe, Krenar Komoni
  • Patent number: 7969223
    Abstract: An embodiment of a logarithmic circuit may include a logging transistor, and a multi-tanh circuit arranged to provide temperature compensation to the logging transistor, where the multi-tanh circuit comprises a multiplicity of multi-tanh cells. In another embodiment, a logarithmic circuit may include a logging transistor, and a multi-tanh circuit arranged to provide temperature compensation to the logging transistor, where the multi-tanh circuit includes a first set of outputs arranged to provide an output signal and a second set of one or more outputs that are diverted.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: June 28, 2011
    Assignee: Analog Devices, Inc.
    Inventor: Barrie Gilbert
  • Patent number: 7952416
    Abstract: The intercept of a logarithmic amplifier is temperature stabilized by generating a signal having the form H log H where H is a function of temperature such as T/T0. The first H factor is cancelled, thereby generating a correction signal having the form Y log H. The cancellation may be implemented with a transconductance cell having a hyperbolic tangent function. The H log H function may be generated by a pair of junctions biased by one temperature-stable current and one temperature-dependent current. The pair of junctions and the transconductance cell may be coupled together in a translinear loop. A user-accessible terminal may allow adjustment of the correction signal for different operating frequencies.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: May 31, 2011
    Assignee: Analog Devices, Inc.
    Inventor: Vincenzo DiTommaso
  • Publication number: 20100237935
    Abstract: Disclosed is a logarithmic detector comprising: an amplifier element; means for setting a frequency of operation of the detector; and a controller, wherein an input signal to the amplifier element is arranged to cause an oscillation in the amplifier element, and the controller is operable to sense a pre-determined threshold, indicative of oscillation and, in response to sensing said threshold, to interrupt the oscillation of the amplifier such that the frequency of said interruption is proportional to the logarithm of the power of the input signal.
    Type: Application
    Filed: October 31, 2008
    Publication date: September 23, 2010
    Inventor: Forrest James Brown
  • Patent number: 7777552
    Abstract: An RF measurement system includes an envelope detector to extract the modulation envelope of the RF input signal. The resulting baseband envelope signal is then applied to a statistics extraction circuit which provides a precise measure of the modulation envelope. The statistics extraction circuit can be implemented with any number of lower-frequency precision measurement technologies because the high-frequency carrier portion of the signal is removed, and thus, the demands on the post-envelope extraction circuit are greatly reduced. In one embodiment, the envelope detector and statistics extraction circuit may be implemented as a logarithmic amplifier followed by an RMS-responding post-processing circuit to provide accurate power measurement.
    Type: Grant
    Filed: April 23, 2009
    Date of Patent: August 17, 2010
    Assignee: Analog Devices, Inc.
    Inventor: Barrie Gilbert
  • Patent number: 7683694
    Abstract: A logarithmic detector circuit including a drive circuit to receive a modulated input signal and generate a buffered modulated signal, a signal shaping circuit coupled to the drive circuit and configured to shape a voltage range of the buffered modulated signal to generate a shaped modulated signal, and a detecting circuit to detect the shaped modulated signal to generate an output signal substantially proportional to a logarithm of an amplitude of the modulated input signal.
    Type: Grant
    Filed: March 14, 2007
    Date of Patent: March 23, 2010
    Assignee: Quantance, Inc.
    Inventor: Mark R. Gehring
  • Publication number: 20100045246
    Abstract: An apparatus and method for measuring the source-side line voltage from a source potential transformer (PT) of a regulator during reverse power flow. A reverse power regulation algorithm (“Source Side PT”) is employed during reverse power operation of the tapchanger to energize a contact relay which switches the analog voltage input from the load side to the source side of the regulator. Voltage regulation then operates based on the measured source side voltage instead of the traditional calculation of the source side voltage based upon the load-side voltage and regulator type.
    Type: Application
    Filed: August 19, 2009
    Publication date: February 25, 2010
    Inventors: Timothy J. Bryant, Thaichong Li
  • Publication number: 20090322404
    Abstract: The invention relates to an arrangement comprising a logarithmizing unit and a subtracting unit, wherein the subtracting unit has an output at which a voltage value linearly proportional to the temperature can be tapped off.
    Type: Application
    Filed: March 13, 2009
    Publication date: December 31, 2009
    Inventors: Roland Thewes, Ralf Brederlow
  • Patent number: 7616044
    Abstract: The intercept of a logarithmic amplifier is temperature stabilized by generating a signal having the form H log H where H is a function of temperature such as T/T0. The first H factor is cancelled, thereby generating a correction signal having the form Y log H. The cancellation may be implemented with a transconductance cell having a hyperbolic tangent function. The H log H function may be generated by a pair of junctions biased by one temperature-stable current and one temperature-dependent current. The pair of junctions and the transconductance cell may be coupled together in a translinear loop. A user-accessible terminal may allow adjustment of the correction signal for different operating frequencies.
    Type: Grant
    Filed: April 14, 2007
    Date of Patent: November 10, 2009
    Assignee: Analog Devices, Inc.
    Inventor: Vincenzo DiTommaso
  • Publication number: 20090206907
    Abstract: A method is provided for the electronic processing of analog signals in thermaltronic device. The method accepts an analog input signal, e.g., an AC signal, at a thermaltronic device input and generates a thermal electric (TE) temperature having a first transfer function responsive to the input signal. As opposed to having a digital response, the transfer function is either linear or logarithmic. An analog output signal, e.g., an AC signal, is generated having a second transfer function responsive to the TE, which is likewise either linear or logarithmic.
    Type: Application
    Filed: September 24, 2008
    Publication date: August 20, 2009
    Inventor: Joseph Martin Patterson
  • Patent number: 7557636
    Abstract: A geometric ladder circuit produces a transfer function having substantially uniform steps measured in dB. Where the ladder has a plurality of substantially identical resistor rungs of a first resistance, one stile that is a conductor connecting the rungs, and another having a series of substantially identical resistors of a second resistance, then for identical currents injected at different rungs, the output signal at an end of the ladder is attenuated by a number of substantially equal steps, one for each rung between input and output. For a ladder with a base rung R, an output at an end opposite the base rung, stile resistors of resistance ?R, and other rungs all of resistance (1+(1/?))R, the step size is 20 log10(1+?).
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: July 7, 2009
    Assignee: Marvell International Ltd.
    Inventors: Alireza Shirvani-Mahdavi, George Chien
  • Patent number: 7453309
    Abstract: The intercept of a logarithmic amplifier is temperature stabilized by generating a signal having the form H log H where H is a function of temperature such as T/T0. The first H factor is cancelled, thereby generating a correction signal having the form Y log H. The cancellation may be implemented with a transconductance cell having a hyperbolic tangent function. The H log H function may be generated by a pair of junctions biased by one temperature-stable current and one temperature-dependent current. The pair of junctions and the transconductance cell may be coupled together in a translinear loop. A user-accessible terminal may allow adjustment of the correction signal for different operating frequencies.
    Type: Grant
    Filed: January 9, 2007
    Date of Patent: November 18, 2008
    Assignee: Analog Devices, Inc.
    Inventor: Vincenzo DiTommaso
  • Publication number: 20080278237
    Abstract: An embodiment of the present invention provides an RF log-amp detector, comprising a pre-amplifer at the input of the RF log-amp detector, a plurality of limiters with variable gain connected to the pre-amplifier, wherein the gain of the preamplifier is set to its minimum and the dynamic range is expanded by modifying the amplification gain of the plurality of limiters, thereby increasing the dynamic range and reducing accuracy, after which a coarse measurement of a power level is taken and wherein the RF log-amp detector then defines which pre-amplification level is required based on the course measurement to bring the signal at the output of the preamp within an optimum dynamic range of the log-amp and wherein the pre-amplification gain is then set while the gain of the plurality of limiters are set to their minimum value with the RF log-amp then performing a second measurement with higher accuracy and calculating the final measurement from fine measurements and the pre-amplification gain.
    Type: Application
    Filed: May 7, 2007
    Publication date: November 13, 2008
    Inventor: Guillaume Blin
  • Patent number: 7375576
    Abstract: A log circuit receives an operated current signal and a reference current signal at respective inputs and comprises an operand log circuit including a first bipolar semiconductor device and being configured to generate a first logarithmized signal on the basis of the operand current signal, a reference log circuit including a second bipolar semiconductor device and being configured to generate a second logarithmized signal on the basis of the reference current signal, and a differential-amplifier circuit receiving the first logarithmized signal and the second logarithmized signal, and outputting a differential-amplifier output signal in dependency on the first logarithmized signal and the second logarithmized signal.
    Type: Grant
    Filed: September 21, 2005
    Date of Patent: May 20, 2008
    Assignee: Infineon Technologies AG
    Inventor: Stefan Groiss
  • Patent number: RE47098
    Abstract: A USB-based isolator system conveys USB signals between a pair of galvanically isolated circuit systems and supports controlled enumeration by a downstream device on upstream USB signal lines. The isolator system provides a multi-mode voltage regulator to support multiple voltage supply configurations. The isolator system further provides control systems for each of the isolated circuit systems and provides robust control in a variety of start up conditions. Additionally, the isolator system includes refresh timers and watchdog mechanisms to support persistent operation but manage possible communication errors that can arise between the isolated circuit systems.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: October 23, 2018
    Assignee: Analog Devices, Inc.
    Inventors: Eric C. Gaalaas, Mark Stewart Cantrell
  • Patent number: RE47432
    Abstract: An output stage circuit includes: a first transistor, including a first terminal coupled to a first node, a second terminal coupled to an output terminal, a third terminal coupled to an input terminal for receiving an input voltage, and a fourth terminal coupled to a first power terminal for receiving a first voltage; a second transistor, including a first terminal coupled to a second node, a second terminal coupled to the output terminal, a third terminal coupled to the input terminal for receiving the input voltage, and a fourth terminal coupled to ground; and a current source, coupled to the output terminal for providing a constant current.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: June 11, 2019
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Ju-Lin Huang, Keko-Chun Liang, Chun-Yung Cho, Cheng-Hung Chen