Abstract: Methods and systems for calibrating clock skew in a SerDes receiver. A method includes detecting a skew in a clock with respect to an edge of a reference clock, based on a value sampled by the clock and a value sampled by the reference clock at an edge of a data pattern, for a first Phase Interpolator (PI) code; determining a count of the skew from a de-serialized data word including outcome values obtained based on values sampled by the clock and values sampled by the reference clock at a predefined number of edges of the data pattern; obtaining a skew calibration code corresponding to the first PI code, from a binary variable obtained by accumulating an encoded variable to a previously generated binary variable; and calibrating the skew by performing a positive phase shift or a negative phase shift to the clock based on the skew calibration code.

Abstract: A common mode filter and a power supply device having the same are provided. The common mode filter includes a first inductor having a first winding number, a second inductor facing the first inductor and having a second winding number, a first intermediate terminal branching from an intermediate portion of a coil of the first inductor, and a second intermediate terminal branching from an intermediate portion of a coil of the second inductor. The effects of two filters are obtained from one common mode filter and the volume is reduced, so that a light, thin, short, and short module is provided.

Abstract: In one embodiment, the present invention includes a mixer having various stages, including a transconductance stage with a differential transistor pair, a bias circuit, and a feedback circuit. The transistor pair can include a first transistor having a first terminal to receive a first input radio frequency (RF) voltage and to output a first RF current via a second terminal of the first transistor, and a second transistor having a first terminal to receive a second input RF voltage and to output a second RF current via a second terminal of the second transistor. In turn, the bias circuit is coupled to the second terminals of the transistors to provide a bias current to these transistors. The feedback circuit is in turn coupled to the second terminals of the transistors to generate a feedback signal corresponding to a common mode voltage at the second terminals of the transistors.

Abstract: Phase correction circuits and methods for reducing phase skew between multiphase clock signals and a semiconductor device including the circuit are provided. The semiconductor device includes a phase correction circuit and an output buffer. The phase correction circuit corrects phase skew between multiphase clock signals and generates skew-corrected clock signals. The output buffer outputs data in synchronization with the skew-corrected clock signals. The phase correction circuit includes a phase corrector, a replication output buffer, a phase detector, and a controller. The phase corrector corrects a duty cycle of a first clock signal, a duty cycle of a second clock signal, and phase skew between the first and second clock signals and generates skew-corrected first and second clock signals. The replication output buffer has the same structure as a data output buffer and outputs replication data in synchronization with the skew-corrected first and second clock signals.

Abstract: The device for detecting and tracking a status of a device under laser trim includes: a series connected string of trim tracking links; and a plurality of detecting devices wherein each detecting device is coupled in parallel with a corresponding trim tracking link. This device allows detection of laser beam to work surface misalignment and the termination of lasing before critical active circuit components can be damaged.

Abstract: In one embodiment, the present invention includes an apparatus having a threshold detector with a current comparator to determine if an input signal exceeds a threshold. The input signal may be obtained from a received optical signal and may be compared to a reference signal obtained from a hierarchical Schmitt trigger, in certain embodiments.

Abstract: An absolute value circuit includes an operational amplifier, the output of which is coupled to control inputs of complementary polarity transistors having current flow paths therethrough coupled in series with inputs of current mirror amplifier stages. A common node of the current flow paths through the transistors is coupled to an input of the operational amplifier to which a current waveform is applied. The current mirror amplifier stages are configured so as to provide like polarity output currents. The outputs of the current mirror amplifier stages are combined to produce an output current that corresponds to a full wave rectification or absolute value of an input current coupled to the operational amplifier.

Abstract: A received signal strength indicator operating at low intermediate of zero intermediate frequency is provided. The received signal strength indicator forms absolute values from an in-phase signal component and a quadrature signal component of a low or zero intermediate frequency signal that represents a received radio frequency signal. The absolute values are added. Logarithmic signal processing is performed either before absolute signal forming or after adding. Finally, low pass filtering is performed.

Abstract: A vector-signal processing circuit can be operated with low power consumption and can be configured so as to be cheap. Sensor signals in three-axial directions are individually rectified by full-wave-rectifier circuits individually formed by combining four diodes. Subsequently, the outputs of the above are added by an adder circuit and are further processed by a comparator, thereby generating digital signals. Forward-voltage-falling characteristics of the individual diodes used in the full-wave rectifier circuits are set to 0.3 V, and a threshold of the comparator is set to 0.6 V.

Abstract: A telephone line measurement circuit is disclosed for detecting a variation of a characteristic between a first and a second leads of a telephone line. The circuit comprises a first circuit having a first and a second inputs and an output. The circuit also has a second circuit having a first and a second inputs and an output. The first input of the first circuit and the second input of the second circuit are coupled to the first lead of the telephone line and the second input of the first circuit and the first input of the second circuit are coupled to the second lead of the telephone line. The outputs of the first and the second circuits are then coupled together to provide an output for the measurement circuit.

Abstract: An integrated circuit arrangement with a diode characteristic including a source-drain section of a first transistor arranged in the current path between the input and output sides of the arrangement; a first inverter stage with an output fed back to its input, and whose supply voltage is provided by the voltage on the output side of the circuit arrangement; a second inverter stage to the input of which the output signal from the first inverter stage is fed and whose supply voltage is provided by the voltage on the input side of the circuit arrangement; and a third inverter stage having an input to which the output signal from the second inverter stage is fed, whose voltage supply is provided by the voltage on the output side of the circuit arrangement, and whose output signal is fed to the gate electrode of the first transistor, and thus regulates the current flow in the current path of the circuit arrangement.

Abstract: A method and apparatus are provided for sensing a common mode signal of a differential circuit. A first full wave rectifier samples the differential signal and generates a first rectified signal. A second full wave rectifier samples the differential signal and generates a second rectified signal. An averaging circuit coupled to the first and second full wave rectifiers averages the first and second rectified signals and generates the common mode signal.

Abstract: An inputted signal applied to an input terminal of a detecting circuit is rectified in a positive amplitude range thereof by a rectifier block and stored in a capacitor. In a negative amplitude range, the electric energy stored in the capacitor is discharged through a load block. The rectifier block and the load block have equal impedances, and hence a time constant when the capacitor is charged is equal to a time constant when the capacitor is discharged. A DC signal outputted from an output terminal of the detecting circuit has a level which is the same as the average power level of the inputted signal. The detecting circuit is capable of outputting a DC signal which is accurately representative of the power level of the inputted signal.

Abstract: Addition is performed by a capacitive coupling or resistive coupling. A quantizing circuit is realized by plurality of thresholding circuits receiving an analog input voltages. Subtraction in performed by two MOSs of anti-polarity inputted analog input voltages to gates.

Abstract: In a full-wave rectifying circuit comprising a differential amplifier (20) differentially amplifies an input alternating current signal (V.sub.IN) to produce first and second amplified output voltages (V.sub.O1, V.sub.O2) and a voltage reference circuit (30) for generating a reference voltage (V.sub.REF), a differential pair circuit (40) carries out half-wave rectification on the first and the second amplified output voltages on the basis of the reference voltage to obtain first and second half-wave rectified currents (I.sub.C3, I.sub.C4). The differential pair circuit (40) includes a combining part (44) for combining the first and the second half-wave rectified currents into a full-wave rectified current (I.sub.RO). The full-wave rectifying circuit may further comprise a current/voltage converting section (50) for converting the full-wave rectified current into a full-wave rectified voltage (V.sub.RO).

Abstract: An absolute value circuit according to the present invention has a configuration wherein a switch is connected directly to an output of an amplifier and an output terminal. Owing to this configuration, the absolute value circuit can be realized which is capable of providing full-wave rectification with less distortion.

Abstract: Addition is performed by a capacitive coupling or resistive coupling. A quantizing circuit is realized by plurality of thresholding circuits receiving an analog input voltages. Subtraction is performed by to MOSs of anti-polarity inputted analog input voltages to gates.

Abstract: A signal processing circuit comprises a structure wherein emitters of a plurality of transistors are commonly connected, an inverting amplifier is connected to a base of each of the plurality of transistors, and an absolute value of an input signal supplied to the inverting amplifier is detected. The signal processing circuit has a compensating circuit to compensate a fluctuation of a voltage due to the plurality of transistors.

Abstract: A transition detector circuit produces an output pulse upon detection of a transition at any one of several input nodes using a single delay path so all input transitions produce the same output pulse width and with only one gate delay in the circuit. The circuit includes precharging means, coupled between the plurality of transitioning inputs and the output node, for charging the output node high. The precharging means comprises stacked field effect transistor (FET) devices, each having a gate connected to a respective one of the transitioning inputs. A first charging device for charging the output node high is coupled to the output node. A second charging device for discharging the output node low is coupled to the output node. A single delay means, coupled between the plurality of transitioning inputs and both the first and second charging devices, both turns off the first charging device and turns on the second charging device.

Abstract: A full wave rectifier includes an amplifier having a minus input, a plus input and an amplifier output; an input resistor connected between a circuit input and the minus input; and a current bridge having an output terminal connected to the circuit output, a first terminal connected to the minus input and a second terminal connected to the amplifier output. The current bridge includes a first current mirror circuit and a second current mirror circuit. The first current mirror circuit includes a first current source and a second current source, a source end of each current source of the first and second current sources being connected to the first terminal, a drain end of the first current source being connected to the second terminal and a drain end of the second current source being connected to the output terminal.

Abstract: A multi-level superposed amplitude-modulated baseband signal processor which has simple hardware structure and a filtering effect for bandwidth and power efficiency in a digital transmission system includes a data delayer, a signal level converter, an operator, two pulse generators, two adders and two amplifiers, thereby eliminating the need for conventionally required pulse waveforms and simplifying circuit structure. Specifically, when the number of the multi-levels is desired to be changed, the relevant multi-level superposed amplitude-modulated baseband signal can be provided by a simple change of the processor.

Abstract: An absolute value circuit for analog type processing combines an analog inverter circuit and a maximum circuit. The inverter circuit uses an operational amplifier comprised of CMOS inverters which are connected in a cascade with a gain of 1. The maximum circuit includes a pair of nMOS transistors, the source follower outputs of which are connected to a common output.